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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [mt45w8mw12/] [rtl/] [verilog/] [top.syn] - Rev 134
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module mt45w8mw12_def #( parameter ADDR_BITS = 23, parameter DQ_BITS = 16, parameter MEM_BITS = 16 ) ( input wire clk, input wire adv_n, input wire cre, output wire o_wait, input wire ce_n, input wire oe_n, input wire we_n, input wire lb_n, input wire ub_n, input wire [ADDR_BITS-1 : 0] addr, inout wire [DQ_BITS-1 : 0] dq ); reg [7:0] memoryl [1<<MEM_BITS-1:0]; reg [7:0] memoryu [1<<MEM_BITS-1:0]; reg [DQ_BITS-1 : 0] dq_out; // Write Memory // Read Memory always@(*) dq_out[7:0] = 8'h0; always@(*) dq_out[15:8] = 8'h0; // Tristate output // assign dq = (!ce_n && !oe_n) ? dq_out[DQ_BITS-1:0]: {DQ_BITS{1'bz}}; endmodule