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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [documentation.xml] - Rev 134
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<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Author : John Eaton Ouabache Designworks //
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>Testbench</spirit:library>
<spirit:name>toolflow</spirit:name>
<spirit:version>documentation</spirit:version>
<spirit:componentGenerators>
<spirit:componentGenerator>
<spirit:name>gen_verilog_doc</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Documentation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_auxiliary</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>html</spirit:name>
</spirit:parameter>
<spirit:parameter>
<spirit:name>top</spirit:name>
</spirit:parameter>
<spirit:parameter>
<spirit:name>interface_only</spirit:name>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../interfaces</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
</spirit:componentGenerators>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-doc</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../interfaces/doc/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-doc</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
</spirit:model>
</spirit:component>
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