Subversion Repositories socgen

<?xml version="1.0" encoding="utf-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
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//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
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//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
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//   This source is distributed in the hope that it will be               //
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//   details.                                                             //
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//   You should have received a copy of the GNU Lesser General            //
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-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org" 
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>Testbench</spirit:library>
<spirit:name>toolflow</spirit:name>
<spirit:version>ise</spirit:version>  

<spirit:componentGenerators>

<spirit:componentGenerator>
  <spirit:name>gen_verilogLib_syn</spirit:name>
  <spirit:phase>105.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>view</spirit:name>
      <spirit:value>syn</spirit:value>
    </spirit:parameter>
  </spirit:parameters>      
</spirit:componentGenerator>

</spirit:componentGenerators>

<spirit:fileSets>

   <spirit:fileSet>
      <spirit:name>fs-syn</spirit:name>

      <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../views/syn/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>

   </spirit:fileSet>

</spirit:fileSets>


<spirit:model>    

       <spirit:views>
              <spirit:view>
              <spirit:name>syn</spirit:name>
              <spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
              <spirit:fileSetRef><spirit:localName>fs-syn</spirit:localName></spirit:fileSetRef>
              </spirit:view>
      </spirit:views>

</spirit:model>       

</spirit:component>