Subversion Repositories socgen

<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
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//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
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//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
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//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
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-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org" 
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>Testbench</spirit:library>
<spirit:name>toolflow</spirit:name>
<spirit:version>verilator</spirit:version>  

<spirit:componentGenerators>


<spirit:componentGenerator>
  <spirit:name>gen_filelists</spirit:name>
  <spirit:phase>104.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions>
    <socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier>
  </spirit:vendorExtensions>
  <spirit:generatorExe>./tools/sys/gen_child_filelist</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>top_file</spirit:name>
      <spirit:value>"./TestBench"</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>top</spirit:name>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>


<spirit:componentGenerator>
  <spirit:name>gen_cov_filelist</spirit:name>
  <spirit:phase>104.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions>
    <socgen:envIdentifier>:*Lint:*</socgen:envIdentifier>
  </spirit:vendorExtensions>
  <spirit:generatorExe>./tools/sys/gen_child_filelist</spirit:generatorExe>
  <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>top_file</spirit:name>
      <spirit:value>"-v ./TestBench"</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>top</spirit:name>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>suffix</spirit:name>
      <spirit:value>COV</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>leader</spirit:name>
      <spirit:value>"-v "</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>






<spirit:componentGenerator>
  <spirit:name>gen_verilogLib_syn</spirit:name>
  <spirit:phase>105.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>view</spirit:name>
      <spirit:value>syn</spirit:value>
    </spirit:parameter>
  </spirit:parameters>      
</spirit:componentGenerator>



<spirit:componentGenerator>
  <spirit:name>gen_verilogLib_lint</spirit:name>
  <spirit:phase>105.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>:*Lint:*</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>view</spirit:name>
      <spirit:value>lint</spirit:value>
    </spirit:parameter>
  </spirit:parameters>      
</spirit:componentGenerator>







</spirit:componentGenerators>



<spirit:fileSets>


   <spirit:fileSet>
      <spirit:name>fs-syn</spirit:name>

      <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../views/syn/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>

   </spirit:fileSet>


   <spirit:fileSet>
      <spirit:name>fs-lint</spirit:name>

      <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../views/lint/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>

   </spirit:fileSet>






</spirit:fileSets>









<spirit:model>  

      <spirit:modelParameters>
        <spirit:modelParameter><spirit:name>PERIOD</spirit:name><spirit:value>40</spirit:value></spirit:modelParameter>
        <spirit:modelParameter><spirit:name>TIMEOUT</spirit:name><spirit:value>100000</spirit:value></spirit:modelParameter>
      </spirit:modelParameters>

    <spirit:views>

              <spirit:view>
              <spirit:name>Bfm</spirit:name>
              <spirit:hierarchyRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="clock_gen" 
                                   spirit:version="bfm.design"/>
              </spirit:view>


              <spirit:view>
              <spirit:name>syn</spirit:name>
              <spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
              <spirit:fileSetRef><spirit:localName>fs-syn</spirit:localName></spirit:fileSetRef>
              </spirit:view>



              <spirit:view>
              <spirit:name>lint</spirit:name>
              <spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
              <spirit:fileSetRef><spirit:localName>fs-lint</spirit:localName></spirit:fileSetRef>
              </spirit:view>





    </spirit:views>



    <spirit:ports>

      <spirit:port><spirit:name>clk</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        <spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
      </spirit:port>

      <spirit:port><spirit:name>START</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        <spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
      </spirit:port>


      <spirit:port><spirit:name>FAIL</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        <spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
      </spirit:port>


      <spirit:port><spirit:name>FINISH</spirit:name>
        <spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
        <spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
      </spirit:port>

    </spirit:ports>


</spirit:model>  



</spirit:component>