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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [doc/] [sch/] [cde_clock_gater.sch] - Rev 131

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v 20121203 2
C 1600 4300 1 0 0 in_port.sym
{
T 2100 4100 5 10 1 1 0 6 1
refdes=enable
}
C 1600 2800 1 0 0 in_port.sym
{
T 1900 2600 5 10 1 1 0 6 1
refdes=clk_in
}
C 1600 4700 1 0 0 in_port.sym
{
T 2300 5100 5 10 1 1 0 6 1
refdes=atg_clk_mode
}
C 8200 4300 1 0 0 out_port.sym
{
T 9200 4300 5 10 1 1 0 0 1
refdes=clk_out
}
C 4500 3000 1 0 0 latch.sym
{
T 6300 4800 5 10 0 0 0 0 1
device=LATCH
T 5800 5000 5 10 1 1 0 6 1
refdes=U?
}
C 6700 4100 1 0 0 and2-1.sym
{
T 7100 4000 5 10 1 1 0 2 1
refdes=U?
T 7100 4200 5 8 0 0 0 0 1
device=and
}
C 3000 3100 1 0 0 not-1.sym
{
T 3200 4100 5 10 0 0 0 0 1
device=not
T 3500 3400 5 10 1 1 0 2 1
refdes=U?
}
N 8200 4400 8000 4400 4
N 4100 3600 4500 3600 4
N 2500 2900 6700 2900 4
N 6700 4600 6100 4600 4
N 3000 3600 3000 2900 4
C 3000 4300 1 0 0 or2-1.sym
{
T 3400 4200 5 10 1 1 0 2 1
refdes=U?
T 3400 4400 5 8 0 0 0 0 1
device=or
}
N 3000 4400 2500 4400 4
N 3000 4800 2500 4800 4
N 4500 4600 4300 4600 4
N 6700 4200 6700 2900 4

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