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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_sys] - Rev 134
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reg [6:0] counter;
reg [3:0] reset_cnt;
always@(posedge ckIn or posedge pwron_reset)
if(pwron_reset) pwron_reset_n <= 1'b0;
else pwron_reset_n <= 1'b1;
generate
if( CLOCK_SRC)
begin
assign ckIn = b_clk_pad_in;
end
else
begin
assign ckIn = a_clk_pad_in;
end
endgenerate
generate
if( RESET_SENSE)
begin
assign pwron_reset = !pwron_pad_in;
end
else
begin
assign pwron_reset = pwron_pad_in;
end
endgenerate
always@(posedge ckIn or posedge pwron_reset)
if( pwron_reset) reset_cnt <= 4'b1111;
else
if(|reset_cnt) reset_cnt <= reset_cnt-4'b0001;
else reset_cnt <= 4'b0000;
always@(posedge ckIn or posedge pwron_reset)
if( pwron_reset) ref_reset <= 1'b1;
else ref_reset <= |reset_cnt;
always@(posedge dll_clk)
if(dll_reset)
begin
one_usec <= 1'b0;
counter <= FREQ*PLL_MULT/2;
end
else if(counter == 7'b0000001)
begin
one_usec <= !one_usec;
counter <= FREQ*PLL_MULT/2;
end
else
begin
one_usec <= one_usec;
counter <= counter -7'b0000001;
end