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localparam   MIN_CLK_DELAY = 0.01;
   

//****************************************************************************
// Measure the clock in period.  Use the and the multiplication
//   factor to determine the period for the output clock
//****************************************************************************
real  last_edge_time;
real  this_edge_time;   // $realtime when the input clock edges occur
real  ref_clk_period;   // input clock period
real  dll_clk_out_period;   // output clock period
real  clk_delay;

   
initial last_edge_time = 0;
initial dll_clk_out_period = 1;

always @(posedge ref_clk)
  begin
    this_edge_time   = $realtime;
    ref_clk_period   =  this_edge_time - last_edge_time;
    dll_clk_out_period   = (ref_clk_period) / MULT;
    last_edge_time   =  this_edge_time;
  end




   
//*****************************************************************************
//  Create a new clock
//*****************************************************************************


reg [SIZE-1:0]  divider;
   
   
initial
  begin
    dll_clk_out = 1'b0;
    forever
      begin
        clk_delay = (dll_clk_out_period/2);
        if (clk_delay < MIN_CLK_DELAY)    
        clk_delay = MIN_CLK_DELAY;
        #(clk_delay) dll_clk_out = ~dll_clk_out;
      end
  end

     
always@(posedge dll_clk_out or posedge reset  )
  if ( reset)                 divider   <= DIV/2;
  else if ( divider ==  'b1)  divider   <= DIV/2;
  else                        divider   <= divider - 'b1;
  
always@(posedge dll_clk_out  or posedge reset )
  if(reset)  div_clk_out                       <= 1'b0;
  else if   (divider ==  'b1)   div_clk_out    <= !div_clk_out;
  else       div_clk_out                       <= div_clk_out;