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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [syn/] [dll] - Rev 134
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always@(*)begindll_clk_out = ref_clk;endalways@(posedge ref_clk or posedge reset)if(reset) div_clk_out <= 1'b0;else div_clk_out <= !div_clk_out;