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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [verilog/] [divider_def] - Rev 134
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reg [SIZE-1:0] divide_cnt;always@(posedge clk)if(reset) divider_out <= RESET;elseif(!enable) divider_out <= 1'b0;else divider_out <= ( divide_cnt == SAMPLE );always@(posedge clk)if(reset) divide_cnt <= divider_in;elseif(!enable) divide_cnt <= divide_cnt;elseif(!(|divide_cnt)) divide_cnt <= divider_in;else divide_cnt <= divide_cnt - 'b1;