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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [doc/] [sch/] [cde_jtag_tap.sch] - Rev 135
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v 20100214 1
C 1500 300 1 0 0 in_port.sym
{
T 1500 300 5 10 1 1 0 6 1 1
refdes=trst_n_pad_in
}
C 1500 700 1 0 0 in_port.sym
{
T 1500 700 5 10 1 1 0 6 1 1
refdes=tms_pad_in
}
C 1500 1100 1 0 0 in_port.sym
{
T 1500 1100 5 10 1 1 0 6 1 1
refdes=tdo_i
}
C 1500 1500 1 0 0 in_port.sym
{
T 1500 1500 5 10 1 1 0 6 1 1
refdes=tdi_pad_in
}
C 1500 1900 1 0 0 in_port.sym
{
T 1500 1900 5 10 1 1 0 6 1 1
refdes=tclk_pad_in
}
C 1500 2300 1 0 0 in_port.sym
{
T 1500 2300 5 10 1 1 0 6 1 1
refdes=bsr_tdo_i
}
C 1500 2700 1 0 0 in_port.sym
{
T 1500 2700 5 10 1 1 0 6 1 1
refdes=aux_tdo_i
}
C 5300 300 1 0 0 out_port.sym
{
T 6300 300 5 10 1 1 0 0 1 1
refdes=update_dr_o
}
C 5300 700 1 0 0 out_port.sym
{
T 6300 700 5 10 1 1 0 0 1 1
refdes=update_dr_clk_o
}
C 5300 1100 1 0 0 out_port.sym
{
T 6300 1100 5 10 1 1 0 0 1 1
refdes=test_logic_reset_o
}
C 5300 1500 1 0 0 out_port.sym
{
T 6300 1500 5 10 1 1 0 0 1 1
refdes=tdo_pad_out
}
C 5300 1900 1 0 0 out_port.sym
{
T 6300 1900 5 10 1 1 0 0 1 1
refdes=tdo_pad_oe
}
C 5300 2300 1 0 0 out_port.sym
{
T 6300 2300 5 10 1 1 0 0 1 1
refdes=tdi_o
}
C 5300 2700 1 0 0 out_port.sym
{
T 6300 2700 5 10 1 1 0 0 1 1
refdes=tap_highz_mode
}
C 5300 3100 1 0 0 out_port.sym
{
T 6300 3100 5 10 1 1 0 0 1 1
refdes=shiftcapture_dr_clk_o
}
C 5300 3500 1 0 0 out_port.sym
{
T 6300 3500 5 10 1 1 0 0 1 1
refdes=shift_dr_o
}
C 5300 3900 1 0 0 out_port.sym
{
T 6300 3900 5 10 1 1 0 0 1 1
refdes=select_o
}
C 5300 4300 1 0 0 out_port.sym
{
T 6300 4300 5 10 1 1 0 0 1 1
refdes=jtag_clk
}
C 5300 4700 1 0 0 out_port.sym
{
T 6300 4700 5 10 1 1 0 0 1 1
refdes=capture_dr_o
}
C 5300 5100 1 0 0 out_port.sym
{
T 6300 5100 5 10 1 1 0 0 1 1
refdes=bsr_select_o
}
C 5300 5500 1 0 0 out_port.sym
{
T 6300 5500 5 10 1 1 0 0 1 1
refdes=bsr_output_mode
}
C 5300 5900 1 0 0 out_port.sym
{
T 6300 5900 5 10 1 1 0 0 1 1
refdes=aux_update_dr_clk_o
}
C 5300 6300 1 0 0 out_port.sym
{
T 6300 6300 5 10 1 1 0 0 1 1
refdes=aux_test_logic_reset_o
}
C 5300 6700 1 0 0 out_port.sym
{
T 6300 6700 5 10 1 1 0 0 1 1
refdes=aux_tdi_o
}
C 5300 7100 1 0 0 out_port.sym
{
T 6300 7100 5 10 1 1 0 0 1 1
refdes=aux_shiftcapture_dr_clk_o
}
C 5300 7500 1 0 0 out_port.sym
{
T 6300 7500 5 10 1 1 0 0 1 1
refdes=aux_shift_dr_o
}
C 5300 7900 1 0 0 out_port.sym
{
T 6300 7900 5 10 1 1 0 0 1 1
refdes=aux_select_o
}
C 5300 8300 1 0 0 out_port.sym
{
T 6300 8300 5 10 1 1 0 0 1 1
refdes=aux_capture_dr_o
}