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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [classic_rpc_reg] - Rev 134
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// shift buffer and shadowreg [BITS-1:0] buffer;always @(posedge shiftcapture_dr_clk or posedge test_logic_reset)if (test_logic_reset) buffer <= RESET_VALUE;elseif (select && capture_dr) buffer <= capture_value;elseif (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] };else buffer <= buffer;always @(posedge update_dr_clk or posedge test_logic_reset)if (test_logic_reset) update_value <= RESET_VALUE;elseif (select) update_value <= buffer;else update_value <= update_value;assign tdo = buffer[0];