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   reg                    synced_reset;

   always@(posedge clk or posedge test_logic_reset  )
   if(test_logic_reset)
      begin
      synced_reset <= 1'b1;
      syn_reset    <= 1'b1;
      end
   else
      begin
      synced_reset <= test_logic_reset; 
      syn_reset    <= synced_reset;
      end
   

   reg                    synced_shift_dr;
   reg                    synced_capture_dr;


   
   
   always@(posedge clk)
     if(!shiftcapture_dr_clk)
       begin
       synced_shift_dr    <= shift_dr ;
       synced_capture_dr  <= capture_dr ;
       end
     
     else
       begin
       synced_shift_dr    <= synced_shift_dr ;
       synced_capture_dr  <= synced_capture_dr ;
       end


   reg [1:0]  synced_shiftcapture_dr_clk;
   

   always@(posedge clk)       
     synced_shiftcapture_dr_clk <= {synced_shiftcapture_dr_clk[0],shiftcapture_dr_clk};


   reg [1:0]  synced_update_dr_clk;
   

   always@(posedge clk)       
     synced_update_dr_clk <= {synced_update_dr_clk[0],update_dr_clk};
   


   always@(posedge clk)
     if(synced_shiftcapture_dr_clk == 2'b01)
       begin
       syn_shift_dr      <= synced_shift_dr ;
       syn_capture_dr    <= synced_capture_dr ;
       end
     else
       begin
       syn_shift_dr      <= 1'b0 ;
       syn_capture_dr    <= 1'b0 ;
       end


   
   always@(posedge clk)
     if(synced_update_dr_clk == 2'b01)
       begin
       syn_update_dr      <= 1'b1 ;
       end
     else
       begin
       syn_update_dr      <= 1'b0 ;
       end



   always@(posedge clk)
     if(!shiftcapture_dr_clk && (shift_dr || capture_dr  ))
       begin
       syn_tdi_o         <= tdi ;
       end
     
     else
       begin
       syn_tdi_o         <= syn_tdi_o ;
       end


   





   

   always@(posedge clk)
     if(synced_update_dr_clk == 2'b01)
       begin
       syn_select      <= select;
       end
   else if(synced_shiftcapture_dr_clk == 2'b01)
       begin
       syn_select      <= select;         
       end
   
     else
       begin
       syn_select      <= syn_select;     
       end

   


   



   assign    syn_clk             = clk;
   assign    tdo                 = syn_tdo_i;