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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Rev 131
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<?xml version="1.0" encoding="utf-8"?>
<!--
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>jtag</spirit:name>
<spirit:version>tap</spirit:version> <spirit:configuration>default</spirit:configuration>
<spirit:busInterfaces>
<spirit:busInterface><spirit:name>jtag</spirit:name>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="cde" spirit:name="jtag" spirit:version="rpc_classic_rtl"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort><spirit:name>test_logic_reset</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>test_logic_reset_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>capture_dr</spirit:name></spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>capture_dr_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>shift_dr</spirit:name></spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>shift_dr_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>update_dr_clk</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>update_dr_clk_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>tdi</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tdi_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>tdo</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>tdo_i</spirit:name>
<spirit:wire><spirit:vector><spirit:left>JTAG_SEL-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>select</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>select_o</spirit:name>
<spirit:wire><spirit:vector><spirit:left>JTAG_SEL-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>shiftcapture_dr_clk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort><spirit:name>shiftcapture_dr_clk_o</spirit:name>
<spirit:wire></spirit:wire>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface><spirit:name>tclk_pad</spirit:name>
<spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="def"/>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="rtl"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort><spirit:name>pad_in</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tclk_pad_in</spirit:name></spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface><spirit:name>tdi_pad</spirit:name>
<spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="def"/>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="rtl"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort><spirit:name>pad_in</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tdi_pad_in</spirit:name></spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface><spirit:name>tms_pad</spirit:name>
<spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="def"/>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="rtl"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort><spirit:name>pad_in</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tms_pad_in</spirit:name></spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface><spirit:name>trst_n_pad</spirit:name>
<spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="def"/>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="rtl"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort><spirit:name>pad_in</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>trst_n_pad_in</spirit:name></spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface><spirit:name>tdo_pad</spirit:name>
<spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="def"/>
<spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="pad" spirit:version="rtl"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort><spirit:name>pad_out</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tdo_pad_out</spirit:name></spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort><spirit:name>pad_oe</spirit:name></spirit:logicalPort>
<spirit:physicalPort><spirit:name>tdo_pad_oe</spirit:name></spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:componentGenerators>
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_sim</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>sim</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
<spirit:componentGenerator>
<spirit:name>gen_verilogLib_syn</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:vendorExtensions><socgen:envIdentifier>:*Synthesis:*</socgen:envIdentifier></spirit:vendorExtensions>
<spirit:generatorExe>./tools/verilog/gen_verilogLib</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>view</spirit:name>
<spirit:value>syn</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
</spirit:componentGenerators>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>Hierarchical</spirit:name>
<spirit:hierarchyRef spirit:vendor="opencores.org"
spirit:library="cde"
spirit:name="jtag"
spirit:version="def.design"/>
</spirit:view>
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
</spirit:views>
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>JTAG_SEL</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INST_LENGTH</spirit:name><spirit:value>4</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INST_RETURN</spirit:name><spirit:value>4'b1101</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INST_RESET</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CHIP_ID_VAL</spirit:name><spirit:value>32'h12345678</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>NUM_USER</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>EXTEST</spirit:name><spirit:value>4'b0000</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>USER</spirit:name><spirit:value>8'b1010_1001</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>SAMPLE</spirit:name><spirit:value>4'b0001</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>HIGHZ_MODE</spirit:name><spirit:value>4'b0010</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CHIP_ID_ACCESS</spirit:name><spirit:value>4'b0011</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>CLAMP</spirit:name><spirit:value>4'b1000</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RPC_DATA</spirit:name><spirit:value>4'b1010</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RPC_ADD</spirit:name><spirit:value>4'b1001</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>BYPASS</spirit:name><spirit:value>4'b1111</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
<spirit:ports>
<spirit:port><spirit:name>tap_highz_mode</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>bsr_output_mode</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>bsr_tdo_i</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>jtag_clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>update_dr_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
<spirit:port><spirit:name>bsr_select_o</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/jtag_tap</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/sim/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/SYNTHESYS</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/jtag_tap</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName>
<spirit:name>../verilog/syn/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
</spirit:component>
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