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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [jtag_classic_rpc_in_reg_dutg.design.xml] - Rev 135
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<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Generated File Do Not EDIT //
// //
// regen by adding -tb to gen_verilog script //
// //
-->
<ipxact:design
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>opencores.org</ipxact:vendor>
<ipxact:library>cde</ipxact:library>
<ipxact:name>jtag</ipxact:name>
<ipxact:version>classic_rpc_in_reg_dutg.design</ipxact:version>
<ipxact:adHocConnections>
<ipxact:adHocConnection>
<ipxact:name>capture_dr</ipxact:name>
<ipxact:externalPortReference portRef="capture_dr" />
<ipxact:internalPortReference componentRef="dut" portRef="capture_dr" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>capture_value</ipxact:name>
<ipxact:externalPortReference portRef="capture_value" left="BITS-1" right="0" />
<ipxact:internalPortReference componentRef="dut" portRef="capture_value" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>select</ipxact:name>
<ipxact:externalPortReference portRef="select" />
<ipxact:internalPortReference componentRef="dut" portRef="select" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>shift_dr</ipxact:name>
<ipxact:externalPortReference portRef="shift_dr" />
<ipxact:internalPortReference componentRef="dut" portRef="shift_dr" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>shiftcapture_dr_clk</ipxact:name>
<ipxact:externalPortReference portRef="shiftcapture_dr_clk" />
<ipxact:internalPortReference componentRef="dut" portRef="shiftcapture_dr_clk" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>tdi</ipxact:name>
<ipxact:externalPortReference portRef="tdi" />
<ipxact:internalPortReference componentRef="dut" portRef="tdi" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>tdo</ipxact:name>
<ipxact:externalPortReference portRef="tdo" />
<ipxact:internalPortReference componentRef="dut" portRef="tdo" />
</ipxact:adHocConnection>
<ipxact:adHocConnection>
<ipxact:name>test_logic_reset</ipxact:name>
<ipxact:externalPortReference portRef="test_logic_reset" />
<ipxact:internalPortReference componentRef="dut" portRef="test_logic_reset" />
</ipxact:adHocConnection>
</ipxact:adHocConnections>
<ipxact:componentInstances>
<ipxact:componentInstance>
<ipxact:instanceName>dut</ipxact:instanceName>
<ipxact:componentRef vendor="opencores.org" library="cde" name="jtag" version="classic_rpc_in_reg" />
<ipxact:configurableElementValues>
<ipxact:configurableElementValue referenceId="BITS">BITS</ipxact:configurableElementValue>
<ipxact:configurableElementValue referenceId="RESET_VALUE">RESET_VALUE</ipxact:configurableElementValue>
</ipxact:configurableElementValues>
</ipxact:componentInstance>
</ipxact:componentInstances>
</ipxact:design>