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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [verilog/] [top.64] - Rev 135
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io_probe_in
#(.MESG ("multiply error"),
.WIDTH (32)
)
rdata_tpb
(
.clk ( clk ),
.expected_value ( mul_prod_exp[31:0] ),
.mask ( {32{mask}} ),
.signal ( mul_prod_r[31:0] )
);
`ifndef SYNTHESIS
task u_cmp;
input [31:0] a_in;
input [31:0] b_in;
input [31:0] exp;
begin
test.a_in <= a_in;
test.b_in <= b_in;
test.mul_prod_exp <= exp;
test.alu_op_mul <= 1'b1;
test.ex_freeze <= 1'b1;
test.cg.next(1);
while(mul_stall) test.cg.next(1);
test.mask <= 1'b1;
$display("%t %m cycle %x %x %x",$realtime,a_in,b_in,exp );
test.alu_op_mul <= 1'b0;
test.ex_freeze <= 1'b0;
test.cg.next(1);
test.mask <= 1'b0;
end
endtask
`endif
assign STOP = 1'b0;
assign BAD = 1'b0;