Subversion Repositories socgen

<?xml version="1.0" encoding="utf-8"?>
<!--

-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>mult</spirit:name>
<spirit:version>ord_r4_lint</spirit:version>  




<spirit:componentGenerators>

<spirit:componentGenerator>
  <spirit:name>elab_verilog</spirit:name>
  <spirit:phase>103.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
  <spirit:generatorExe>./tools/verilog/elab_verilog</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>configuration</spirit:name>
      <spirit:value>default</spirit:value>
    </spirit:parameter>
    <spirit:parameter> 
      <spirit:name>dest_dir</spirit:name>
      <spirit:value>io_ports</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>

<spirit:componentGenerator>
  <spirit:name>gen_design</spirit:name>
  <spirit:phase>103.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>:*Simulation:*</socgen:envIdentifier></spirit:vendorExtensions
>
  <spirit:generatorExe>./tools/verilog/gen_design</spirit:generatorExe>
    <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>dest_dir</spirit:name>
      <spirit:value>io_ports</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>

</spirit:componentGenerators>





<spirit:model>    
       <spirit:views>



              <spirit:view>
              <spirit:name>Dut</spirit:name>
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="cde" 
                                   spirit:name="mult" 
                                   spirit:version="ord_r4_dut.params"/>
              </spirit:vendorExtensions>
              </spirit:view>



              <spirit:view>
              <spirit:name>lint</spirit:name>
              <spirit:envIdentifier>:*Lint:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:fileSetRef><spirit:localName>fs-lint</spirit:localName></spirit:fileSetRef>
              </spirit:view>



              <spirit:view>
              <spirit:name>rtl_check</spirit:name>              
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="rtl_check"/> 
              </spirit:vendorExtensions>
              </spirit:view>

      </spirit:views>



</spirit:model>    



<spirit:fileSets>


   <spirit:fileSet>
      <spirit:name>fs-common</spirit:name>

   </spirit:fileSet>



   <spirit:fileSet>
      <spirit:name>fs-lint</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/synthesys</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>include</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/lint/mult_ord_r4_lint</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


   </spirit:fileSet>




</spirit:fileSets>



</spirit:component>