URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [sim/] [testbenches/] [xml/] [serial_xmit_dutg.design.xml] - Rev 135
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<?xml version="1.0" encoding="UTF-8"?><!--// //// Generated File Do Not EDIT //// //// regen by adding -tb to gen_verilog script //// //--><ipxact:designxmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"xmlns:socgen="http://opencores.org"xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd"><ipxact:vendor>opencores.org</ipxact:vendor><ipxact:library>cde</ipxact:library><ipxact:name>serial</ipxact:name><ipxact:version>xmit_dutg.design</ipxact:version><ipxact:adHocConnections><ipxact:adHocConnection><ipxact:name>buffer_empty</ipxact:name><ipxact:externalPortReference portRef="buffer_empty" /><ipxact:internalPortReference componentRef="dut" portRef="buffer_empty" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>clk</ipxact:name><ipxact:externalPortReference portRef="clk" /><ipxact:internalPortReference componentRef="dut" portRef="clk" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>data</ipxact:name><ipxact:externalPortReference portRef="data" left="WIDTH-1" right="0" /><ipxact:internalPortReference componentRef="dut" portRef="data" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>edge_enable</ipxact:name><ipxact:externalPortReference portRef="edge_enable" /><ipxact:internalPortReference componentRef="dut" portRef="edge_enable" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>load</ipxact:name><ipxact:externalPortReference portRef="load" /><ipxact:internalPortReference componentRef="dut" portRef="load" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>parity_enable</ipxact:name><ipxact:externalPortReference portRef="parity_enable" /><ipxact:internalPortReference componentRef="dut" portRef="parity_enable" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>parity_force</ipxact:name><ipxact:externalPortReference portRef="parity_force" /><ipxact:internalPortReference componentRef="dut" portRef="parity_force" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>parity_type</ipxact:name><ipxact:externalPortReference portRef="parity_type" /><ipxact:internalPortReference componentRef="dut" portRef="parity_type" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>reset</ipxact:name><ipxact:externalPortReference portRef="reset" /><ipxact:internalPortReference componentRef="dut" portRef="reset" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>ser_out</ipxact:name><ipxact:externalPortReference portRef="ser_out" /><ipxact:internalPortReference componentRef="dut" portRef="ser_out" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>start_value</ipxact:name><ipxact:externalPortReference portRef="start_value" /><ipxact:internalPortReference componentRef="dut" portRef="start_value" /></ipxact:adHocConnection><ipxact:adHocConnection><ipxact:name>stop_value</ipxact:name><ipxact:externalPortReference portRef="stop_value" /><ipxact:internalPortReference componentRef="dut" portRef="stop_value" /></ipxact:adHocConnection></ipxact:adHocConnections><ipxact:componentInstances><ipxact:componentInstance><ipxact:instanceName>dut</ipxact:instanceName><ipxact:componentRef vendor="opencores.org" library="cde" name="serial" version="xmit" /><ipxact:configurableElementValues><ipxact:configurableElementValue referenceId="WIDTH">WIDTH</ipxact:configurableElementValue><ipxact:configurableElementValue referenceId="SIZE">SIZE</ipxact:configurableElementValue></ipxact:configurableElementValues></ipxact:componentInstance></ipxact:componentInstances></ipxact:design>
