Subversion Repositories socgen

<?xml version="1.0" encoding="UTF-8"?>
<!--

-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>sram</spirit:name>
<spirit:version>def</spirit:version>  <spirit:configuration>default</spirit:configuration>  



<spirit:busInterfaces>

 <spirit:busInterface><spirit:name>slave_clk</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="clock" spirit:version="rtl"/>
  <spirit:slave/>
    <spirit:portMaps>
      <spirit:portMap>
        <spirit:logicalPort><spirit:name>clk</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>clk</spirit:name></spirit:physicalPort>
      </spirit:portMap>
    </spirit:portMaps>
 </spirit:busInterface>


 <spirit:busInterface><spirit:name>mem</spirit:name>
  <spirit:busType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="def"/>
  <spirit:abstractionType spirit:vendor="opencores.org" spirit:library="Busdefs" spirit:name="micro_bus" spirit:version="rtl"/>
  <spirit:slave>
  <spirit:memoryMapRef spirit:memoryMapRef="mem"/>
  </spirit:slave>
    <spirit:portMaps>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>cs</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>cs</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>wr</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>wr</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

      <spirit:portMap>
        <spirit:logicalPort><spirit:name>rd</spirit:name></spirit:logicalPort>
        <spirit:physicalPort><spirit:name>rd</spirit:name>
        </spirit:physicalPort>
      </spirit:portMap>

    </spirit:portMaps>
 </spirit:busInterface>

</spirit:busInterfaces>


<spirit:model>    
       <spirit:views>

              <spirit:view>
              <spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-sim</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>

              <spirit:view>
              <spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-syn</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>


              <spirit:view>
              <spirit:name>lint</spirit:name><spirit:envIdentifier>lint</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-lint</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>





              <spirit:view>
              <spirit:name>doc</spirit:name>
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="documentation"/> 
              </spirit:vendorExtensions>
              <spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              </spirit:view>




      </spirit:views>



<spirit:modelParameters>
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter>
</spirit:modelParameters>

<spirit:ports>



<spirit:port><spirit:name>cs</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>addr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>ADDR-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>wdata</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>rdata</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>



</spirit:ports>

</spirit:model>    







<spirit:fileSets>




   <spirit:fileSet>
      <spirit:name>fs-sim</spirit:name>



       <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>



  </spirit:fileSet>


   <spirit:fileSet>
      <spirit:name>fs-syn</spirit:name>



       <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>




   </spirit:fileSet>



   <spirit:fileSet>
      <spirit:name>fs-lint</spirit:name>


       <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>




   </spirit:fileSet>





</spirit:fileSets>





<spirit:memoryMaps>


 <spirit:memoryMap>
  <spirit:name>mem</spirit:name>
  <spirit:addressUnitBits>8</spirit:addressUnitBits>
   <spirit:bank>
     <spirit:name>mem</spirit:name>
     <spirit:baseAddress>0x0000</spirit:baseAddress>
      <spirit:addressBlock>
       <spirit:name>mem</spirit:name>
     </spirit:addressBlock>
   </spirit:bank>

 </spirit:memoryMap>

</spirit:memoryMaps>




</spirit:component>