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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [verilog/] [sync_def] - Rev 134
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reg [WIDTH - 1:0] sync_data [DEPTH:0];always @(*)beginsync_data[0] = data_in;endinteger i;always @(posedge clk)beginfor (i = 1 ; i <= DEPTH ; i = i + 1) sync_data[i] <= sync_data[i-1];endassign data_out = sync_data[DEPTH];