Subversion Repositories socgen

v 20110115 2
C 56000 51800 1 0 0 reg_rst.sym
{
T 57800 53600 5 10 0 0 0 0 1
device=REGISTER_RST
T 57300 53800 5 10 1 1 0 6 1
refdes=U?
}
B 56000 48800 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 62400 49000 9 10 1 0 0 0 2
ACTIVE LOW
RESET
B 53200 41500 21200 13100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
C 54600 45600 1 0 0 high-1.sym
{
T 54900 45900 5 10 0 1 0 0 1
device=HIGH
T 54800 45800 5 10 1 1 0 0 1
refdes=H?
}
C 56100 43400 1 0 0 low-1.sym
{
T 56500 43400 5 10 0 1 0 0 1
device=LOW
T 56400 43600 5 10 1 1 0 0 1
refdes=G?
}
C 53800 49900 1 0 0 pullup-1.sym
{
T 54000 50000 5 10 1 1 0 0 1
refdes=H?
}
C 53800 50700 1 0 0 pulldown-1.sym
{
T 54000 50800 5 10 1 1 0 0 1
refdes=G?
}
C 54400 51500 1 0 0 ipad-1.sym
{
T 54484 51721 5 10 0 1 0 0 1
device=IPAD
T 54400 51800 5 10 1 1 0 0 1
refdes=TRST_n
}
N 53900 51000 53900 51600 4
N 53900 51600 54400 51600 4
N 55300 51600 56800 51600 4
N 56800 51600 56800 51800 4
C 54500 49500 1 0 0 ipad-1.sym
{
T 54584 49721 5 10 0 1 0 0 1
device=IPAD
T 54500 49800 5 10 1 1 0 0 1
refdes=CLK_RST_n
}
N 55400 49600 56000 49600 4
N 53900 49200 53900 49900 4
N 53900 49600 54500 49600 4
T 56100 49300 9 10 1 0 0 0 3
Metastable 
      filter 
        inv
C 56500 43700 1 90 0 asic-cap-2.sym
{
T 56100 44700 5 8 0 0 90 0 1
device=CAPACITOR
T 56100 43800 5 10 1 1 90 0 1
refdes=C?
T 56100 44300 5 10 1 1 90 0 1
value=1n
}
C 54100 48300 1 90 0 asic-cap-2.sym
{
T 53700 49300 5 8 0 0 90 0 1
device=CAPACITOR
T 53700 48400 5 10 1 1 90 0 1
refdes=C?
T 53700 48900 5 10 1 1 90 0 1
value=1n
}
C 53700 48000 1 0 0 low-1.sym
{
T 54100 48000 5 10 0 1 0 0 1
device=LOW
T 54000 48200 5 10 1 1 0 0 1
refdes=G?
}
C 56200 45300 1 0 0 pullup-1.sym
{
T 56400 45400 5 10 1 1 0 0 1
refdes=H?
}
N 56300 44600 56300 45300 4
N 56300 45000 57200 45000 4
C 57200 44900 1 0 0 ipad-1.sym
{
T 57284 45121 5 10 0 1 0 0 1
device=IPAD
T 57200 45200 5 10 1 1 0 0 1
refdes=PWR_ON
}
C 58200 49600 1 0 0 or2-1.sym
{
T 58600 49500 5 10 1 1 0 2 1
refdes=U?
T 58600 49700 5 8 0 0 0 0 1
device=or
}
N 58200 49700 57300 49700 4
N 57600 53400 58200 53400 4
N 58200 53400 58200 50100 4
C 54500 43700 1 0 0 low-1.sym
{
T 54900 43700 5 10 0 1 0 0 1
device=LOW
T 54800 43900 5 10 1 1 0 0 1
refdes=G?
}
B 54100 44000 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 54400 44800 9 10 1 0 0 0 2
  Power
Monitor
N 56300 45000 55400 45000 4
B 58400 44200 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 58500 44700 9 10 1 0 0 0 3
Metastable 
      filter 
        inv
N 60300 49900 59500 49900 4
N 60300 49500 59900 49500 4
N 59900 49500 59900 45000 4
N 59900 45000 59700 45000 4
N 59900 49900 59900 53600 4
N 59900 53600 62200 53600 4
T 60800 53700 9 20 1 0 0 0 1
clkdiv_reset
C 60300 49400 1 0 0 nor2-1.sym
{
T 60700 49300 5 10 1 1 0 2 1
refdes=U?
T 60700 49500 5 8 0 0 0 0 1
device=nor
}
C 62800 49800 1 0 0 reg_rst.sym
{
T 64600 51600 5 10 0 0 0 0 1
device=REGISTER_RST
T 64100 51800 5 10 1 1 0 6 1
refdes=U?
}
C 64800 49800 1 0 0 reg_rst.sym
{
T 66600 51600 5 10 0 0 0 0 1
device=REGISTER_RST
T 66100 51800 5 10 1 1 0 6 1
refdes=U?
}
C 66700 49800 1 0 0 reg_rst.sym
{
T 68500 51600 5 10 0 0 0 0 1
device=REGISTER_RST
T 68000 51800 5 10 1 1 0 6 1
refdes=U?
}
C 68500 49800 1 0 0 reg_rst.sym
{
T 70300 51600 5 10 0 0 0 0 1
device=REGISTER_RST
T 69800 51800 5 10 1 1 0 6 1
refdes=U?
}
C 70400 48900 1 0 0 and2-1.sym
{
T 70800 48800 5 10 1 1 0 2 1
refdes=U?
T 70800 49000 5 8 0 0 0 0 1
device=and
}
C 71700 47600 1 0 0 reg_rst.sym
{
T 73500 49400 5 10 0 0 0 0 1
device=REGISTER_RST
T 73000 49600 5 10 1 1 0 6 1
refdes=U?
}
C 70400 46700 1 0 0 and2-1.sym
{
T 70800 46600 5 10 1 1 0 2 1
refdes=U?
T 70800 46800 5 8 0 0 0 0 1
device=and
}
C 71700 45400 1 0 0 reg_rst.sym
{
T 73500 47200 5 10 0 0 0 0 1
device=REGISTER_RST
T 73000 47400 5 10 1 1 0 6 1
refdes=U?
}
V 62000 49700 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 61800 49600 9 10 1 0 0 0 1
DFT
N 69300 49800 69300 49700 4
N 69300 49700 62400 49700 4
N 63600 49800 63600 49700 4
N 65600 49800 65600 49700 4
N 64800 51400 64400 51400 4
N 66700 51400 66400 51400 4
N 68500 51400 68300 51400 4
N 70100 47200 70100 51400 4
N 70100 49400 70400 49400 4
N 70400 47200 70100 47200 4
N 70400 49000 69200 49000 4
N 70400 46800 69200 46800 4
N 72500 47600 63600 47600 4
N 63600 45400 63600 49700 4
N 72500 45400 63600 45400 4
C 62700 51400 1 0 0 high-1.sym
{
T 63000 51700 5 10 0 1 0 0 1
device=HIGH
T 62700 51900 5 10 1 1 0 0 1
refdes=H?
}
C 67600 47400 1 0 0 reg.sym
{
T 69400 49200 5 10 0 0 0 0 1
device=REGISTER
T 68900 49400 5 10 1 1 0 6 1
refdes=U?
}
C 67600 45200 1 0 0 reg.sym
{
T 69400 47000 5 10 0 0 0 0 1
device=REGISTER
T 68900 47200 5 10 1 1 0 6 1
refdes=U?
}
N 67500 49800 67500 49700 4
T 72800 44900 9 10 1 0 0 0 3
ACTIVE LOW
RESETS TO
COMPONENTS
N 73300 49200 74100 49200 4
N 73300 47000 74100 47000 4
T 62900 52300 9 25 1 0 0 0 1
Synchronous Reset Distribution Tree
T 67400 44300 9 25 1 0 0 0 2
Soft Reset 
 Sources
T 53400 52600 9 25 1 0 0 0 2
JTAG RPC
CONTROL
T 54900 47800 9 25 1 0 0 0 2
SIM/TEST
   RESET
T 64500 42100 9 40 1 0 0 0 1
Modern ASIC Reset System
C 58100 42900 1 0 1 out_port.sym
{
T 57798 43118 5 10 0 1 0 6 1
device=OPAD
T 57200 43200 5 10 1 1 0 0 1
refdes=PWR_ON
}
N 57000 45000 57000 43000 4
N 57000 43000 57200 43000 4
B 58400 42400 1300 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
N 58100 43000 58400 43000 4
T 58600 43100 9 10 1 0 0 0 1
WatchDog
N 58100 45000 58400 45000 4
T 53600 42000 9 25 1 0 0 0 2
PCA PWR
 RESET