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[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [reset_fig2.sch] - Rev 27

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v 20100214 2
C 58200 44800 1 0 0 frame_800x600.sym
C 59100 46000 1 0 0 reg_rst.sym
{
T 60900 47800 5 10 0 0 0 0 1
device=REGISTER_RST
T 60400 48000 5 10 1 1 0 6 1
refdes=U?
}
C 64900 49100 1 0 0 reg_rst.sym
{
T 66700 50900 5 10 0 0 0 0 1
device=REGISTER_RST
T 66200 51100 5 10 1 1 0 6 1
refdes=U?
}
C 63600 47300 1 0 0 and2-1.sym
{
T 64000 47200 5 10 1 1 0 2 1
refdes=U?
T 64000 47400 5 8 0 0 0 0 1
device=and
}
T 63700 46300 9 10 1 0 0 0 3
ASYNCHRONOUS
 DFT CONTROL
       LOGIC
C 62300 47500 1 0 0 or2-1.sym
{
T 62700 47400 5 10 1 1 0 2 1
refdes=U?
T 62700 47600 5 8 0 0 0 0 1
device=or
}
N 60700 47600 62300 47600 4
N 63600 47400 63400 47400 4
N 63400 47400 63400 45700 4
N 58700 45700 63400 45700 4
N 59900 45700 59900 46000 4
N 64900 47600 65700 47600 4
N 65700 47600 65700 49100 4
N 62300 48000 62300 49000 4
N 62300 49000 58700 49000 4
T 58800 49100 9 10 1 0 0 0 1
ATG_ASYNCDISABLE
T 58700 45800 9 10 1 0 0 0 1
RESET_N
B 62000 46900 3200 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 60600 47800 9 10 1 0 0 0 2
ACTIVE LOW
RESET

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