Subversion Repositories socgen

v 20100214 2
C 48900 14100 1 0 0 frame_800x600.sym
B 52000 17400 800 2300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 50100 18100 1400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 52100 18500 9 10 1 0 0 0 3
 BFM
MODEL

T 50100 18600 9 10 1 0 0 0 2
 TEST_DEFINE

L 51500 18900 52000 18900 3 0 0 0 -1 -1
L 51500 18800 52000 18800 3 0 0 0 -1 -1
L 52000 18800 51900 18700 3 0 0 0 -1 -1
L 52000 18900 51900 19000 3 0 0 0 -1 -1
L 52800 19500 53100 19500 3 0 0 0 -1 -1
L 52800 19400 53100 19400 3 0 0 0 -1 -1
T 53200 19600 9 10 1 0 0 0 1
TIMED_DRIVER
B 53100 18900 1800 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 55500 17000 1700 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 54900 17700 55000 17800 3 0 0 0 -1 -1
L 54900 17600 55000 17500 3 0 0 0 -1 -1
T 56100 18700 9 16 1 0 0 0 1
DUT
T 49200 20300 9 20 1 0 0 0 1
GATE SIMS
L 53100 19400 53000 19300 3 0 0 0 -1 -1
L 53100 19500 53000 19600 3 0 0 0 -1 -1
L 54900 19500 55500 19500 3 0 0 0 -1 -1
L 54900 19400 55500 19400 3 0 0 0 -1 -1
L 55500 19400 55400 19300 3 0 0 0 -1 -1
L 55500 19500 55400 19600 3 0 0 0 -1 -1
L 52800 18000 53100 18000 3 0 0 0 -1 -1
L 52800 17900 53100 17900 3 0 0 0 -1 -1
B 53100 17100 1800 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 54900 17700 55500 17700 3 0 0 0 -1 -1
L 54900 17600 55500 17600 3 0 0 0 -1 -1
T 53200 17800 9 10 1 0 0 0 1
TIMED_TESTER
L 51500 18900 51600 19000 3 0 0 0 -1 -1
L 51500 18800 51600 18700 3 0 0 0 -1 -1
L 53100 17900 53000 17800 3 0 0 0 -1 -1
L 53100 18000 53000 18100 3 0 0 0 -1 -1
B 50100 14900 1300 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 50100 15400 9 10 1 0 0 0 2
 CLOCK_GEN

B 51400 15400 1500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 51500 15400 9 10 1 0 0 0 2
 TIMING_GEN

B 51400 14900 1500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 51500 14900 9 10 1 0 0 0 2
 TIMING_GEN

B 51400 15900 1500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 51500 15900 9 10 1 0 0 0 2
 TIMING_GEN

T 53000 16100 9 10 1 0 0 0 1
CLK_TGEN
T 53000 15600 9 10 1 0 0 0 1
IN_TGEN
T 53000 15100 9 10 1 0 0 0 1
OUT_TGEN
L 53100 17200 51200 17200 3 0 0 0 -1 -1
L 51200 17200 51400 17300 3 0 0 0 -1 -1
L 51200 17200 51400 17100 3 0 0 0 -1 -1
T 50300 17100 9 10 1 0 0 0 1
FAILURE
L 52800 17600 52900 17700 3 0 0 0 -1 -1
L 52800 17500 52900 17400 3 0 0 0 -1 -1
L 52800 17600 53100 17600 3 0 0 0 -1 -1
L 52800 17500 53100 17500 3 0 0 0 -1 -1
T 52500 19400 9 10 1 0 0 0 1
out
T 52200 17900 9 10 1 0 0 0 1
expect
T 52200 17500 9 10 1 0 0 0 1
actual
T 53200 16700 9 10 1 0 0 0 1
mask
L 53400 16900 53400 17100 3 0 0 0 -1 -1
L 53400 17100 53300 17000 3 0 0 0 -1 -1
L 53400 17100 53500 17000 3 0 0 0 -1 -1
L 54500 16900 54500 17100 3 0 0 0 -1 -1
L 54500 17100 54400 17000 3 0 0 0 -1 -1
L 54500 17100 54600 17000 3 0 0 0 -1 -1
T 54300 16700 9 10 1 0 0 0 1
in_tgen
L 54500 18700 54500 18900 3 0 0 0 -1 -1
L 54500 18900 54400 18800 3 0 0 0 -1 -1
L 54500 18900 54600 18800 3 0 0 0 -1 -1
T 54300 18500 9 10 1 0 0 0 1
out_tgen