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[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [ver_fig4.sch] - Rev 65

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v 20100214 2
C 48900 14100 1 0 0 frame_800x600.sym
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 BFM
MODEL

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 TEST_DEFINE

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TIMED_DRIVER
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DUT
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GATE SIMS
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TIMED_TESTER
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 CLOCK_GEN

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 TIMING_GEN

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 TIMING_GEN

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 TIMING_GEN

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CLK_TGEN
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IN_TGEN
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OUT_TGEN
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FAILURE
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out
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expect
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actual
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mask
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in_tgen
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T 54300 18500 9 10 1 0 0 0 1
out_tgen

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