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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] [ver_fig5.sch] - Rev 99
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v 20100214 2
C 57800 33600 1 0 0 frame_800x600.sym
B 61400 33900 2000 5500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 58400 36700 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 58500 37300 9 10 1 0 0 0 1
REG
L 59000 37100 61400 37100 3 0 0 0 -1 -1
T 61500 39500 9 10 1 0 0 0 2
RTL COMP
DUT
B 58300 38400 1400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 58400 38800 9 10 1 0 0 0 1
CLOCK_GEN
L 59700 38900 61400 38900 3 0 0 0 -1 -1
L 59700 38600 61400 38600 3 0 0 0 -1 -1
T 60100 39000 9 10 1 0 0 0 1
CLK
T 59900 38700 9 10 1 0 0 0 1
RESET
T 58100 37600 9 10 1 0 0 0 1
SIG_1_DRV
T 59900 36800 9 10 1 0 0 0 1
WIRE
T 59800 37200 9 10 1 0 0 0 1
SIG_1
B 58400 35300 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 59000 35700 61400 35700 3 0 0 0 -1 -1
T 58500 35900 9 10 1 0 0 0 1
REG
T 58100 36200 9 10 1 0 0 0 1
SIG_2_DRV
T 59900 35400 9 10 1 0 0 0 1
WIRE
T 59800 35800 9 10 1 0 0 0 1
SIG_2
B 58400 33800 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 59000 34200 61400 34200 3 0 0 0 -1 -1
T 58500 34400 9 10 1 0 0 0 1
REG
T 58100 34700 9 10 1 0 0 0 1
SIG_3_DRV
T 59900 33900 9 10 1 0 0 0 1
WIRE
T 59800 34300 9 10 1 0 0 0 1
SIG_3
T 61400 37000 9 10 1 0 0 0 1
SIG_1
T 61400 35600 9 10 1 0 0 0 1
SIG_2
T 61400 34100 9 10 1 0 0 0 1
SIG_3
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L 63400 38100 64500 38100 3 0 0 0 -1 -1
T 64900 39400 9 10 1 0 0 0 1
REG
T 64500 39700 9 10 1 0 0 0 1
SIG_4_EXP
T 63800 37800 9 10 1 0 0 0 1
WIRE
T 63800 38200 9 10 1 0 0 0 1
SIG_4
B 64800 36500 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 64900 37100 9 10 1 0 0 0 1
REG
T 64500 36200 9 10 1 0 0 0 1
SIG_4_MASK
B 64500 37700 1300 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 64600 38000 9 10 1 0 0 0 1
COMPARE
T 66200 38000 9 10 1 0 0 0 1
FAIL
L 65800 38100 66100 38100 3 0 0 0 -1 -1
L 66100 38100 66000 38200 3 0 0 0 -1 -1
L 66100 38100 66000 38000 3 0 0 0 -1 -1
L 65100 37300 65100 37700 3 0 0 0 -1 -1
L 65100 37700 65000 37600 3 0 0 0 -1 -1
L 65100 37700 65200 37600 3 0 0 0 -1 -1
L 65100 38800 65100 38500 3 0 0 0 -1 -1
L 65100 38500 65000 38600 3 0 0 0 -1 -1
L 65100 38500 65200 38600 3 0 0 0 -1 -1
T 62800 38000 9 10 1 0 0 0 1
SIG_4
T 61500 38800 9 10 1 0 0 0 1
CLK
T 61500 38500 9 10 1 0 0 0 1
RESET
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