Subversion Repositories socgen

v 20100214 2
C 57800 33700 1 0 0 frame_800x600.sym
B 61400 33900 2000 5500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 58400 36700 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 58500 37300 9 10 1 0 0 0 1
REG
L 59000 37100 60100 37100 3 0 0 0 -1 -1
T 61500 39500 9 10 1 0 0 0 2
GATES  COMP
DUT
B 57900 39400 1400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 58000 39800 9 10 1 0 0 0 1
CLOCK_GEN
T 58100 37600 9 10 1 0 0 0 1
SIG_1_DRV
B 58400 35300 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 59000 35700 60000 35700 3 0 0 0 -1 -1
T 58500 35900 9 10 1 0 0 0 1
REG
T 58100 36200 9 10 1 0 0 0 1
SIG_2_DRV
B 58400 34100 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 59000 34500 60000 34500 3 0 0 0 -1 -1
T 58500 34700 9 10 1 0 0 0 1
REG
T 58100 35000 9 10 1 0 0 0 1
SIG_3_DRV
T 61400 37000 9 10 1 0 0 0 1
SIG_1
T 61400 35600 9 10 1 0 0 0 1
SIG_2
T 61400 34400 9 10 1 0 0 0 1
SIG_3
B 64800 38800 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 63400 38100 64500 38100 3 0 0 0 -1 -1
T 64900 39400 9 10 1 0 0 0 1
REG
T 64500 39700 9 10 1 0 0 0 1
SIG_4_EXP
B 64800 36500 600 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 64900 37100 9 10 1 0 0 0 1
REG
T 64500 36200 9 10 1 0 0 0 1
SIG_4_MASK
B 64500 37700 1300 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 64600 38000 9 10 1 0 0 0 1
COMPARE
T 66200 38000 9 10 1 0 0 0 1
FAIL
L 65800 38100 66100 38100 3 0 0 0 -1 -1
L 66100 38100 66000 38200 3 0 0 0 -1 -1
L 66100 38100 66000 38000 3 0 0 0 -1 -1
L 65100 37300 65100 37700 3 0 0 0 -1 -1
L 65100 37700 65000 37600 3 0 0 0 -1 -1
L 65100 37700 65200 37600 3 0 0 0 -1 -1
L 65100 38800 65100 38500 3 0 0 0 -1 -1
L 65100 38500 65000 38600 3 0 0 0 -1 -1
L 65100 38500 65200 38600 3 0 0 0 -1 -1
T 62800 38000 9 10 1 0 0 0 1
SIG_4
T 61500 38800 9 10 1 0 0 0 1
CLK
T 61500 38000 9 10 1 0 0 0 1
RESET
T 58000 39100 9 10 1 0 0 0 1
CLK_TGEN
T 58000 38800 9 10 1 0 0 0 1
IN_TGEN
T 58000 38500 9 10 1 0 0 0 1
OUT_TGEN
B 57900 39000 1400 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 57900 38700 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 57900 38400 1400 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
B 60100 38600 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 60200 38700 9 10 1 0 0 0 2
TESTER
DRIVER
B 60100 37800 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 60200 37900 9 10 1 0 0 0 2
TESTER
DRIVER
B 60100 36800 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 60200 36900 9 10 1 0 0 0 2
TESTER
DRIVER
B 60000 35400 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 60100 35500 9 10 1 0 0 0 2
TESTER
DRIVER
B 60000 34200 1100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 60100 34300 9 10 1 0 0 0 2
TESTER
DRIVER
L 61100 34500 61400 34500 3 0 0 0 -1 -1
L 61100 35700 61400 35700 3 0 0 0 -1 -1
L 61200 37100 61400 37100 3 0 0 0 -1 -1
L 61200 38100 61400 38100 3 0 0 0 -1 -1
L 61200 38900 61400 38900 3 0 0 0 -1 -1
L 60100 38100 59600 38100 3 0 0 0 -1 -1
L 59600 38100 59600 39600 3 0 0 0 -1 -1
L 59600 39600 59300 39600 3 0 0 0 -1 -1
T 59400 39700 9 10 1 0 0 0 1
RESET
T 59800 38900 9 10 1 0 0 0 1
1
L 59900 38900 60100 38900 3 0 0 0 -1 -1
T 60100 33900 9 10 1 0 0 0 1
IN_TGEN
T 60100 39200 9 10 1 0 0 0 1
CLK_TGEN
T 63500 37800 9 10 1 0 0 0 1
OUT_TGEN