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<p><br>
<br>
</p>
</div>
<h1><a name="socgen_project"></a>SOCGEN Project</h1>
<h2>Signal,Port and Pad Naming Guidelines</h2>
<p><br>
<br>
</p>
<p>As Digital designs and design teams continue to grow it is
mandatory
that all rtl code must follow an established name space guideline. The
days when designers could simply pull names out of thin air are fast
disappearing. Naming guidelines have three functions. First they
ensure that no two designers select the same name for different objects
and have a name collision. The second function is to ensure that the
chosen names are meaningful to all of the design team. It is quite
common for designers to select names
that only make sense to themselves and no one else on the team. The
third function
is to ensure that all rtl code follows a consistent format so that it
may be parsed
by various eda tools.
</p>
<h3 class="western"><br>
</h3>
<h3 class="western"><br>
</h3>
<h3 class="western"><br>
</h3>
<h3 class="western">Signal ,Port and Pad Names<br>
</h3>
<p>Signals define the nodes inside of a component and each node
must have a unique name. That signal name becomes the port name when a
node is ported up the hierarchy. The port names become the pad names at
the top level. All of these exist in the same name space along
with other items such as instance names. Managing this name space is
crucial.<br>
</p>
<p><br>
There are two distinct groups that use these names. The IC design team
is one group and it will use all three. The other group consists
of System designers,PCB designers, Board Test engineers etc.<br>
They only access the chip via the pad names and never see the internal
ones. These two groups often have incompatible objectives. The IC
design team is dealing with millions of names and needs a naming scheme
that produces long descriptive names that won't collide and conveys
information about the signals function. <br>
</p>
<p>The rest of the world is only dealing with a few hundred or thousand
names. They also have their own naming requirements as well. These
typically
are:<br>
</p>
<p><br>
</p>
<ul>
<li>Short Names that fit on a schematic graphic symbol. If you
have 99 short names and 1 long one then you have a long column and
wasted white space on your schematic.</li>
</ul>
<br>
<ul>
<li>Capital Letters. They make a packed schematic
readable. You don't want your board designers squinting at a sheet
trying to guess if it's a
1 or a l.</li>
</ul>
<br>
<ul>
<li>ATE naming requirements. Do you know what the IEEE 1149.1
pad naming rules are? If not then you better not try to pick any pad
names.</li>
</ul>
<br>
<br>
The guideline for selecting pad names is that the IC design team should
not attempt to pick pad names based on the internal signal names.
They should first meet all of the PCA customers requirements without
regard to what names are chosen for the internal signals. Name
collisions are avoided by ensuring that ALL pad names start with a
capital letter and that all internal names start with a small
one. <br>
<br>
<br>
<br>
<br>
For internal signal and port names you must first find the four pieces
of information that will uniquely identify every signal in the design.
These are:<br>
<br>
<br>
<ul>
<li>Interface Name You don't want 5 different ways
to spell clock in a design. Each team must agree
on common signal names and everyone must follow the rules. These
are called standard interfaces. The team must create a document that
lists all the standard interfaces and their names. It is
ESSENTIAL that once a standard is chosen then all signals covered by
that standards MUST follow the naming rules and the no signals that are
not covered by the standard are allowed to use its name.<br>
</li>
</ul>
<br>
<ul>
<li>Sub_member If the standard
interface has more than one signal then you must also define the
names for each sub_member as part of the standard <br>
</li>
</ul>
<br>
<br>
<ul>
<li>Ad
hoc
If
a signal is not defined by a standard interface then an ad hoc
signal can be created based on the designers insight. If a module has 2
or more signals with the same standard interface then a ad hoc field is
needed to distinguish between them.</li>
</ul>
<br>
<ul>
<li>Driving Instance This is the instance name that
is driving the signal. Wired or tristate logic is not allowed. There
will be one and only one driver per node.</li>
</ul>
<br>
<br>
<br>
You can create signal names by simply gathering akk this information
and
concatenating it into a valid signal name. While you can use all
four fields,it is acceptable to
drop any field(s) if they are not needed to <br>
uniquely identify a node. For example a IC design may have a signal
named "clk". Clk is the
standard interface name for a clock signal so we know that it is a
clock. The clock interface has two sub_members - rising edge and
falling edge. If you have N sub_members then you only have to
identify N-1 of them. In this case the standard chooses _n for falling
edge clocks and nothing for rising edge. clk is a rising edge clock. An
ad hoc field is needed if the design has more than one clock and we
have several - 2x, 4x 1.5 x etc. But again we only have to add this to
all but one of the clocks. clk is a 1x clock. This design only has one
clock generator so we don't need to add the driving instance. If
a second clock generator is added then all of those clocks must include
the driving instance in their name.<br>
<br>
<br>
Besides defining all of the standard interfaces the design team must
also define a field separator such as _ (underscore) as the way to
separate the different fields that are combined to make a signal or
port name. But the most important decision of all is the order
that the fields are assembled to make up a name. This is like the Big
Endian/Little Endian issue. They both have their strengths and
weaknesses and it really doesn't matter which one you pick. BUT it is
essential that the design team picks one and everybody does it that
way. <br>
<br>
Signal and port names are even worse because with four fields you can
have 24 possible signal names for each node. Unless everyone on
the design team adheres to one order then it will be chaos when you try
to architect and synthesize a design.<br>
<br>
<br>
<br>
<br>
The recommended order for fields in a signal/port name is<br>
<br>
<br>
<br>
Driving_instance_(sep)_Ad
hoc_(sep)_Interface_(sep)_Sub_member<br>
<br>
<br>
<br>
This ordering gives us the ability to have our signal names follow
their function as the signals pass up and down the hierarchy. It also
gives us an easy rule to follow when we need to pick a signal name. All
that you need to do is find the instance name of the module that is
driving that signal and combine it with the port name from that
module. Since instance names are unique inside a design and port
names are unique inside of a module then this rule guarantees that no
other signal will use that name.<br>
<br>
By following this rule a signal name will grow as it progresses up the
hierarchy. At each new level a new instance name is
stuck on the front end and the instance name
from the lower level becomes part of the ad hoc field. Each
name contains a history of how it was created and what it does.<br>
<br>
<br>
There are some special cases that can occur and these rules should be
followed:<br>
<br>
<br>
<ul>
<li>There is one sub_member that can be used on a ad hoc signal
that is not defined as a standard interface. That sub_member is active
low (_n).</li>
</ul>
<br>
<ul>
<li>If a standard interface includes a signal that is itself defined
as another standard interface then the interface name of the
child becomes the sub member name for the parent. This usually occurs
when a clock or reset is included in a bus interface. This ensures that
when parsing the signal name it will match on both interfaces. If there
are multiples of this interface then a ad hoc field must be perpended
to the sub_member interface.</li>
</ul>
<br>
<ul>
<li>If the driving instance is not known such as a module where the
signal is an input port then the instance and port of a receiving
instance may be used instead.</li>
</ul>
<br>
<br>
<br>
Again remember that any field may be dropped if it is not needed to
uniquely identify the node<br>
<br>
<br>
<br>
<img style="width: 800px; height: 600px;" alt=""
src="../png/naming_guide_1.png"><br>
<p><br>
<br>
<br>
Here is an example of how this works in a real design. A router IC has
24 instances of a ethernet interface. Each instance controls a transmit
sram buffer and a receive sram buffer. There are four instances in a
bank and the bank is instantiated six times. The receive write
data for the third interface in the second bank
originates in a register bank deep inside a submodule. The name
of this register is sram_wdata and that was chosen because the sram bus
is a standard interface and wdata is the sub_member for the wdata. As
it passes through the hierarchy the driving instance name is prepended
on the front. It always parses as a sram wdata signal but the ad hoc
field keeps growing.</p>
<p><br>
If the clock signal is also included in the sram interface then it's
name would be:</p>
<p> <br>
</p>
<p>
bank_2_eth_3_sram_clk<br>
<br>
</p>
<p>It would parse as both a clock signal and a sram signal. If this
were a dual port sram then the signal would be:</p>
<p><br>
</p>
<p>
bank_2_eth_3_sram_a_clk
<br>
</p>
<p><br>
</p>
<p>Notice that there is an ad hoc field both before and after the sram
interface name and it still parses as both a clock and a sram signal.<br>
</p>
<p><br>
</p>
<p>If you want to synthesize the bank of 4 controllers then you will
need to set an output delay on the sram outputs as a placeholder for
the setup and routing delays in the full chip. To do this you need the
full instance name of the source registers as seen from the top level.
Assuming you use the standard _reg convention it would be:<br>
</p>
<p><br>
eth_3/rx/sram_wdata_reg<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
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</p>
<p><br>
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</p>
<p><br>
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</p>
<p><br>
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</p>
<p><br>
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</p>
<p><br>
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</p>
<p><br>
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</p>
<p><br>
<br>
</p>
<br>
<p><br>
</p>
<h2>Standard Interfaces<br>
</h2>
<p></p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<h3 class="western">Clock <br>
</h3>
<p><br>
A clock is a signal that drives the clock port of a flipflop.<br>
</p>
<br>
<table style="text-align: left; width: 500px; height: 120px;" border="8"
cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Interface<br>
</td>
<td style="vertical-align: top;">Clock<br>
</td>
<td style="vertical-align: top;">Name<br>
</td>
<td style="vertical-align: top;">Sub <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">CLK<br>
</td>
<td style="vertical-align: top;"> <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">Rising Edge<br>
</td>
<td style="vertical-align: top;">CLK<br>
</td>
<td style="vertical-align: top;"> <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Falling Edge<br>
</td>
<td style="vertical-align: top;">CLK<br>
</td>
<td style="vertical-align: top;">_N<br>
</td>
</tr>
</tbody>
</table>
<br>
<br>
<br>
<h3 class="western">Reset <br>
</h3>
<p><br>
A reset is a signal forces nodes into a known safe state<br>
</p>
<br>
<table style="text-align: left; width: 500px; height: 120px;" border="8"
cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Interface<br>
</td>
<td style="vertical-align: top;">Reset<br>
</td>
<td style="vertical-align: top;">Name<br>
</td>
<td style="vertical-align: top;">Sub <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">RESET<br>
</td>
<td style="vertical-align: top;"> <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">Active high sync<br>
</td>
<td style="vertical-align: top;">RESET<br>
</td>
<td style="vertical-align: top;"> <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Active Low async<br>
</td>
<td style="vertical-align: top;">RESET<br>
</td>
<td style="vertical-align: top;">_N<br>
</td>
</tr>
</tbody>
</table>
<br>
<br>
<br>
<h3 class="western">Pads <br>
</h3>
<p><br>
Pads are the connections made between the pad_ring and the core.<br>
</p>
<br>
<table style="text-align: left; width: 500px; height: 120px;" border="8"
cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Interface<br>
</td>
<td style="vertical-align: top;">Pads<br>
</td>
<td style="vertical-align: top;">Name<br>
</td>
<td style="vertical-align: top;">Sub <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">PAD<br>
</td>
<td style="vertical-align: top;"> <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">output<br>
</td>
<td style="vertical-align: top;">PAD<br>
</td>
<td style="vertical-align: top;">_OUT <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Input<br>
</td>
<td style="vertical-align: top;">PAD<br>
</td>
<td style="vertical-align: top;">_IN<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Enable<br>
</td>
<td style="vertical-align: top;">PAD<br>
</td>
<td style="vertical-align: top;">_OE<br>
</td>
</tr>
</tbody>
</table>
<br>
<br>
<br>
<h3 class="western">Sram <br>
</h3>
<p><br>
Sram signals connect between the core and an instantiated memory cell.<br>
</p>
<br>
<table style="text-align: left; width: 500px; height: 120px;" border="8"
cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Interface<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">Name<br>
</td>
<td style="vertical-align: top;">Sub <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;"> <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">RW Address<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_ADDR <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">Read Address<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_RADDR <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">Write Address<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_WADDR <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Write Data<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_WDATA<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Read Data<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_RDATA<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Ram Select<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_CS<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Write Enable<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_WR<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Read Enable<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_RD<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Bit Write Enable<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_BE<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Clock<br>
</td>
<td style="vertical-align: top;">SRAM<br>
</td>
<td style="vertical-align: top;">_CLK<br>
</td>
</tr>
</tbody>
</table>
<br>
<br>
<br>
<h3 class="western">Wishbone Bus <br>
</h3>
<p><br>
The wishbone bus provides microprocessor interconnection .<br>
</p>
<br>
<table style="text-align: left; width: 500px; height: 120px;" border="8"
cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Interface<br>
</td>
<td style="vertical-align: top;">Wishbone<br>
</td>
<td style="vertical-align: top;">Name<br>
</td>
<td style="vertical-align: top;">Sub <br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">Address<br>
</td>
<td style="vertical-align: top;">WB<br>
</td>
<td style="vertical-align: top;">_ADR<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"> <br>
</td>
<td style="vertical-align: top;">Write Data<br>
</td>
<td style="vertical-align: top;">WB<br>
</td>
<td style="vertical-align: top;"> _WDAT<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Read Data<br>
</td>
<td style="vertical-align: top;">WB<br>
</td>
<td style="vertical-align: top;">_RDAT<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Write Enable<br>
</td>
<td style="vertical-align: top;">WB<br>
</td>
<td style="vertical-align: top;">_WE<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Byte Select<br>
</td>
<td style="vertical-align: top;">WB<br>
</td>
<td style="vertical-align: top;">_SEL<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Cycle<br>
</td>
<td style="vertical-align: top;">WB<br>
</td>
<td style="vertical-align: top;">_CYC<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Data Strobe<br>
</td>
<td style="vertical-align: top;">WB<br>
</td>
<td style="vertical-align: top;">_STB<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">Acknowledge<br>
</td>
<td style="vertical-align: top;">WB<br>
</td>
<td style="vertical-align: top;">_ACK<br>
</td>
</tr>
<tr>
<td style="vertical-align: top;"><br>
</td>
<td style="vertical-align: top;">CTI<br>
</td>
<td style="vertical-align: top;">WB<br>
</td>
<td style="vertical-align: top;">_CTI<br>
</td>
</tr>
</tbody>
</table>
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