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<h1><a name="socgen_project"></a><big>SOCGEN Project</big></h1>
<h2><br>
</h2>
<h2><a name="manifesto"></a>Verification Guidelines</h2>
<p><br>
<br>
</p>
<p>Verification is the art of stimulating a component
module and checking that it produces the correct outputs. Stimulations
are designed to
ensure that all of the components functions are exercised and any
deviation from the expected behaviour is reported as an error.
Every
component must have at least one test case but may have as many as
needed to fully verify the design. All components will have at least
one interface and a bus functional model (bfm) must be created for each
and every interface.<br>
</p>
<p>A complete test suite is required for every component module.
Each test_case is simulated and the log file will indicate whether the
test passed or failed. Other output files such as dump files may also
be produced duging the simulation.<br>
</p>
<p><br>
</p>
<p></p>
<br>
<p><img style="width: 800px; height: 600px;" alt=""
src="../png/ver_fig1.png"><br>
</p>
<p><br>
</p>
<p>A test suite is needed for every piece of IP in the design and
creating this suite can be a very labor intensive operation. It usually
takes four hours to create the test_cases for each hour that was spent
creating the rtl code. A full test must be run on every leaf cell
component and some of these are repeated as the components are used as
children of other components. It is essential that all test_cases
are written so that they may be reused when testing the component when
it it part of a parent component.<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><img style="width: 800px; height: 600px;" alt=""
src="../png/ver_fig2.png"><br>
</p>
<p>In this case a new component is created by combining two leaf
cell components and its test_case is created by combining blocks from
those two components test_cases.<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
<br>
</p>
<p><br>
</p>
<p><img style="width: 800px; height: 600px;" alt=""
src="../png/ver_fig3.png"><br>
</p>
<p><br>
</p>
<p>Every interface on the component is connected to it's own bfm model
that contains all the tasks needed to test the interface. The calling
sequences needed to preform a particular test are all loaded from a
sperate test_define file. It is important that each interface has its
task calls in
a seperate code block in the test_define file. The goal is to develop
these models and task
calls on the component simulation and then reuse them as the
component is used in larger designs. Interleaving task calls for
different models makes that difficult.<br>
</p>
<p><br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>Protocol checkers and monitors<br>
</h2>
<br>
Protocol checkers and monitors are similar to a bus functional
models except that they are for obsevation only and cannot
control any signals. They watch every transaction that occurs on the
interface and reports a failure when anything violates that interfaces
defined protocols. <span style="font-family: serif;"> They are created
in a seperate module and may be instantiated in the testbench and
connected to an interface.<br>
<br>
The same protocol checker can also be included in the rtl code so it
can monitor an interface that is buried deep inside a chip. Once
inserted in the rtl source it will watch for and report errors
that may occur during the regression suite. Since protocol checkers
are not synthesizable they must be excluded from synthesis with a
`ifndef SYNTHESYS statement.<br>
<br>
Monitors are similar to protocol checkers except that they are designed
to be implemetent in actual logic. If they ever fire during
product usage then these events should be latched and saved for later
debugging.<br>
<br>
</span>
<p><br>
<br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>guidelines for creating reusable test_cases<br>
</h2>
<br>
All test_cases will have a master clock and reset signal.
The DUT and all models will respond to the reset signal. Anything in
test_define will only change state on the rising edge of clock.<br
style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;"> All test_cases will be
self-checking. Test suites are usually run by scripts and robots
that need a simple method to determine wether a test_case finished and
passed. </span><br style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;"> All models, tasks and protocal
checkers will use a common method to report if there is a failure.</span><br
style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;"> All test sequences will use a
common method to signal the successful completion of the test</span><br
style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;"> All messages in the log file
must use the following format:</span><br>
<br style="font-family: serif;">
<ul style="font-family: monospace;">
<li><big>Time stamp This is the
$realtime formated by %t</big></li>
<li><big>Instance Name This is obtained with
%m</big></li>
<li><big>Message Type This is either
ERROR or WARNING. No type indicates informational message</big></li>
<li><big>Message
</big><br>
</li>
</ul>
<br style="font-family: serif;">
<br style="font-family: serif;">
<p style="font-family: serif;"> All test cases MUST have a
finite run time. Use a TIMEOUT counter to stop the sim if it
exceeds the expected number of clocks<br style="font-family: serif;">
</p>
<span style="font-family: serif;">
<code><span style="font-family: serif;">All test_cases must be
deterministic. If any pseudorandom delays are used they must be
"seeded" and repeatable from run to run.</span></code></span><code
style="font-family: serif;"><br>
<br>
<br>
<span style="font-family: serif;"> </span></code><span
style="font-family: serif;"><code><span style="font-family: serif;">Do
not interweave threads in the test_define blocks. Each block should
only access a single BFM.</span><br style="font-family: serif;">
<br style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;"> Plan on designs where you will
need to test multiple instances of a component</span><br
style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;"> Only test a single
configuration or mode in any test_case. If you need to test 3 different
modes then create 3 different test_cases. The exception to this is when
there is a mission mode requirement to switch modes and you are testing
that switch. </span><br style="font-family: serif;">
</code></span>
<p style="font-family: serif;"><br>
</p>
<p><br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>Gate and Post Route Simulations<br>
</h2>
<br>
All signals between the DUT and the bfms change only at the
rising edge of clk. This is fine for RTL sims but will not work for
real logic with setup and hold time requirements. For these the signals
driving the dut must be delayed from clk and from each other to provide
the required setup and hold times. Signals from the DUT will have
delays and must only be tested during a prescribed time window.<br>
This is accomplished with a set of modules that mimic the functions of
a IC tester. These modules provide the interface between the BFM's and
the DUT.<br>
<br>
<br>
<img style="width: 800px; height: 600px;" alt=""
src="../png/ver_fig4.png"><br>
<br style="font-family: serif;">
<br style="font-family: serif;">
<span style="font-family: serif;"></span><span
style="font-family: serif;"><br>
</span>
<p></p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
<br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>simulation directory (sim)<br>
</h2>
<p><br>
</p>
<big><code>
./sim<br>
+/bin<br>
Makefile<br>
+/bench<br>
+verilog<br>
TestBench<br>
+models<br>
model1<br>
model2<br>
.<br>
.<br>
.<br>
+/lib<br>
+lib_part1<br>
lib_part(s).v<br>
+lib_part2<br>
.<br>
.<br>
.<br>
</code><code> +/run</code><br>
<code> +test_case1<br>
filelist<br>
dmp_define<br>
modellist<br>
dut<br>
test_define<br>
liblist<br>
TB.defs<br>
+test_case2<br>
.<br>
.<br>
.<br>
+/log<br>
test_case1.log<br>
test_case2.log<br>
.<br>
.<br>
.<br>
+/out<br>
</code><code> test_case1.vcd<br>
test_case2.vcd<br>
.<br>
.<br>
.</code><br>
</big>
<code><ouabache design="" works=""><big><br>
<br>
<br>
</big>
<br>
</ouabache></code>
<p>Each component will have a ./sim directory for the test suite.
Typing:<br>
</p>
<p><big><big><br>
<small><span style="font-family: monospace;">
<>:~$>cd ./sim/bin</span><br style="font-family: monospace;">
</small><span style="font-family: monospace;"><small>
<>:~$>make run_sims</small><br>
</span></big></big></p>
<p><big><big><span style="font-family: monospace;"><br>
</span></big></big>
</p>
will run the entire test suite. After that has been done then
individual test_cases may be rerun by changing into their test_case
directory and typing:<br>
<code><ouabache design="" works=""><br>
<br>
</ouabache></code>
<p><big><big><span style="font-family: monospace;"><small><>:~$>make
sim</small></span></big></big>
</p>
<p><br>
</p>
<p>Each test_case will produce a log file that may be parsed for the
string "PASSED" to indicate that the sim finished. If so then the log
file should be parsed for the strings "ERROR" and "WARNING" to see if
there were and errors or warnings. <br>
</p>
<p>Simulating a test_case requires involking a verilog simulator and
passing it command line arguments and a TestBench file. Icarus verilog
is the default simulator for the socgen project. Socgen uses a minumal
command line and instead puts most needed information in the TestBench
file. The only command line option is to set the VCD flag if a
value change dump file is needed.<br>
</p>
<p><br>
</p>
<p><br>
<br>
<br>
<br>
<br>
</p>
<h2><a name="manifesto"></a>TestBench file<br>
</h2>
<code>
<ouabache design="" works="">--------------------------------------------------------------------------------------------------------------------------------------<br>
<br>
`include "./TB.defs"<br>
<br>
`ifndef TIMESCALE<br>
`define TIMESCALE 1ns/1ns<br>
`endif<br>
<br>
<br>
`ifndef TIMEFORMAT<br>
`define TIMEFORMAT $timeformat(-6, 2, "
us", 14);<br>
`endif<br>
<br>
<br>
`ifndef PERIOD<br>
`define PERIOD
40.00000 <br>
`endif<br>
<br>
`ifndef TIMEOUT<br>
`define TIMEOUT 200000<br>
`endif<br>
<br>
<br>
`timescale `TIMESCALE<br>
<br>
<br>
`include "./filelist"<br>
`include "./liblist"<br>
`include "./modellist"<br>
<br>
<br>
<br>
<br>
module TB();<br>
<br>
wire clk;<br>
wire reset;<br>
<br>
`include "./dut"<br>
`include "./test_define"<br>
<br>
<br>
`ifdef VCD<br>
initial<br>
begin<br>
`include "./dmp_define"<br>
end<br>
`endif<br>
<br>
clock_gen<br>
#(.PERIOD(`PERIOD),<br>
.TIMEOUT(`TIMEOUT))<br>
cg <br>
( .clk ( clk ),<br>
.reset ( reset )<br>
);<br>
<br>
<br>
<br>
<br>
endmodule<br>
</ouabache></code><span style="font-family: monospace;"><br>
--------------------------------------------------------------------------------------------------------------------------------------<br>
</span>
<p><span style="font-family: monospace;"><br>
</span></p>
<p><br>
<span style="font-family: monospace;"></span></p>
<p>A single TestBench file provides the infrastructure for all
test cases. The actual testing is determined by the data contained in
six files in the ./sim/run/test_case directory. The TestBench file
creates a top level module named TB and instantiates a clock_reset
generator module to provide each test_case with a clock and a reset
signal. It also provides a vcd dump and timeout functions
for each test_case.<span style="font-family: monospace;"><br>
</span></p>
<p><span style="font-family: monospace;"><br>
</span></p>
<p><span style="font-family: monospace;"><br>
</span></p>
<h2><a name="manifesto"></a>TB.defs <br>
</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
</p>
<code>
`define TIMESCALE 1ns/1ns<br>
`define TIMEFORMAT $timeformat(-6, 2, "
us", 14);<br>
`define PERIOD
40.0000 <br>
`define TIMEOUT 200000<br>
</code>
<p></p>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------<br>
</span></p>
<p><span style="font-family: monospace;"><br>
</span></p>
<p>The TB.defs file may be used to set up the timescale and master
clock period for the simulation. Any model or lib part that needs
to reset the timescale back to the system default must use:<br>
</p>
<p><code>`timescale `TIMESCALE<br>
</code></p>
<p><code><br>
<span style="font-family: serif;">Do NOT use</span><br>
</code></p>
<p><code>`include "./timescale.v"<br>
</code></p>
<p><code><br>
<span style="font-family: serif;">The socgen project does not contain
any timescale.v file. All socgen rtl code is preprocessed before
it is passed to simulation and the value of the timescale may change
depending on the simulation. All ip components must only contain
synthesisable code and should not have any need for timescale.<br>
</span></code></p>
<p><code><span style="font-family: serif;">TIMEFORMAT will set the
format that is used when time is displayed using the %t format . All
$display statements must start by displaying $realtime using the %t
format so every line in the log has a time stamp. Any display statement
from an instantiated module must also have %m to print out it's
instance name. If the message is an error or a warning then the strings
ERROR or WARNING must be used so that this information may be parsed
from the log file.<br>
<br style="font-family: serif;">
</span></code></p>
<p><span style="font-family: monospace;"><br>
</span>The TB.defs file may also
be used to pass the size and location of an embedded bit
file to the device_under_test<span style="font-family: monospace;"> <br>
</span></p>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span></p>
<p><span style="font-family: monospace;">`define ROM_WORDS 2048 <br>
`define ROM_ADDR 11 <br>
`define ROM_WIDTH 12 <br>
`define ROM_FILE "../../../../../sw/mouse/mouse.abs12"<br>
</span><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
</p>
<p>The path is the relative path from the test_case run directory.<span
style="font-family: monospace;"><br>
</span></p>
<p><span style="font-family: monospace;"><br>
</span></p>
<h2><a name="manifesto"></a>filelist </h2>
<p style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------<br>
</p>
<p style="font-family: monospace;">`include
"../../../rtl/gen/sim/soc_mouse.v"<br>
`include "../../../../pic16c5x/rtl/gen/sim/pic16c5x.v"<br>
`include
"../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module_mouse.v"<br>
`include
"../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"<br>
`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"<br>
</p>
<code style="font-family: monospace;"></code>
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
<p><br>
</p>
<p>The filelist uses `include statements to load all the rtl files into
the simulation.The paths are relative from the test_case run
directory. Note that all the verilog files have been post-processed and
search directories or include directories are not needed.
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>liblist</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
</p>
<code>
<br>
`include "../../lib/cde_sram/cde_sram.v"<br>
`include "../../lib/cde_lifo/cde_lifo.v"<br>
`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v"<br>
<br>
</code>
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
<p>The liblist uses `include statements to load all the generic lib
models into
the simulation.The paths are relative from the test_case run
directory. Note that these libs may be replaced by vendor
specific instances when the design is synthesised into gates.<br>
</p>
<p><br>
</p>
<p></p>
<p><br>
</p>
<h2><a name="manifesto"></a>modellist</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span>
</p>
<code><br>
`include "../../bench/verilog/models/clock_gen.v"<br>
`include "../../bench/verilog/models/ps2_model.v"<br>
</code><code>`include "../../bench/verilog/models/uart_model.v"</code><code>
<br>
`include "../../bench/verilog/models/iobuftri.v" <br>
</code><span style="font-family: monospace;"></span><code><br>
</code>
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
<br>
This list loads all of the simulation models used in the simulation.<br>
<br>
<p><br>
<br>
</p>
<h2><a name="manifesto"></a>dut<br>
</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><code><br>
wire ps2_data_pad_oe;<br>
wire ps2_data_pad_in;<br>
wire ps2_data;<br>
wire ps2_clk_pad_oe;<br>
wire ps2_clk_pad_in;<br>
wire ps2_clk;<br>
<br>
wire [7:0] portaout;<br>
wire [7:0] portbout;<br>
wire [7:0] portcout;<br>
<br>
<br>
wire [9:0] y_pos;<br>
wire [9:0] x_pos;<br>
wire
new_packet;<br>
wire
ms_mid; <br>
wire
ms_right; <br>
wire
ms_left; <br>
<br>
<br>
<br>
wire
serial_txd;<br>
wire
serial_rxd;<br>
wire loop;<br>
<br>
<br>
soc_mouse<br>
#(<br>
.ROM_WORDS ( `ROM_WORDS ), <br>
.ROM_ADDR ( `ROM_ADDR ), <br>
.ROM_WIDTH ( `ROM_WIDTH ), <br>
.ROM_FILE ( `ROM_FILE )<br>
)<br>
dut(<br>
.clk (
clk ),<br>
.reset (
reset ),<br>
<br>
.ps2_data_pad_in ( ps2_data_pad_in ),<br>
.ps2_clk_pad_in ( ps2_clk_pad_in ),<br>
<br>
.ps2_data_pad_oe ( ps2_data_pad_oe ),<br>
.ps2_clk_pad_oe ( ps2_clk_pad_oe ),<br>
<br>
.portaout (
portaout ),<br>
.portbout ( portbout
),<br>
.portcout (
portcout ),<br>
<br>
.y_pos (
y_pos ),<br>
.x_pos (
x_pos ),<br>
.new_packet ( new_packet
),<br>
.ms_mid (
ms_mid ), <br>
.ms_right (
ms_right
), <br>
.ms_left (
ms_left ), <br>
<br>
.txd_pad_out (
serial_txd ),<br>
.rxd_pad_in (
serial_rxd ),<br>
.cts_pad_in (
loop
),<br>
.rts_pad_out (
loop
) <br>
<br>
);<br>
</code></p>
<p><code>uart_model <br>
#(.CLKCNT(4'hc))<br>
uart_model<br>
(<br>
.clk
(
clk
),<br>
.reset
(
reset
),
<br>
.txd_in
( serial_txd ),<br>
.rxd_out
( serial_rxd )<br>
<br>
);</code><br>
<code></code></p>
<p><code><br>
</code></p>
<p><code><br>
iobuftri<br>
data_tri_buf<br>
(<br>
.i (
1'b0 ),<br>
.oe ( ps2_data_pad_oe ),<br>
.o ( ps2_data_pad_in ),<br>
.pad ( ps2_data )<br>
);<br>
<br>
<br>
iobuftri<br>
clk_tri_buf<br>
(<br>
.i ( 1'b0
),<br>
.oe ( ps2_clk_pad_oe ),<br>
.o ( ps2_clk_pad_in ),<br>
.pad ( ps2_clk )<br>
);<br>
<br>
<br>
<br>
pullup ua0(ps2_clk);<br>
pullup ua1(ps2_data);<br>
<br>
<br>
ps2_model <br>
#(.CLKCNT(10'h177))<br>
ps2_model<br>
(<br>
.clk
(
clk
),<br>
.reset
(
reset
),
<br>
.ps2_clk
(
ps2_clk
),<br>
.ps2_data
(
ps2_data
)<br>
<br>
);</code></p>
<p><code><br>
</code></p>
<p><code><br>
</code><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
</p>
<p>This file is a verilog code segment that declares all the wires and
regs needed in the sim (except for clk and reset). It then
instantiates the component and all needed models for the simulation.<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>test_define<br>
</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span></p>
<p><br>
</p>
<p><span style="font-family: monospace;">initial</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">begin</span><span
style="font-family: monospace;"></span><br
style="font-family: monospace;">
<span style="font-family: monospace;">$display("
");</span><br style="font-family: monospace;">
<span style="font-family: monospace;">$display("
===================================================");</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">$display("
Test
Start");</span><br style="font-family: monospace;">
<span style="font-family: monospace;">$display("
===================================================");</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">$display("
");</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'h00;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_ack
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_stop
=
1'b1;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">cg.reset_off;</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'haa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'h00;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'h03;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">while (device_rx_read == 1'b0 )
cg.next(1);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(2000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hfa;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'h12;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'h34;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'h56;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'h78;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b0;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'h9a;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">device_parity
= 1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">device_tx_data
= 8'hbc;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b1;</span><br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(1);</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">device_write
=
1'b0;</span><br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">cg.next(20000);</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<br style="font-family: monospace;">
<span style="font-family: monospace;">$display("%t
Test PASSED",$realtime);</span><br style="font-family: monospace;">
<span style="font-family: monospace;">$finish;</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">end</span><br
style="font-family: monospace;">
<br style="font-family: monospace;">
<br>
</p>
<p><br>
</p>
<p><br>
<span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>dmp_define<br>
</h2>
<p style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------<br>
</p>
<p style="font-family: monospace;">$dumpfile ("TestBench.vcd");<br>
$dumpvars (0, TB);<br>
--------------------------------------------------------------------------------------------------------------------------------------<br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
</p>
<p><br>
</p>
<p><br>
</p>
<p>This is a test<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
</body>
</html>
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