Subversion Repositories socgen

eval 'exec `which perl` -S $0 ${1+"$@"}'
   if 0;

#/**********************************************************************/
#/*                                                                    */
#/*             -------                                                */
#/*            /   SOC  \                                              */
#/*           /    GEN   \                                             */
#/*          /    TOOL    \                                            */
#/*          ==============                                            */
#/*          |            |                                            */
#/*          |____________|                                            */
#/*                                                                    */
#/*  convert verilog file(s)ports  to a geda schematic                 */
#/*                                                                    */
#/*                                                                    */
#/*  Author(s):                                                        */
#/*      - John Eaton, jt_eaton@opencores.org                          */
#/*                                                                    */
#/**********************************************************************/
#/*                                                                    */
#/*    Copyright (C) <2010>  <Ouabache Design Works>                   */
#/*                                                                    */
#/*  This source file may be used and distributed without              */
#/*  restriction provided that this copyright statement is not         */
#/*  removed from the file and that any derivative work contains       */
#/*  the original copyright notice and the associated disclaimer.      */
#/*                                                                    */
#/*  This source file is free software; you can redistribute it        */
#/*  and/or modify it under the terms of the GNU Lesser General        */
#/*  Public License as published by the Free Software Foundation;      */
#/*  either version 2.1 of the License, or (at your option) any        */
#/*  later version.                                                    */
#/*                                                                    */
#/*  This source is distributed in the hope that it will be            */
#/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
#/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
#/*  PURPOSE.  See the GNU Lesser General Public License for more      */
#/*  details.                                                          */
#/*                                                                    */
#/*  You should have received a copy of the GNU Lesser General         */
#/*  Public License along with this source; if not, download it        */
#/*  from http://www.opencores.org/lgpl.shtml                          */
#/*                                                                    */
#/**********************************************************************/

#  ToDo:
#  parse reg from output bus name
#  parse bus and change pin type to bus

use Verilog::Netlist;

# Setup options so files can be found
use Verilog::Getopt;
my $opt = new Verilog::Getopt;
$opt->parameter( "+incdir+verilog",
                    "-y","verilog",
               );


@files            = @ARGV;


# Prepare netlist
my $nl = new Verilog::Netlist (options => $opt,);

foreach $file (@files) {
                        print "Parsing   $file\n";
                        $nl->read_file (filename=>$file);
} 







# Read in any sub-modules
$nl->link();
$nl->exit_if_error();


foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}



sub make_sch {
        my $mod = shift;
        my $mod_name  = $mod->name;

        my $in_count   = 0;
        my $out_count  = 0;
        my $in_length  = 0;
        my $out_length = 0;

        my $color =  5;
        my $size  = 10;


        open(FILE,">sch/${mod_name}.sch") or die "No sch directory";

        foreach my $sig ($mod->ports_sorted) {

            my $dir       =  $sig->direction;
            my $data_type =  $sig->data_type;
            my $sig_name  =  $sig->name;
            $data_type  =~ s/reg //;
            $data_type  =~ s/reg//;






            if($data_type)
              {
              $pin_name = "$sig_name"."$data_type";
              if("in" eq  $dir)
                {
                push(@invads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length) { $in_length =  length($pin_name)};
                }
              if("out" eq  $dir)
                {
                push(@outvads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }
              if("inout" eq  $dir)
                {
                push(@inoutvads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
                }

              }
            else          
              {
              $pin_name = $sig_name;
              if("in" eq  $dir)
                {
                push(@inpads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
                }
              if("out" eq  $dir)
                {
                push(@outpads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }

              if("inout" eq  $dir)
                {
                push(@inoutpads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
              }


           };          


        }

        my $max_pins;

        if($in_count > $out_count) {$max_pins = $in_count ;} else  {$max_pins = $out_count ;}

        my $in_edg  = ($in_length)*10*$size +200;
        my $in_pad  = ($in_length)*10*$size +200;
        my $out_edg = ($in_length +$out_length)*10*$size +2500;
        my $out_pad = ($in_length +$out_length)*10*$size +1500;

        printf FILE ("v 20100214 1\n");

        printf  ("%s\n", $mod->name);

         my $pin_y = 300;

         while( $name =pop(@invads))
          {
         printf FILE ("C $in_pad $pin_y 1 0 0 in_port_v.sym   \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);
         $pin_y = $pin_y +400;
          }


         while( $name =pop(@inpads))
          {
           printf FILE ("C $in_pad $pin_y 1 0 0 in_port.sym  \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }



         while( $name =pop(@inoutvads))
          {
         printf FILE ("C $in_pad $pin_y 1 0 0 io_port_v.sym   \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);
         $pin_y = $pin_y +400;
          }


         while( $name =pop(@inoutpads))
          {
           printf FILE ("C $in_pad $pin_y 1 0 0 io_port.sym  \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }




         $pin_y = 300;

         while( $name =pop(@outvads))         
          {
           printf FILE ("C $out_pad $pin_y  1 0  0 out_port_v.sym\n{\nT $out_edg $pin_y $color  $size 1 1 0 0 1 1 \nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }


         while( $name =pop(@outpads))         
          {
           printf FILE ("C $out_pad $pin_y  1 0 0 out_port.sym\n{\nT $out_edg $pin_y $color  $size 1 1 0 0 1 1\nrefdes=%s\n}\n",$name);
           $pin_y = $pin_y +400;
          }






        foreach my $cell ($mod->cells_sorted) {
            close(FILE);
            make_sch ($cell->submod, $cell->name) if $cell->submod;
        }
    }







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