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[/] [socgen/] [trunk/] [tools/] [simulation/] [run_sims] - Rev 128

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eval 'exec `which perl` -S $0 ${1+"$@"}'
   if 0;

#/**********************************************************************/
#/*                                                                    */
#/*             -------                                                */
#/*            /   SOC  \                                              */
#/*           /    GEN   \                                             */
#/*          /    TOOL    \                                            */
#/*          ==============                                            */
#/*          |            |                                            */
#/*          |____________|                                            */
#/*                                                                    */
#/*                                                                    */
#/*                                                                    */
#/*  Author(s):                                                        */
#/*      - John Eaton, jt_eaton@opencores.org                          */
#/*                                                                    */
#/**********************************************************************/
#/*                                                                    */
#/*    Copyright (C) <2010-2011>  <Ouabache Design Works>              */
#/*                                                                    */
#/*  This source file may be used and distributed without              */
#/*  restriction provided that this copyright statement is not         */
#/*  removed from the file and that any derivative work contains       */
#/*  the original copyright notice and the associated disclaimer.      */
#/*                                                                    */
#/*  This source file is free software; you can redistribute it        */
#/*  and/or modify it under the terms of the GNU Lesser General        */
#/*  Public License as published by the Free Software Foundation;      */
#/*  either version 2.1 of the License, or (at your option) any        */
#/*  later version.                                                    */
#/*                                                                    */
#/*  This source is distributed in the hope that it will be            */
#/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
#/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
#/*  PURPOSE.  See the GNU Lesser General Public License for more      */
#/*  details.                                                          */
#/*                                                                    */
#/*  You should have received a copy of the GNU Lesser General         */
#/*  Public License along with this source; if not, download it        */
#/*  from http://www.opencores.org/lgpl.shtml                          */
#/*                                                                    */
#/**********************************************************************/


############################################################################
# General PERL config
############################################################################
use Getopt::Long;
use English;
use File::Basename;
use Cwd;
use XML::LibXML;
use lib './tools';
use sys::lib;
use yp::lib;

$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.


############################################################################
### Process the options
############################################################################
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h","help",
) || die "(use '$program_name -h' for help)";




##############################################################################
## Help option
##############################################################################
if ( $opt_h or $opt_help  ) 
  { print "\n run_sims project_name  project_vendor";
    print "\n";
    exit 1;
  }


#/**********************************************************************/
#/*  Process each project by finding any ip-xact file in any component */
#/*                                                                    */
#/*  Each ip-xact file is parsed and it's filename and the names of any*/
#/*  modules that it uses are saved.                                   */
#/*                                                                    */
#/*                                                                    */
#/**********************************************************************/


my $home              = cwd();
my $vendor ;
my $project  ;




$_               = $ARGV[0];
my $work_site    = $ARGV[1];


if(/(\S+)__(\S+)/) 
     { 
     $vendor           = $1;
     $project         = $2;
     }











my $parser = XML::LibXML->new();



my @components   = yp::lib::find_components("socgen:componentConfiguration",$vendor,$project);

foreach my $component (@components) 
   {
   my $sogen_file     = $parser->parse_file(yp::lib::find_socgen("socgen:componentConfiguration",$vendor,$project,$component));
   my $sim_library_path   = $sogen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:library_path/text()")->to_literal;



   #/*********************************************************************************************/
   #/   files for simulation                                                                     */
   #/                                                                                            */
   #/*********************************************************************************************/

   foreach  my   $i_name ($sogen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))
      {
      my($sim_name)     = $i_name ->findnodes('./text()')->to_literal ;
      my($sim_configuration)  = $i_name ->findnodes('../socgen:configuration/text()')->to_literal ;
      my($sim_variant)  = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
   
      print "  SIMs     $sim_name        $sim_configuration   $sim_variant   "; 
      chdir  ".${work_site}/${vendor}__${project}${sim_library_path}/icarus/${sim_name}";

      $cmd ="iverilog   -f ../../testbenches/filelists/${sim_variant}.sim -D VCD  2>   ./${sim_name}_elab.log  | tee >> ./${$sim_name}_elab.log \n";
      if (system($cmd)) {}
      $cmd ="./a.out 2>    ./${sim_name}_sim.log     | tee >> ./${sim_name}_sim.log  \n";
      if (system($cmd)) {}
      $cmd ="grep PASSED  ./${sim_name}_sim.log \n";
      if (system($cmd)) {}
      $cmd ="rm a.out \n";
      if (system($cmd)) {}

      chdir $home;
      }



   foreach  my   $i_name ($sogen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:verilator/socgen:test/socgen:name"))
      {
      my($sim_name)     = $i_name ->findnodes('./text()')->to_literal ;
      my($sim_configuration)  = $i_name ->findnodes('../socgen:configuration/text()')->to_literal ;
      my($sim_variant)  = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
      print "  VSIMs     $sim_name        $sim_configuration   $sim_variant   "; 
      chdir  ".${work_site}/${vendor}__${project}${sim_library_path}/verilator/${sim_name}";
      $cmd ="make verilator\n";
      if (system($cmd)) {}
      chdir $home;
      }

   }



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