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//**************************************************************
//  Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.        
//  File Name    : unisim_comp.v
//  Library      : unisim uni9000
//  Release      : 10.1
//  Module Count : 1105
//  Generated by : gencomp
//**************************************************************
 
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND2B1 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND2B2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND3B1 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND3B2 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND3B3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND4B1 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND4B2 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND4B3 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND4B4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND5B1 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND5B2 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND5B3 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND5B4 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND5B5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND6 (O, I0, I1, I2, I3, I4, I5);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND7 (O, I0, I1, I2, I3, I4, I5, I6);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module AND8 (O, I0, I1, I2, I3, I4, I5, I6, I7);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BSCAN_FPGACORE (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
output CAPTURE;
output DRCK1;
output DRCK2;
output RESET;
output SEL1;
output SEL2;
output SHIFT;
output TDI;
output UPDATE;
input TDO1;
input TDO2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BSCAN_SPARTAN2 (DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
output DRCK1;
output DRCK2;
output RESET;
output SEL1;
output SEL2;
output SHIFT;
output TDI;
output UPDATE;
input TDO1;
input TDO2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BSCAN_SPARTAN3A (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TCK, TDI, TMS, UPDATE, TDO1, TDO2);
output CAPTURE;
output DRCK1;
output DRCK2;
output RESET;
output SEL1;
output SEL2;
output SHIFT;
output TCK;
output TDI;
output TMS;
output UPDATE;
input TDO1;
input TDO2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BSCAN_SPARTAN3 (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
output CAPTURE;
output DRCK1;
output DRCK2;
output RESET;
output SEL1;
output SEL2;
output SHIFT;
output TDI;
output UPDATE;
input TDO1;
input TDO2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BSCAN_VIRTEX2 (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
output CAPTURE;
output DRCK1;
output DRCK2;
output RESET;
output SEL1;
output SEL2;
output SHIFT;
output TDI;
output UPDATE;
input TDO1;
input TDO2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BSCAN_VIRTEX4 (CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO);
parameter integer JTAG_CHAIN = 1;
output CAPTURE;
output DRCK;
output RESET;
output SEL;
output SHIFT;
output TDI;
output UPDATE;
input TDO;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BSCAN_VIRTEX5 (CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO);
parameter integer JTAG_CHAIN = 1;
output CAPTURE;
output DRCK;
output RESET;
output SEL;
output SHIFT;
output TDI;
output UPDATE;
input TDO;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BSCAN_VIRTEX (DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
output DRCK1;
output DRCK2;
output RESET;
output SEL1;
output SEL2;
output SHIFT;
output TDI;
output UPDATE;
input TDO1;
input TDO2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFCF (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFE (O, E, I);
output O;
input E;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFFOE (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGCE_1 (O, CE, I);
output O;
input CE;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGCE (O, CE, I);
output O;
input CE;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGCTRL (O, CE0, CE1, I0, I1, IGNORE0, IGNORE1, S0, S1);
parameter integer INIT_OUT = 0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
output O;
input CE0;
input CE1;
input I0;
input I1;
input IGNORE0;
input IGNORE1;
input S0;
input S1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGDLL (O, I);
parameter DUTY_CYCLE_CORRECTION = "TRUE";
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGMUX_1 (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGMUX_CTRL (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGMUX (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGMUX_VIRTEX4 (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGP (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGSR (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFGTS (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFG (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFIO (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFR (O, CE, CLR, I);
parameter BUFR_DIVIDE = "BYPASS";
parameter SIM_DEVICE = "VIRTEX4";
output O;
input CE;
input CLR;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUFT (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module BUF (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CAPTURE_FPGACORE (CAP, CLK);
parameter ONESHOT = "FALSE";
input CAP;
input CLK;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CAPTURE_SPARTAN2 (CAP, CLK);
parameter ONESHOT = "FALSE";
input CAP;
input CLK;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CAPTURE_SPARTAN3A (CAP, CLK);
parameter ONESHOT = "TRUE";
input CAP;
input CLK;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CAPTURE_SPARTAN3 (CAP, CLK);
parameter ONESHOT = "FALSE";
input CAP;
input CLK;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CAPTURE_VIRTEX2 (CAP, CLK);
parameter ONESHOT = "FALSE";
input CAP;
input CLK;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CAPTURE_VIRTEX4 (CAP, CLK);
parameter ONESHOT = "TRUE";
input CAP;
input CLK;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CAPTURE_VIRTEX5 (CAP, CLK);
parameter ONESHOT = "TRUE";
input CAP;
input CLK;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CAPTURE_VIRTEX (CAP, CLK);
parameter ONESHOT = "FALSE";
input CAP;
input CLK;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CARRY4 (CO, O, CI, CYINIT, DI, S);
output [3:0] CO;
output [3:0] O;
input CI;
input CYINIT;
input [3:0] DI;
input [3:0] S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CFGLUT5 (CDO, O5, O6, CDI, CE, CLK, I0, I1, I2, I3, I4);
parameter INIT = 32'h00000000;
output CDO;
output O5;
output O6;
input CDI;
input CE;
input CLK;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV10RSD (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 10;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV10R (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 10;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV10SD (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 10;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV10 (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 10;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV12RSD (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 12;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV12R (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 12;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV12SD (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 12;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV12 (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 12;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV14RSD (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 14;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV14R (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 14;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV14SD (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 14;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV14 (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 14;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV16RSD (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 16;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV16R (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 16;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV16SD (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 16;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV16 (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 16;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV2RSD (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 2;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV2R (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 2;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV2SD (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 2;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV2 (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 2;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV4RSD (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 4;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV4R (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 4;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV4SD (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 4;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV4 (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 4;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV6RSD (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 6;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV6R (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 6;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV6SD (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 6;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV6 (CLKIN, CLKDV);
parameter integer DIVIDE_BY = 6;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV8RSD (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 8;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV8R (CLKDV, CDRST, CLKIN);
parameter integer DIVIDE_BY = 8;
output CLKDV;
input CDRST;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV8SD (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 8;
parameter integer DIVIDER_DELAY = 1;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLK_DIV8 (CLKDV, CLKIN);
parameter integer DIVIDE_BY = 8;
output CLKDV;
input CLKIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLKDLLE (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, LOCKED, CLKFB, CLKIN, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hC080;
parameter STARTUP_WAIT = "FALSE";
output CLK0;
output CLK180;
output CLK270;
output CLK2X;
output CLK2X180;
output CLK90;
output CLKDV;
output LOCKED;
input CLKFB;
input CLKIN;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLKDLLHF (CLK0, CLK180, CLKDV, LOCKED, CLKFB, CLKIN, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hFFF0;
parameter STARTUP_WAIT = "FALSE";
output CLK0;
output CLK180;
output CLKDV;
output LOCKED;
input CLKFB;
input CLKIN;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CLKDLL (CLK0, CLK180, CLK270, CLK2X, CLK90, CLKDV, LOCKED, CLKFB, CLKIN, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hC080;
parameter STARTUP_WAIT = "FALSE";
output CLK0;
output CLK180;
output CLK270;
output CLK2X;
output CLK90;
output CLKDV;
output LOCKED;
input CLKFB;
input CLKIN;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CONFIG ();
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CRC32 (CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET);
parameter CRC_INIT = 32'hFFFFFFFF;
output [31:0] CRCOUT;
input CRCCLK;
input CRCDATAVALID;
input [2:0] CRCDATAWIDTH;
input [31:0] CRCIN;
input CRCRESET;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module CRC64 (CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET);
parameter CRC_INIT = 32'hFFFFFFFF;
output [31:0] CRCOUT;
input CRCCLK;
input CRCDATAVALID;
input [2:0] CRCDATAWIDTH;
input [63:0] CRCIN;
input CRCRESET;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DCC_FPGACORE (BCLK, DONEOUT, DOUT0, DOUT1, DOUT2, DOUT3, DOUT4, DOUT5, DOUT6, DOUT7, GSR, GTS, GWE, INITBOUT, TDO, CCLK, CSB, DIN0, DIN1, DIN2, DIN3, DIN4, DIN5, DIN6, DIN7, DONEIN, LBISTISOLATEB, M0, M1, M2, PROGB, TCK, TDI, TMS, WRITEB);
parameter DEVICE_SIZE = 9'd10;
output BCLK;
output DONEOUT;
output DOUT0;
output DOUT1;
output DOUT2;
output DOUT3;
output DOUT4;
output DOUT5;
output DOUT6;
output DOUT7;
output GSR;
output GTS;
output GWE;
output INITBOUT;
output TDO;
input CCLK;
input CSB;
input DIN0;
input DIN1;
input DIN2;
input DIN3;
input DIN4;
input DIN5;
input DIN6;
input DIN7;
input DONEIN;
input LBISTISOLATEB;
input M0;
input M1;
input M2;
input PROGB;
input TCK;
input TDI;
input TMS;
input WRITEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DCIRESET (LOCKED, RST);
output LOCKED;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DCM_ADV (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, DO, DRDY, LOCKED, PSDONE, CLKFB, CLKIN, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter real CLKIN_PERIOD = 10.0;
parameter CLKOUT_PHASE_SHIFT = "NONE";
parameter CLK_FEEDBACK = "1X";
parameter DCM_AUTOCALIBRATION = "TRUE";
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
parameter DFS_FREQUENCY_MODE = "LOW";
parameter DLL_FREQUENCY_MODE = "LOW";
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hF0F0;
parameter integer PHASE_SHIFT = 0;
parameter SIM_DEVICE = "VIRTEX4";
parameter STARTUP_WAIT = "FALSE";
output CLK0;
output CLK180;
output CLK270;
output CLK2X;
output CLK2X180;
output CLK90;
output CLKDV;
output CLKFX;
output CLKFX180;
output [15:0] DO;
output DRDY;
output LOCKED;
output PSDONE;
input CLKFB;
input CLKIN;
input [6:0] DADDR;
input DCLK;
input DEN;
input [15:0] DI;
input DWE;
input PSCLK;
input PSEN;
input PSINCDEC;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DCM_BASE (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, CLKFB, CLKIN, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter real CLKIN_PERIOD = 10.0;
parameter CLKOUT_PHASE_SHIFT = "NONE";
parameter CLK_FEEDBACK = "1X";
parameter DCM_AUTOCALIBRATION = "TRUE";
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
parameter DFS_FREQUENCY_MODE = "LOW";
parameter DLL_FREQUENCY_MODE = "LOW";
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hF0F0;
parameter integer PHASE_SHIFT = 0;
parameter STARTUP_WAIT = "FALSE";
output CLK0;
output CLK180;
output CLK270;
output CLK2X;
output CLK2X180;
output CLK90;
output CLKDV;
output CLKFX;
output CLKFX180;
output LOCKED;
input CLKFB;
input CLKIN;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DCM_PS (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, DO, LOCKED, PSDONE, CLKFB, CLKIN, PSCLK, PSEN, PSINCDEC, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter real CLKIN_PERIOD = 10.0;
parameter CLKOUT_PHASE_SHIFT = "NONE";
parameter CLK_FEEDBACK = "1X";
parameter DCM_AUTOCALIBRATION = "TRUE";
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
parameter DFS_FREQUENCY_MODE = "LOW";
parameter DLL_FREQUENCY_MODE = "LOW";
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hF0F0;
parameter integer PHASE_SHIFT = 0;
parameter STARTUP_WAIT = "FALSE";
output CLK0;
output CLK180;
output CLK270;
output CLK2X;
output CLK2X180;
output CLK90;
output CLKDV;
output CLKFX;
output CLKFX180;
output [15:0] DO;
output LOCKED;
output PSDONE;
input CLKFB;
input CLKIN;
input PSCLK;
input PSEN;
input PSINCDEC;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DCM_SP (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter real CLKIN_PERIOD = 10.0;
parameter CLKOUT_PHASE_SHIFT = "NONE";
parameter CLK_FEEDBACK = "1X";
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
parameter DFS_FREQUENCY_MODE = "LOW";
parameter DLL_FREQUENCY_MODE = "LOW";
parameter DSS_MODE = "NONE";
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hC080;
parameter integer PHASE_SHIFT = 0;
parameter STARTUP_WAIT = "FALSE";
output CLK0;
output CLK180;
output CLK270;
output CLK2X;
output CLK2X180;
output CLK90;
output CLKDV;
output CLKFX;
output CLKFX180;
output LOCKED;
output PSDONE;
output [7:0] STATUS;
input CLKFB;
input CLKIN;
input DSSEN;
input PSCLK;
input PSEN;
input PSINCDEC;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DCM (CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter real CLKIN_PERIOD = 10.0;
parameter CLKOUT_PHASE_SHIFT = "NONE";
parameter CLK_FEEDBACK = "1X";
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
parameter DFS_FREQUENCY_MODE = "LOW";
parameter DLL_FREQUENCY_MODE = "LOW";
parameter DSS_MODE = "NONE";
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hC080;
parameter integer PHASE_SHIFT = 0;
parameter SIM_MODE = "SAFE";
parameter STARTUP_WAIT = "FALSE";
output CLK0;
output CLK180;
output CLK270;
output CLK2X;
output CLK2X180;
output CLK90;
output CLKDV;
output CLKFX;
output CLKFX180;
output LOCKED;
output PSDONE;
output [7:0] STATUS;
input CLKFB;
input CLKIN;
input DSSEN;
input PSCLK;
input PSEN;
input PSINCDEC;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT);
parameter SIM_DNA_VALUE = 57'h0;
output DOUT;
input CLK;
input DIN;
input READ;
input SHIFT;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DSP48A (BCOUT, CARRYOUT, P, PCOUT, A, B, C, CARRYIN, CEA, CEB, CEC, CECARRYIN, CED, CEM, CEOPMODE, CEP, CLK, D, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTD, RSTM, RSTOPMODE, RSTP);
parameter integer A0REG = 0;
parameter integer A1REG = 1;
parameter integer B0REG = 0;
parameter integer B1REG = 1;
parameter integer CARRYINREG = 1;
parameter CARRYINSEL = "CARRYIN";
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer MREG = 1;
parameter integer OPMODEREG = 1;
parameter integer PREG = 1;
parameter RSTTYPE = "SYNC";
output [17:0] BCOUT;
output CARRYOUT;
output [47:0] P;
output [47:0] PCOUT;
input [17:0] A;
input [17:0] B;
input [47:0] C;
input CARRYIN;
input CEA;
input CEB;
input CEC;
input CECARRYIN;
input CED;
input CEM;
input CEOPMODE;
input CEP;
input CLK;
input [17:0] D;
input [7:0] OPMODE;
input [47:0] PCIN;
input RSTA;
input RSTB;
input RSTC;
input RSTCARRYIN;
input RSTD;
input RSTM;
input RSTOPMODE;
input RSTP;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DSP48E (ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL, CEA1, CEA2, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CEM, CEMULTCARRYIN, CEP, CLK, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTM, RSTP);
parameter SIM_MODE = "SAFE";
parameter integer ACASCREG = 1;
parameter integer ALUMODEREG = 1;
parameter integer AREG = 1;
parameter AUTORESET_PATTERN_DETECT = "FALSE";
parameter AUTORESET_PATTERN_DETECT_OPTINV = "MATCH";
parameter A_INPUT = "DIRECT";
parameter integer BCASCREG = 1;
parameter integer BREG = 1;
parameter B_INPUT = "DIRECT";
parameter integer CARRYINREG = 1;
parameter integer CARRYINSELREG = 1;
parameter integer CREG = 1;
parameter MASK = 48'h3FFFFFFFFFFF;
parameter integer MREG = 1;
parameter integer MULTCARRYINREG = 1;
parameter integer OPMODEREG = 1;
parameter PATTERN = 48'h000000000000;
parameter integer PREG = 1;
parameter SEL_MASK = "MASK";
parameter SEL_PATTERN = "PATTERN";
parameter SEL_ROUNDING_MASK = "SEL_MASK";
parameter USE_MULT = "MULT_S";
parameter USE_PATTERN_DETECT = "NO_PATDET";
parameter USE_SIMD = "ONE48";
output [29:0] ACOUT;
output [17:0] BCOUT;
output CARRYCASCOUT;
output [3:0] CARRYOUT;
output MULTSIGNOUT;
output OVERFLOW;
output [47:0] P;
output PATTERNBDETECT;
output PATTERNDETECT;
output [47:0] PCOUT;
output UNDERFLOW;
input [29:0] A;
input [29:0] ACIN;
input [3:0] ALUMODE;
input [17:0] B;
input [17:0] BCIN;
input [47:0] C;
input CARRYCASCIN;
input CARRYIN;
input [2:0] CARRYINSEL;
input CEA1;
input CEA2;
input CEALUMODE;
input CEB1;
input CEB2;
input CEC;
input CECARRYIN;
input CECTRL;
input CEM;
input CEMULTCARRYIN;
input CEP;
input CLK;
input MULTSIGNIN;
input [6:0] OPMODE;
input [47:0] PCIN;
input RSTA;
input RSTALLCARRYIN;
input RSTALUMODE;
input RSTB;
input RSTC;
input RSTCTRL;
input RSTM;
input RSTP;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module DSP48 (BCOUT, P, PCOUT, A, B, BCIN, C, CARRYIN, CARRYINSEL, CEA, CEB, CEC, CECARRYIN, CECINSUB, CECTRL, CEM, CEP, CLK, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTCTRL, RSTM, RSTP, SUBTRACT);
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter B_INPUT = "DIRECT";
parameter integer CARRYINREG = 1;
parameter integer CARRYINSELREG = 1;
parameter integer CREG = 1;
parameter LEGACY_MODE = "MULT18X18S";
parameter integer MREG = 1;
parameter integer OPMODEREG = 1;
parameter integer PREG = 1;
parameter integer SUBTRACTREG = 1;
output [17:0] BCOUT;
output [47:0] P;
output [47:0] PCOUT;
input [17:0] A;
input [17:0] B;
input [17:0] BCIN;
input [47:0] C;
input CARRYIN;
input [1:0] CARRYINSEL;
input CEA;
input CEB;
input CEC;
input CECARRYIN;
input CECINSUB;
input CECTRL;
input CEM;
input CEP;
input CLK;
input [6:0] OPMODE;
input [47:0] PCIN;
input RSTA;
input RSTB;
input RSTC;
input RSTCARRYIN;
input RSTCTRL;
input RSTM;
input RSTP;
input SUBTRACT;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module EMAC (DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXD, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXDVREG6, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATS, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXGMIIMIICLKOUT, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXD, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXD, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXDVREG6, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME, EMAC1CLIENTRXSTATS, EMAC1CLIENTRXSTATSBYTEVLD, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXGMIIMIICLKOUT, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK, EMAC1PHYTXD, EMAC1PHYTXEN, EMAC1PHYTXER, EMACDCRACK, EMACDCRDBUS, HOSTMIIMRDY, HOSTRDDATA, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXD, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE, CLIENTEMAC0TXGMIIMIICLKIN, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1PAUSEVAL, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXD, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXGMIIMIICLKIN, CLIENTEMAC1TXIFGDELAY, CLIENTEMAC1TXUNDERRUN, DCREMACABUS, DCREMACCLK, DCREMACDBUS, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTADDR, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTOPCODE, HOSTREQ, HOSTWRDATA, PHYEMAC0COL, PHYEMAC0CRS, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0PHYAD, PHYEMAC0RXBUFERR, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCLKCORCNT, PHYEMAC0RXCOMMADET, PHYEMAC0RXD, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXLOSSOFSYNC, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN, PHYEMAC1MDIN, PHYEMAC1MIITXCLK, PHYEMAC1PHYAD, PHYEMAC1RXBUFERR, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCLKCORCNT, PHYEMAC1RXCOMMADET, PHYEMAC1RXD, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXLOSSOFSYNC, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, RESET, TIEEMAC0CONFIGVEC, TIEEMAC0UNICASTADDR, TIEEMAC1CONFIGVEC, TIEEMAC1UNICASTADDR);
output DCRHOSTDONEIR;
output EMAC0CLIENTANINTERRUPT;
output EMAC0CLIENTRXBADFRAME;
output EMAC0CLIENTRXCLIENTCLKOUT;
output [15:0] EMAC0CLIENTRXD;
output EMAC0CLIENTRXDVLD;
output EMAC0CLIENTRXDVLDMSW;
output EMAC0CLIENTRXDVREG6;
output EMAC0CLIENTRXFRAMEDROP;
output EMAC0CLIENTRXGOODFRAME;
output [6:0] EMAC0CLIENTRXSTATS;
output EMAC0CLIENTRXSTATSBYTEVLD;
output EMAC0CLIENTRXSTATSVLD;
output EMAC0CLIENTTXACK;
output EMAC0CLIENTTXCLIENTCLKOUT;
output EMAC0CLIENTTXCOLLISION;
output EMAC0CLIENTTXGMIIMIICLKOUT;
output EMAC0CLIENTTXRETRANSMIT;
output EMAC0CLIENTTXSTATS;
output EMAC0CLIENTTXSTATSBYTEVLD;
output EMAC0CLIENTTXSTATSVLD;
output EMAC0PHYENCOMMAALIGN;
output EMAC0PHYLOOPBACKMSB;
output EMAC0PHYMCLKOUT;
output EMAC0PHYMDOUT;
output EMAC0PHYMDTRI;
output EMAC0PHYMGTRXRESET;
output EMAC0PHYMGTTXRESET;
output EMAC0PHYPOWERDOWN;
output EMAC0PHYSYNCACQSTATUS;
output EMAC0PHYTXCHARDISPMODE;
output EMAC0PHYTXCHARDISPVAL;
output EMAC0PHYTXCHARISK;
output EMAC0PHYTXCLK;
output [7:0] EMAC0PHYTXD;
output EMAC0PHYTXEN;
output EMAC0PHYTXER;
output EMAC1CLIENTANINTERRUPT;
output EMAC1CLIENTRXBADFRAME;
output EMAC1CLIENTRXCLIENTCLKOUT;
output [15:0] EMAC1CLIENTRXD;
output EMAC1CLIENTRXDVLD;
output EMAC1CLIENTRXDVLDMSW;
output EMAC1CLIENTRXDVREG6;
output EMAC1CLIENTRXFRAMEDROP;
output EMAC1CLIENTRXGOODFRAME;
output [6:0] EMAC1CLIENTRXSTATS;
output EMAC1CLIENTRXSTATSBYTEVLD;
output EMAC1CLIENTRXSTATSVLD;
output EMAC1CLIENTTXACK;
output EMAC1CLIENTTXCLIENTCLKOUT;
output EMAC1CLIENTTXCOLLISION;
output EMAC1CLIENTTXGMIIMIICLKOUT;
output EMAC1CLIENTTXRETRANSMIT;
output EMAC1CLIENTTXSTATS;
output EMAC1CLIENTTXSTATSBYTEVLD;
output EMAC1CLIENTTXSTATSVLD;
output EMAC1PHYENCOMMAALIGN;
output EMAC1PHYLOOPBACKMSB;
output EMAC1PHYMCLKOUT;
output EMAC1PHYMDOUT;
output EMAC1PHYMDTRI;
output EMAC1PHYMGTRXRESET;
output EMAC1PHYMGTTXRESET;
output EMAC1PHYPOWERDOWN;
output EMAC1PHYSYNCACQSTATUS;
output EMAC1PHYTXCHARDISPMODE;
output EMAC1PHYTXCHARDISPVAL;
output EMAC1PHYTXCHARISK;
output EMAC1PHYTXCLK;
output [7:0] EMAC1PHYTXD;
output EMAC1PHYTXEN;
output EMAC1PHYTXER;
output EMACDCRACK;
output [0:31] EMACDCRDBUS;
output HOSTMIIMRDY;
output [31:0] HOSTRDDATA;
input CLIENTEMAC0DCMLOCKED;
input CLIENTEMAC0PAUSEREQ;
input [15:0] CLIENTEMAC0PAUSEVAL;
input CLIENTEMAC0RXCLIENTCLKIN;
input CLIENTEMAC0TXCLIENTCLKIN;
input [15:0] CLIENTEMAC0TXD;
input CLIENTEMAC0TXDVLD;
input CLIENTEMAC0TXDVLDMSW;
input CLIENTEMAC0TXFIRSTBYTE;
input CLIENTEMAC0TXGMIIMIICLKIN;
input [7:0] CLIENTEMAC0TXIFGDELAY;
input CLIENTEMAC0TXUNDERRUN;
input CLIENTEMAC1DCMLOCKED;
input CLIENTEMAC1PAUSEREQ;
input [15:0] CLIENTEMAC1PAUSEVAL;
input CLIENTEMAC1RXCLIENTCLKIN;
input CLIENTEMAC1TXCLIENTCLKIN;
input [15:0] CLIENTEMAC1TXD;
input CLIENTEMAC1TXDVLD;
input CLIENTEMAC1TXDVLDMSW;
input CLIENTEMAC1TXFIRSTBYTE;
input CLIENTEMAC1TXGMIIMIICLKIN;
input [7:0] CLIENTEMAC1TXIFGDELAY;
input CLIENTEMAC1TXUNDERRUN;
input [8:9] DCREMACABUS;
input DCREMACCLK;
input [0:31] DCREMACDBUS;
input DCREMACENABLE;
input DCREMACREAD;
input DCREMACWRITE;
input [9:0] HOSTADDR;
input HOSTCLK;
input HOSTEMAC1SEL;
input HOSTMIIMSEL;
input [1:0] HOSTOPCODE;
input HOSTREQ;
input [31:0] HOSTWRDATA;
input PHYEMAC0COL;
input PHYEMAC0CRS;
input PHYEMAC0GTXCLK;
input PHYEMAC0MCLKIN;
input PHYEMAC0MDIN;
input PHYEMAC0MIITXCLK;
input [4:0] PHYEMAC0PHYAD;
input PHYEMAC0RXBUFERR;
input [1:0] PHYEMAC0RXBUFSTATUS;
input PHYEMAC0RXCHARISCOMMA;
input PHYEMAC0RXCHARISK;
input PHYEMAC0RXCHECKINGCRC;
input PHYEMAC0RXCLK;
input [2:0] PHYEMAC0RXCLKCORCNT;
input PHYEMAC0RXCOMMADET;
input [7:0] PHYEMAC0RXD;
input PHYEMAC0RXDISPERR;
input PHYEMAC0RXDV;
input PHYEMAC0RXER;
input [1:0] PHYEMAC0RXLOSSOFSYNC;
input PHYEMAC0RXNOTINTABLE;
input PHYEMAC0RXRUNDISP;
input PHYEMAC0SIGNALDET;
input PHYEMAC0TXBUFERR;
input PHYEMAC1COL;
input PHYEMAC1CRS;
input PHYEMAC1GTXCLK;
input PHYEMAC1MCLKIN;
input PHYEMAC1MDIN;
input PHYEMAC1MIITXCLK;
input [4:0] PHYEMAC1PHYAD;
input PHYEMAC1RXBUFERR;
input [1:0] PHYEMAC1RXBUFSTATUS;
input PHYEMAC1RXCHARISCOMMA;
input PHYEMAC1RXCHARISK;
input PHYEMAC1RXCHECKINGCRC;
input PHYEMAC1RXCLK;
input [2:0] PHYEMAC1RXCLKCORCNT;
input PHYEMAC1RXCOMMADET;
input [7:0] PHYEMAC1RXD;
input PHYEMAC1RXDISPERR;
input PHYEMAC1RXDV;
input PHYEMAC1RXER;
input [1:0] PHYEMAC1RXLOSSOFSYNC;
input PHYEMAC1RXNOTINTABLE;
input PHYEMAC1RXRUNDISP;
input PHYEMAC1SIGNALDET;
input PHYEMAC1TXBUFERR;
input RESET;
input [79:0] TIEEMAC0CONFIGVEC;
input [47:0] TIEEMAC0UNICASTADDR;
input [79:0] TIEEMAC1CONFIGVEC;
input [47:0] TIEEMAC1UNICASTADDR;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FD_1 (Q, C, D);
parameter INIT = 1'b0;
output Q;
input C;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDC_1 (Q, C, CLR, D);
parameter INIT = 1'b0;
output Q;
input C;
input CLR;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDCE_1 (Q, C, CE, CLR, D);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input CLR;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDCE (Q, C, CE, CLR, D);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input CLR;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDCP_1 (Q, C, CLR, D, PRE);
parameter INIT = 1'b0;
output Q;
input C;
input CLR;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDCPE_1 (Q, C, CE, CLR, D, PRE);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input CLR;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDCPE (Q, C, CE, CLR, D, PRE);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input CLR;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDCP (Q, C, CLR, D, PRE);
parameter INIT = 1'b0;
output Q;
input C;
input CLR;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDCPX1 (Q, C, CLR, D, PRE);
output Q;
input C;
input CLR;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDC (Q, C, CLR, D);
parameter INIT = 1'b0;
output Q;
input C;
input CLR;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDDCE (Q, C, CE, CLR, D);
output Q;
input C;
input CE;
input CLR;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDDCPE (Q, C, CE, CLR, D, PRE);
output Q;
input C;
input CE;
input CLR;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDDCP (Q, C, CLR, D, PRE);
parameter INIT = 1'b0;
output Q;
input C;
input CLR;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDDC (Q, C, CLR, D);
parameter INIT = 1'b0;
output Q;
input C;
input CLR;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDDPE (Q, C, CE, D, PRE);
output Q;
input C;
input CE;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDDP (Q, C, D, PRE);
parameter INIT = 1'b1;
output Q;
input C;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDDRCPE (Q, C0, C1, CE, CLR, D0, D1, PRE);
parameter INIT = 1'b0;
output Q;
input C0;
input C1;
input CE;
input CLR;
input D0;
input D1;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
parameter INIT = 1'b0;
output Q;
input C0;
input C1;
input CE;
input D0;
input D1;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDD (Q, C, D);
parameter INIT = 1'b0;
output Q;
input C;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDE_1 (Q, C, CE, D);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDE (Q, C, CE, D);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDP_1 (Q, C, D, PRE);
parameter INIT = 1'b1;
output Q;
input C;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDPE_1 (Q, C, CE, D, PRE);
parameter INIT = 1'b1;
output Q;
input C;
input CE;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDPE (Q, C, CE, D, PRE);
parameter INIT = 1'b1;
output Q;
input C;
input CE;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDP (Q, C, D, PRE);
parameter INIT = 1'b1;
output Q;
input C;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDR_1 (Q, C, D, R);
parameter INIT = 1'b0;
output Q;
input C;
input D;
input R;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDRE_1 (Q, C, CE, D, R);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input D;
input R;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDRE (Q, C, CE, D, R);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input D;
input R;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDRS_1 (Q, C, D, R, S);
parameter INIT = 1'b0;
output Q;
input C;
input D;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDRSE_1 (Q, C, CE, D, R, S);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input D;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDRSE (Q, C, CE, D, R, S);
parameter INIT = 1'b0;
output Q;
input C;
input CE;
input D;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDRS (Q, C, D, R, S);
parameter INIT = 1'b0;
output Q;
input C;
input D;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDR (Q, C, D, R);
parameter INIT = 1'b0;
output Q;
input C;
input D;
input R;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDS_1 (Q, C, D, S);
parameter INIT = 1'b1;
output Q;
input C;
input D;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDSE_1 (Q, C, CE, D, S);
parameter INIT = 1'b1;
output Q;
input C;
input CE;
input D;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDSE (Q, C, CE, D, S);
parameter INIT = 1'b1;
output Q;
input C;
input CE;
input D;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FDS (Q, C, D, S);
parameter INIT = 1'b1;
output Q;
input C;
input D;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FD (Q, C, D);
parameter INIT = 1'b0;
output Q;
input C;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FIFO16 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
parameter ALMOST_FULL_OFFSET = 12'h080;
parameter ALMOST_EMPTY_OFFSET = 12'h080;
parameter integer DATA_WIDTH = 36;
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
output ALMOSTEMPTY;
output ALMOSTFULL;
output [31:0] DO;
output [3:0] DOP;
output EMPTY;
output FULL;
output [11:0] RDCOUNT;
output RDERR;
output [11:0] WRCOUNT;
output WRERR;
input [31:0] DI;
input [3:0] DIP;
input RDCLK;
input RDEN;
input RST;
input WRCLK;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FIFO18_36 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
parameter ALMOST_EMPTY_OFFSET = 9'h080;
parameter ALMOST_FULL_OFFSET = 9'h080;
parameter integer DO_REG = 1;
parameter EN_SYN = "FALSE";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter SIM_MODE = "SAFE";
output ALMOSTEMPTY;
output ALMOSTFULL;
output [31:0] DO;
output [3:0] DOP;
output EMPTY;
output FULL;
output [8:0] RDCOUNT;
output RDERR;
output [8:0] WRCOUNT;
output WRERR;
input [31:0] DI;
input [3:0] DIP;
input RDCLK;
input RDEN;
input RST;
input WRCLK;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FIFO18 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
parameter ALMOST_EMPTY_OFFSET = 12'h080;
parameter ALMOST_FULL_OFFSET = 12'h080;
parameter integer DATA_WIDTH = 4;
parameter integer DO_REG = 1;
parameter EN_SYN = "FALSE";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter SIM_MODE = "SAFE";
output ALMOSTEMPTY;
output ALMOSTFULL;
output [15:0] DO;
output [1:0] DOP;
output EMPTY;
output FULL;
output [11:0] RDCOUNT;
output RDERR;
output [11:0] WRCOUNT;
output WRERR;
input [15:0] DI;
input [1:0] DIP;
input RDCLK;
input RDEN;
input RST;
input WRCLK;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FIFO36_72_EXP (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, RDCLKL, RDCLKU, RDEN, RDRCLKL, RDRCLKU, RST, WRCLKL, WRCLKU, WREN);
parameter ALMOST_EMPTY_OFFSET = 9'h080;
parameter ALMOST_FULL_OFFSET = 9'h080;
parameter integer DO_REG = 1;
parameter EN_ECC_WRITE = "FALSE";
parameter EN_ECC_READ = "FALSE";
parameter EN_SYN = "FALSE";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter SIM_MODE = "SAFE";
output ALMOSTEMPTY;
output ALMOSTFULL;
output DBITERR;
output [63:0] DO;
output [7:0] DOP;
output [7:0] ECCPARITY;
output EMPTY;
output FULL;
output [12:0] RDCOUNT;
output RDERR;
output SBITERR;
output [12:0] WRCOUNT;
output WRERR;
input [63:0] DI;
input [7:0] DIP;
input RDCLKL;
input RDCLKU;
input RDEN;
input RDRCLKL;
input RDRCLKU;
input RST;
input WRCLKL;
input WRCLKU;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FIFO36_72 (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
parameter ALMOST_EMPTY_OFFSET = 9'h080;
parameter ALMOST_FULL_OFFSET = 9'h080;
parameter integer DO_REG = 1;
parameter EN_ECC_WRITE = "FALSE";
parameter EN_ECC_READ = "FALSE";
parameter EN_SYN = "FALSE";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter SIM_MODE = "SAFE";
output ALMOSTEMPTY;
output ALMOSTFULL;
output DBITERR;
output [63:0] DO;
output [7:0] DOP;
output [7:0] ECCPARITY;
output EMPTY;
output FULL;
output [8:0] RDCOUNT;
output RDERR;
output SBITERR;
output [8:0] WRCOUNT;
output WRERR;
input [63:0] DI;
input [7:0] DIP;
input RDCLK;
input RDEN;
input RST;
input WRCLK;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FIFO36_EXP (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLKL, RDCLKU, RDEN, RDRCLKL, RDRCLKU, RST, WRCLKL, WRCLKU, WREN);
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
parameter integer DATA_WIDTH = 4;
parameter integer DO_REG = 1;
parameter EN_SYN = "FALSE";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter SIM_MODE = "SAFE";
output ALMOSTEMPTY;
output ALMOSTFULL;
output [31:0] DO;
output [3:0] DOP;
output EMPTY;
output FULL;
output [12:0] RDCOUNT;
output RDERR;
output [12:0] WRCOUNT;
output WRERR;
input [31:0] DI;
input [3:0] DIP;
input RDCLKL;
input RDCLKU;
input RDEN;
input RDRCLKL;
input RDRCLKU;
input RST;
input WRCLKL;
input WRCLKU;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FIFO36 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
parameter integer DATA_WIDTH = 4;
parameter integer DO_REG = 1;
parameter EN_SYN = "FALSE";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter SIM_MODE = "SAFE";
output ALMOSTEMPTY;
output ALMOSTFULL;
output [31:0] DO;
output [3:0] DOP;
output EMPTY;
output FULL;
output [12:0] RDCOUNT;
output RDERR;
output [12:0] WRCOUNT;
output WRERR;
input [31:0] DI;
input [3:0] DIP;
input RDCLK;
input RDEN;
input RST;
input WRCLK;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FMAP (I1, I2, I3, I4, O);
input I1;
input I2;
input I3;
input I4;
input O;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FRAME_ECC_VIRTEX4 (ERROR, SYNDROME, SYNDROMEVALID);
output ERROR;
output [11:0] SYNDROME;
output SYNDROMEVALID;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FRAME_ECC_VIRTEX5 (CRCERROR, ECCERROR, SYNDROME, SYNDROMEVALID);
output CRCERROR;
output ECCERROR;
output [11:0] SYNDROME;
output SYNDROMEVALID;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FTCP (Q, C, CLR, PRE, T);
parameter INIT = 1'b0;
output Q;
input C;
input CLR;
input PRE;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FTC (Q, C, CLR, T);
output Q;
input C;
input CLR;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module FTP (Q, C, PRE, T);
output Q;
input C;
input PRE;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GND (G);
output G;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_10GE_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "TRUE";
parameter CHAN_BOND_64B66B_SV = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "TRUE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter CLK_CORRECT_USE = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_10GE_8 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "TRUE";
parameter CHAN_BOND_64B66B_SV = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "TRUE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter CLK_CORRECT_USE = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [63:0] RXDATA;
output [7:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [7:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [7:0] RXRUNDISP;
output TXBUFERR;
output [7:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [7:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [7:0] TXBYPASS8B10B;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input [63:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_10GFC_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "TRUE";
parameter CHAN_BOND_64B66B_SV = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "TRUE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter CLK_CORRECT_USE = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_10GFC_8 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "TRUE";
parameter CHAN_BOND_64B66B_SV = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "TRUE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter CLK_CORRECT_USE = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [63:0] RXDATA;
output [7:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [7:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [7:0] RXRUNDISP;
output TXBUFERR;
output [7:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [7:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [7:0] TXBYPASS8B10B;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input [63:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_AURORA_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter CLK_CORRECT_USE = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00fc0db00b0f32263068090104a628;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_AURORA_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter CLK_CORRECT_USE = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00fc0db00b0f32663068090105a628;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_AURORA_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter CLK_CORRECT_USE = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132663068090105a628;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_AURORAX_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_64B66B_SV = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter CLK_CORRECT_USE = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_AURORAX_8 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_64B66B_SV = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter CLK_CORRECT_USE = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [63:0] RXDATA;
output [7:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [7:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [7:0] RXRUNDISP;
output TXBUFERR;
output [7:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [7:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [7:0] TXBYPASS8B10B;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input [63:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_CUSTOM (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter CHAN_BOND_64B66B_SV = "FALSE";
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter CLK_CORRECT_USE = "TRUE";
parameter COMMA_10B_MASK = 10'b0001111111;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter MCOMMA_10B_VALUE = 10'b1010000011;
parameter MCOMMA_DETECT = "TRUE";
parameter PCOMMA_10B_VALUE = 10'b0101111100;
parameter PCOMMA_DETECT = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED = "0_32";
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [63:0] RXDATA;
output [7:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [7:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [7:0] RXRUNDISP;
output TXBUFERR;
output [7:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [7:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [7:0] TXBYPASS8B10B;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input [63:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_INFINIBAND_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 2;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter integer CHAN_BOND_SEQ_LEN = 2;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 2;
parameter CLK_CORRECT_USE = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter LANE_ID = 11'b00000000000;
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132263068090104a620;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_INFINIBAND_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 2;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter integer CHAN_BOND_SEQ_LEN = 2;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 2;
parameter CLK_CORRECT_USE = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter LANE_ID = 11'b00000000000;
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00fc0d300b0f32663068090105a620;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_INFINIBAND_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 2;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter integer CHAN_BOND_SEQ_LEN = 2;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 2;
parameter CLK_CORRECT_USE = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter LANE_ID = 11'b00000000000;
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132663068090105a620;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_OC192_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLKBSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter MCOMMA_10B_VALUE = 10'b0010101010;
parameter MCOMMA_DETECT = "TRUE";
parameter PCOMMA_10B_VALUE = 10'b0010101010;
parameter PCOMMA_DETECT = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504c00208c9050d0068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLKBSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_OC192_8 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLKBSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter MCOMMA_10B_VALUE = 10'b0010101010;
parameter MCOMMA_DETECT = "TRUE";
parameter PCOMMA_10B_VALUE = 10'b0010101010;
parameter PCOMMA_DETECT = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504c00208c9050d0068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [63:0] RXDATA;
output [7:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [7:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [7:0] RXRUNDISP;
output TXBUFERR;
output [7:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [7:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLKBSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [7:0] TXBYPASS8B10B;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input [63:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_OC48_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter MCOMMA_10B_VALUE = 10'b0010101010;
parameter MCOMMA_DETECT = "TRUE";
parameter PCOMMA_10B_VALUE = 10'b0010101010;
parameter PCOMMA_DETECT = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd500b01300830680901040820;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_OC48_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter MCOMMA_10B_VALUE = 10'b0010101010;
parameter MCOMMA_DETECT = "TRUE";
parameter PCOMMA_10B_VALUE = 10'b0010101010;
parameter PCOMMA_DETECT = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00fc0d300b0f304830680901050820;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_OC48_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter MCOMMA_10B_VALUE = 10'b0010101010;
parameter MCOMMA_DETECT = "TRUE";
parameter PCOMMA_10B_VALUE = 10'b0010101010;
parameter PCOMMA_DETECT = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd500b01304830680901050820;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_PCI_EXPRESS_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 2;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 2;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 2;
parameter CLK_CORRECT_USE = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132263068090104a620;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_PCI_EXPRESS_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 2;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 2;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 2;
parameter CLK_CORRECT_USE = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00fc0d300b0f32663068090105a620;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_PCI_EXPRESS_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 2;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 2;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 2;
parameter CLK_CORRECT_USE = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132663068090105a620;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 1;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter CHAN_BOND_64B66B_SV = "FALSE";
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter CLK_CORRECT_USE = "TRUE";
parameter COMMA_10B_MASK = 10'b0001111111;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter MCOMMA_10B_VALUE = 10'b1010000011;
parameter MCOMMA_DETECT = "TRUE";
parameter PCOMMA_10B_VALUE = 10'b0101111100;
parameter PCOMMA_DETECT = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED = "0_32";
parameter PMA_SPEED_HEX = 120'h00ffcd24ca1504d00208c9050d4068;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [63:0] RXDATA;
output [7:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [7:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [7:0] RXRUNDISP;
output TXBUFERR;
output [7:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [7:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [7:0] TXBYPASS8B10B;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input [63:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_XAUI_1 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 2;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 2;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 2;
parameter CLK_CORRECT_USE = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00fc0db00b0f32263068090104a628;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_XAUI_2 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 2;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 2;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 2;
parameter CLK_CORRECT_USE = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00fc0db00b0f32663068090105a628;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT10_XAUI_4 (CHBONDDONE, CHBONDO, PMARXLOCK, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCLKCORCNT, RXCOMMADET, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXOUTCLK, TXP, TXRUNDISP, BREFCLKNIN, BREFCLKPIN, CHBONDI, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, PMAINIT, PMAREGADDR, PMAREGDATAIN, PMAREGRW, PMAREGSTROBE, PMARXLOCKSEL, POWERDOWN, REFCLK, REFCLK2, REFCLKBSEL, REFCLKSEL, RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXN, RXP, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXUSRCLK, TXUSRCLK2);
parameter integer ALIGN_COMMA_WORD = 2;
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 2;
parameter CLK_COR_8B10B_DE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 36;
parameter integer CLK_COR_MIN_LAT = 28;
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 2;
parameter CLK_CORRECT_USE = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter PMA_PWR_CNTRL = 8'b11111111;
parameter PMA_SPEED_HEX = 120'h00ffcd500b0132663068090105a628;
parameter PMA_SPEED_USE = "PMA_SPEED";
parameter RX_BUFFER_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter TX_BUFFER_USE = "TRUE";
output CHBONDDONE;
output [4:0] CHBONDO;
output PMARXLOCK;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXOUTCLK;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLKNIN;
input BREFCLKPIN;
input [4:0] CHBONDI;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input PMAINIT;
input [5:0] PMAREGADDR;
input [7:0] PMAREGDATAIN;
input PMAREGRW;
input PMAREGSTROBE;
input [1:0] PMARXLOCKSEL;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKBSEL;
input REFCLKSEL;
input RXBLOCKSYNC64B66BUSE;
input RXCOMMADETUSE;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT11CLK_MGT (SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP);
parameter SYNCLK1OUTEN = "ENABLE";
parameter SYNCLK2OUTEN = "DISABLE";
output SYNCLK1OUT;
output SYNCLK2OUT;
input MGTCLKN;
input MGTCLKP;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT11CLK (SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP, REFCLK, RXBCLK, SYNCLK1IN, SYNCLK2IN);
parameter REFCLKSEL = "MGTCLK";
parameter SYNCLK1OUTEN = "ENABLE";
parameter SYNCLK2OUTEN = "DISABLE";
output SYNCLK1OUT;
output SYNCLK2OUT;
input MGTCLKN;
input MGTCLKP;
input REFCLK;
input RXBCLK;
input SYNCLK1IN;
input SYNCLK2IN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT11_CUSTOM (CHBONDO, DO, DRDY, RXBUFERR, RXCALFAIL, RXCHARISCOMMA, RXCHARISK, RXCOMMADET, RXCRCOUT, RXCYCLELIMIT, RXDATA, RXDISPERR, RXLOCK, RXLOSSOFSYNC, RXMCLK, RXNOTINTABLE, RXPCSHCLKOUT, RXREALIGN, RXRECCLK1, RXRECCLK2, RXRUNDISP, RXSIGDET, RXSTATUS, TX1N, TX1P, TXBUFERR, TXCALFAIL, TXCRCOUT, TXCYCLELIMIT, TXKERR, TXLOCK, TXOUTCLK1, TXOUTCLK2, TXPCSHCLKOUT, TXRUNDISP, CHBONDI, DADDR, DCLK, DEN, DI, DWE, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, GREFCLK, LOOPBACK, POWERDOWN, REFCLK1, REFCLK2, RX1N, RX1P, RXBLOCKSYNC64B66BUSE, RXCLKSTABLE, RXCOMMADETUSE, RXCRCCLK, RXCRCDATAVALID, RXCRCDATAWIDTH, RXCRCIN, RXCRCINIT, RXCRCINTCLK, RXCRCPD, RXCRCRESET, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXPMARESET, RXPOLARITY, RXRESET, RXSLIDE, RXSYNC, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXCLKSTABLE, TXCRCCLK, TXCRCDATAVALID, TXCRCDATAWIDTH, TXCRCIN, TXCRCINIT, TXCRCINTCLK, TXCRCPD, TXCRCRESET, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXENOOB, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPMARESET, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXSYNC, TXUSRCLK, TXUSRCLK2);
parameter BANDGAPSEL = "FALSE";
parameter BIASRESSEL = "FALSE";
parameter CCCB_ARBITRATOR_DISABLE = "FALSE";
parameter CHAN_BOND_MODE = "NONE";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_MASK = 4'b1110;
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b1110;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter CLK_CORRECT_USE = "FALSE";
parameter CLK_COR_8B10B_DE = "FALSE";
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
parameter CLK_COR_SEQ_1_MASK = 4'b1110;
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
parameter CLK_COR_SEQ_2_MASK = 4'b1110;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter COMMA32 = "FALSE";
parameter COMMA_10B_MASK = 10'h3FF;
parameter CYCLE_LIMIT_SEL = 2'b00;
parameter DCDR_FILTER = 3'b010;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter DIGRX_FWDCLK = 2'b00;
parameter DIGRX_SYNC_MODE = "FALSE";
parameter ENABLE_DCDR = "FALSE";
parameter FDET_HYS_CAL = 3'b010;
parameter FDET_HYS_SEL = 3'b100;
parameter FDET_LCK_CAL = 3'b100;
parameter FDET_LCK_SEL = 3'b001;
parameter IREFBIASMODE = 2'b11;
parameter LOOPCAL_WAIT = 2'b00;
parameter MCOMMA_32B_VALUE = 32'h00000000;
parameter MCOMMA_DETECT = "TRUE";
parameter OPPOSITE_SELECT = "FALSE";
parameter PCOMMA_32B_VALUE = 32'h00000000;
parameter PCOMMA_DETECT = "TRUE";
parameter PCS_BIT_SLIP = "FALSE";
parameter PMACLKENABLE = "TRUE";
parameter PMACOREPWRENABLE = "TRUE";
parameter PMAIREFTRIM = 4'b0111;
parameter PMAVBGCTRL = 5'b00000;
parameter PMAVREFTRIM = 4'b0111;
parameter PMA_BIT_SLIP = "FALSE";
parameter POWER_ENABLE = "TRUE";
parameter REPEATER = "FALSE";
parameter RXACTST = "FALSE";
parameter RXAFEEQ = 9'b000000000;
parameter RXAFEPD = "FALSE";
parameter RXAFETST = "FALSE";
parameter RXAPD = "FALSE";
parameter RXAREGCTRL = 5'b00000;
parameter RXASYNCDIVIDE = 2'b11;
parameter RXBY_32 = "FALSE";
parameter RXCDRLOS = 6'b000000;
parameter RXCLK0_FORCE_PMACLK = "FALSE";
parameter RXCLKMODE = 6'b110001;
parameter RXCLMODE = 2'b00;
parameter RXCMADJ = 2'b01;
parameter RXCPSEL = "TRUE";
parameter RXCPTST = "FALSE";
parameter RXCRCCLOCKDOUBLE = "FALSE";
parameter RXCRCENABLE = "FALSE";
parameter RXCRCINITVAL = 32'h00000000;
parameter RXCRCINVERTGEN = "FALSE";
parameter RXCRCSAMECLOCK = "FALSE";
parameter RXCTRL1 = 10'h200;
parameter RXCYCLE_LIMIT_SEL = 2'b00;
parameter RXDATA_SEL = 2'b00;
parameter RXDCCOUPLE = "FALSE";
parameter RXDIGRESET = "FALSE";
parameter RXDIGRX = "FALSE";
parameter RXEQ = 64'h4000000000000000;
parameter RXFDCAL_CLOCK_DIVIDE = "NONE";
parameter RXFDET_HYS_CAL = 3'b010;
parameter RXFDET_HYS_SEL = 3'b100;
parameter RXFDET_LCK_CAL = 3'b100;
parameter RXFDET_LCK_SEL = 3'b001;
parameter RXFECONTROL1 = 2'b00;
parameter RXFECONTROL2 = 3'b000;
parameter RXFETUNE = 2'b01;
parameter RXLB = "FALSE";
parameter RXLKADJ = 5'b00000;
parameter RXLKAPD = "FALSE";
parameter RXLOOPCAL_WAIT = 2'b00;
parameter RXLOOPFILT = 4'b0111;
parameter RXMODE = 6'b000000;
parameter RXPD = "FALSE";
parameter RXPDDTST = "TRUE";
parameter RXPMACLKSEL = "REFCLK1";
parameter RXRCPADJ = 3'b011;
parameter RXRCPPD = "FALSE";
parameter RXRECCLK1_USE_SYNC = "FALSE";
parameter RXRIBADJ = 2'b11;
parameter RXRPDPD = "FALSE";
parameter RXRSDPD = "FALSE";
parameter RXSLOWDOWN_CAL = 2'b00;
parameter RXTUNE = 13'h0000;
parameter RXVCODAC_INIT = 10'b1010000000;
parameter RXVCO_CTRL_ENABLE = "FALSE";
parameter RX_BUFFER_USE = "TRUE";
parameter RX_CLOCK_DIVIDER = 2'b00;
parameter SAMPLE_8X = "FALSE";
parameter SLOWDOWN_CAL = 2'b00;
parameter TXABPMACLKSEL = "REFCLK1";
parameter TXAPD = "FALSE";
parameter TXAREFBIASSEL = "TRUE";
parameter TXASYNCDIVIDE = 2'b11;
parameter TXCLK0_FORCE_PMACLK = "FALSE";
parameter TXCLKMODE = 4'b1001;
parameter TXCLMODE = 2'b00;
parameter TXCPSEL = "TRUE";
parameter TXCRCCLOCKDOUBLE = "FALSE";
parameter TXCRCENABLE = "FALSE";
parameter TXCRCINITVAL = 32'h00000000;
parameter TXCRCINVERTGEN = "FALSE";
parameter TXCRCSAMECLOCK = "FALSE";
parameter TXCTRL1 = 10'h200;
parameter TXDATA_SEL = 2'b00;
parameter TXDAT_PRDRV_DAC = 3'b111;
parameter TXDAT_TAP_DAC = 5'b10110;
parameter TXDIGPD = "FALSE";
parameter TXFDCAL_CLOCK_DIVIDE = "NONE";
parameter TXHIGHSIGNALEN = "TRUE";
parameter TXLOOPFILT = 4'b0111;
parameter TXLVLSHFTPD = "FALSE";
parameter TXOUTCLK1_USE_SYNC = "FALSE";
parameter TXPD = "FALSE";
parameter TXPHASESEL = "FALSE";
parameter TXPOST_PRDRV_DAC = 3'b111;
parameter TXPOST_TAP_DAC = 5'b01110;
parameter TXPOST_TAP_PD = "TRUE";
parameter TXPRE_PRDRV_DAC = 3'b111;
parameter TXPRE_TAP_DAC = 5'b00000;
parameter TXPRE_TAP_PD = "TRUE";
parameter TXSLEWRATE = "FALSE";
parameter TXTERMTRIM = 4'b1100;
parameter TXTUNE = 13'h0000;
parameter TX_BUFFER_USE = "TRUE";
parameter TX_CLOCK_DIVIDER = 2'b00;
parameter VCODAC_INIT = 10'b1010000000;
parameter VCO_CTRL_ENABLE = "FALSE";
parameter VREFBIASMODE = 2'b11;
parameter integer ALIGN_COMMA_WORD = 4;
parameter integer CHAN_BOND_LIMIT = 16;
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter integer CLK_COR_MAX_LAT = 48;
parameter integer CLK_COR_MIN_LAT = 36;
parameter integer CLK_COR_SEQ_LEN = 1;
parameter integer RXOUTDIV2SEL = 1;
parameter integer RXPLLNDIVSEL = 8;
parameter integer RXUSRDIVISOR = 1;
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter integer TXOUTDIV2SEL = 1;
parameter integer TXPLLNDIVSEL = 8;
output [4:0] CHBONDO;
output [15:0] DO;
output DRDY;
output RXBUFERR;
output RXCALFAIL;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output RXCOMMADET;
output [31:0] RXCRCOUT;
output RXCYCLELIMIT;
output [63:0] RXDATA;
output [7:0] RXDISPERR;
output RXLOCK;
output [1:0] RXLOSSOFSYNC;
output RXMCLK;
output [7:0] RXNOTINTABLE;
output RXPCSHCLKOUT;
output RXREALIGN;
output RXRECCLK1;
output RXRECCLK2;
output [7:0] RXRUNDISP;
output RXSIGDET;
output [5:0] RXSTATUS;
output TX1N;
output TX1P;
output TXBUFERR;
output TXCALFAIL;
output [31:0] TXCRCOUT;
output TXCYCLELIMIT;
output [7:0] TXKERR;
output TXLOCK;
output TXOUTCLK1;
output TXOUTCLK2;
output TXPCSHCLKOUT;
output [7:0] TXRUNDISP;
input [4:0] CHBONDI;
input [7:0] DADDR;
input DCLK;
input DEN;
input [15:0] DI;
input DWE;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input GREFCLK;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK1;
input REFCLK2;
input RX1N;
input RX1P;
input RXBLOCKSYNC64B66BUSE;
input RXCLKSTABLE;
input RXCOMMADETUSE;
input RXCRCCLK;
input RXCRCDATAVALID;
input [2:0] RXCRCDATAWIDTH;
input [63:0] RXCRCIN;
input RXCRCINIT;
input RXCRCINTCLK;
input RXCRCPD;
input RXCRCRESET;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXPMARESET;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXSYNC;
input RXUSRCLK;
input RXUSRCLK2;
input [7:0] TXBYPASS8B10B;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input TXCLKSTABLE;
input TXCRCCLK;
input TXCRCDATAVALID;
input [2:0] TXCRCDATAWIDTH;
input [63:0] TXCRCIN;
input TXCRCINIT;
input TXCRCINTCLK;
input TXCRCPD;
input TXCRCRESET;
input [63:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXENOOB;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPMARESET;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXSYNC;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT11_DUAL (CHBONDOA, CHBONDOB, DOA, DOB, DRDYA, DRDYB, RXBUFERRA, RXBUFERRB, RXCALFAILA, RXCALFAILB, RXCHARISCOMMAA, RXCHARISCOMMAB, RXCHARISKA, RXCHARISKB, RXCOMMADETA, RXCOMMADETB, RXCRCOUTA, RXCRCOUTB, RXCYCLELIMITA, RXCYCLELIMITB, RXDATAA, RXDATAB, RXDISPERRA, RXDISPERRB, RXLOCKA, RXLOCKB, RXLOSSOFSYNCA, RXLOSSOFSYNCB, RXMCLKA, RXMCLKB, RXNOTINTABLEA, RXNOTINTABLEB, RXPCSHCLKOUTA, RXPCSHCLKOUTB, RXREALIGNA, RXREALIGNB, RXRECCLK1A, RXRECCLK1B, RXRECCLK2A, RXRECCLK2B, RXRUNDISPA, RXRUNDISPB, RXSIGDETA, RXSIGDETB, RXSTATUSA, RXSTATUSB, TX1NA, TX1NB, TX1PA, TX1PB, TXBUFERRA, TXBUFERRB, TXCALFAILA, TXCALFAILB, TXCRCOUTA, TXCRCOUTB, TXCYCLELIMITA, TXCYCLELIMITB, TXKERRA, TXKERRB, TXLOCKA, TXLOCKB, TXOUTCLK1A, TXOUTCLK1B, TXOUTCLK2A, TXOUTCLK2B, TXPCSHCLKOUTA, TXPCSHCLKOUTB, TXRUNDISPA, TXRUNDISPB, CHBONDIA, CHBONDIB, DADDRA, DADDRB, DCLKA, DCLKB, DENA, DENB, DIA, DIB, DWEA, DWEB, ENCHANSYNCA, ENCHANSYNCB, ENMCOMMAALIGNA, ENMCOMMAALIGNB, ENPCOMMAALIGNA, ENPCOMMAALIGNB, GREFCLKA, GREFCLKB, LOOPBACKA, LOOPBACKB, POWERDOWNA, POWERDOWNB, REFCLK1A, REFCLK1B, REFCLK2A, REFCLK2B, RX1NA, RX1NB, RX1PA, RX1PB, RXBLOCKSYNC64B66BUSEA, RXBLOCKSYNC64B66BUSEB, RXCLKSTABLEA, RXCLKSTABLEB, RXCOMMADETUSEA, RXCOMMADETUSEB, RXCRCCLKA, RXCRCCLKB, RXCRCDATAVALIDA, RXCRCDATAVALIDB, RXCRCDATAWIDTHA, RXCRCDATAWIDTHB, RXCRCINA, RXCRCINB, RXCRCINITA, RXCRCINITB, RXCRCINTCLKA, RXCRCINTCLKB, RXCRCPDA, RXCRCPDB, RXCRCRESETA, RXCRCRESETB, RXDATAWIDTHA, RXDATAWIDTHB, RXDEC64B66BUSEA, RXDEC64B66BUSEB, RXDEC8B10BUSEA, RXDEC8B10BUSEB, RXDESCRAM64B66BUSEA, RXDESCRAM64B66BUSEB, RXIGNOREBTFA, RXIGNOREBTFB, RXINTDATAWIDTHA, RXINTDATAWIDTHB, RXPMARESETA, RXPMARESETB, RXPOLARITYA, RXPOLARITYB, RXRESETA, RXRESETB, RXSLIDEA, RXSLIDEB, RXSYNCA, RXSYNCB, RXUSRCLK2A, RXUSRCLK2B, RXUSRCLKA, RXUSRCLKB, TXBYPASS8B10BA, TXBYPASS8B10BB, TXCHARDISPMODEA, TXCHARDISPMODEB, TXCHARDISPVALA, TXCHARDISPVALB, TXCHARISKA, TXCHARISKB, TXCLKSTABLEA, TXCLKSTABLEB, TXCRCCLKA, TXCRCCLKB, TXCRCDATAVALIDA, TXCRCDATAVALIDB, TXCRCDATAWIDTHA, TXCRCDATAWIDTHB, TXCRCINA, TXCRCINB, TXCRCINITA, TXCRCINITB, TXCRCINTCLKA, TXCRCINTCLKB, TXCRCPDA, TXCRCPDB, TXCRCRESETA, TXCRCRESETB, TXDATAA, TXDATAB, TXDATAWIDTHA, TXDATAWIDTHB, TXENC64B66BUSEA, TXENC64B66BUSEB, TXENC8B10BUSEA, TXENC8B10BUSEB, TXENOOBA, TXENOOBB, TXGEARBOX64B66BUSEA, TXGEARBOX64B66BUSEB, TXINHIBITA, TXINHIBITB, TXINTDATAWIDTHA, TXINTDATAWIDTHB, TXPMARESETA, TXPMARESETB, TXPOLARITYA, TXPOLARITYB, TXRESETA, TXRESETB, TXSCRAM64B66BUSEA, TXSCRAM64B66BUSEB, TXSYNCA, TXSYNCB, TXUSRCLK2A, TXUSRCLK2B, TXUSRCLKA, TXUSRCLKB);
parameter BANDGAPSEL_A = "FALSE";
parameter BANDGAPSEL_B = "FALSE";
parameter BIASRESSEL_A = "FALSE";
parameter BIASRESSEL_B = "FALSE";
parameter CCCB_ARBITRATOR_DISABLE_A = "FALSE";
parameter CCCB_ARBITRATOR_DISABLE_B = "FALSE";
parameter CHAN_BOND_MODE_A = "NONE";
parameter CHAN_BOND_MODE_B = "NONE";
parameter CHAN_BOND_ONE_SHOT_A = "FALSE";
parameter CHAN_BOND_ONE_SHOT_B = "FALSE";
parameter CHAN_BOND_SEQ_1_1_A = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_1_B = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_2_A = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_2_B = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_3_A = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_3_B = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_4_A = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_4_B = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_MASK_A = 4'b1110;
parameter CHAN_BOND_SEQ_1_MASK_B = 4'b1110;
parameter CHAN_BOND_SEQ_2_1_A = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_1_B = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_2_A = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_2_B = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_3_A = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_3_B = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_4_A = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_4_B = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_MASK_A = 4'b1110;
parameter CHAN_BOND_SEQ_2_MASK_B = 4'b1110;
parameter CHAN_BOND_SEQ_2_USE_A = "FALSE";
parameter CHAN_BOND_SEQ_2_USE_B = "FALSE";
parameter CLK_CORRECT_USE_A = "FALSE";
parameter CLK_CORRECT_USE_B = "FALSE";
parameter CLK_COR_8B10B_DE_A = "FALSE";
parameter CLK_COR_8B10B_DE_B = "FALSE";
parameter CLK_COR_SEQ_1_1_A = 11'b00000000000;
parameter CLK_COR_SEQ_1_1_B = 11'b00000000000;
parameter CLK_COR_SEQ_1_2_A = 11'b00000000000;
parameter CLK_COR_SEQ_1_2_B = 11'b00000000000;
parameter CLK_COR_SEQ_1_3_A = 11'b00000000000;
parameter CLK_COR_SEQ_1_3_B = 11'b00000000000;
parameter CLK_COR_SEQ_1_4_A = 11'b00000000000;
parameter CLK_COR_SEQ_1_4_B = 11'b00000000000;
parameter CLK_COR_SEQ_1_MASK_A = 4'b1110;
parameter CLK_COR_SEQ_1_MASK_B = 4'b1110;
parameter CLK_COR_SEQ_2_1_A = 11'b00000000000;
parameter CLK_COR_SEQ_2_1_B = 11'b00000000000;
parameter CLK_COR_SEQ_2_2_A = 11'b00000000000;
parameter CLK_COR_SEQ_2_2_B = 11'b00000000000;
parameter CLK_COR_SEQ_2_3_A = 11'b00000000000;
parameter CLK_COR_SEQ_2_3_B = 11'b00000000000;
parameter CLK_COR_SEQ_2_4_A = 11'b00000000000;
parameter CLK_COR_SEQ_2_4_B = 11'b00000000000;
parameter CLK_COR_SEQ_2_MASK_A = 4'b1110;
parameter CLK_COR_SEQ_2_MASK_B = 4'b1110;
parameter CLK_COR_SEQ_2_USE_A = "FALSE";
parameter CLK_COR_SEQ_2_USE_B = "FALSE";
parameter CLK_COR_SEQ_DROP_A = "FALSE";
parameter CLK_COR_SEQ_DROP_B = "FALSE";
parameter COMMA32_A = "FALSE";
parameter COMMA32_B = "FALSE";
parameter COMMA_10B_MASK_A = 10'h3FF;
parameter COMMA_10B_MASK_B = 10'h3FF;
parameter CYCLE_LIMIT_SEL_A = 2'b00;
parameter CYCLE_LIMIT_SEL_B = 2'b00;
parameter DCDR_FILTER_A = 3'b010;
parameter DCDR_FILTER_B = 3'b010;
parameter DEC_MCOMMA_DETECT_A = "TRUE";
parameter DEC_MCOMMA_DETECT_B = "TRUE";
parameter DEC_PCOMMA_DETECT_A = "TRUE";
parameter DEC_PCOMMA_DETECT_B = "TRUE";
parameter DEC_VALID_COMMA_ONLY_A = "TRUE";
parameter DEC_VALID_COMMA_ONLY_B = "TRUE";
parameter DIGRX_FWDCLK_A = 2'b00;
parameter DIGRX_FWDCLK_B = 2'b00;
parameter DIGRX_SYNC_MODE_A = "FALSE";
parameter DIGRX_SYNC_MODE_B = "FALSE";
parameter ENABLE_DCDR_A = "FALSE";
parameter ENABLE_DCDR_B = "FALSE";
parameter FDET_HYS_CAL_A = 3'b010;
parameter FDET_HYS_CAL_B = 3'b010;
parameter FDET_HYS_SEL_A = 3'b100;
parameter FDET_HYS_SEL_B = 3'b100;
parameter FDET_LCK_CAL_A = 3'b100;
parameter FDET_LCK_CAL_B = 3'b100;
parameter FDET_LCK_SEL_A = 3'b001;
parameter FDET_LCK_SEL_B = 3'b001;
parameter IREFBIASMODE_A = 2'b11;
parameter IREFBIASMODE_B = 2'b11;
parameter LOOPCAL_WAIT_A = 2'b00;
parameter LOOPCAL_WAIT_B = 2'b00;
parameter MCOMMA_32B_VALUE_A = 32'h00000000;
parameter MCOMMA_32B_VALUE_B = 32'h00000000;
parameter MCOMMA_DETECT_A = "TRUE";
parameter MCOMMA_DETECT_B = "TRUE";
parameter OPPOSITE_SELECT_A = "FALSE";
parameter OPPOSITE_SELECT_B = "FALSE";
parameter PCOMMA_32B_VALUE_A = 32'h00000000;
parameter PCOMMA_32B_VALUE_B = 32'h00000000;
parameter PCOMMA_DETECT_A = "TRUE";
parameter PCOMMA_DETECT_B = "TRUE";
parameter PCS_BIT_SLIP_A = "FALSE";
parameter PCS_BIT_SLIP_B = "FALSE";
parameter PMACLKENABLE_A = "TRUE";
parameter PMACLKENABLE_B = "TRUE";
parameter PMACOREPWRENABLE_A = "TRUE";
parameter PMACOREPWRENABLE_B = "TRUE";
parameter PMAIREFTRIM_A = 4'b0111;
parameter PMAIREFTRIM_B = 4'b0111;
parameter PMAVBGCTRL_A = 5'b00000;
parameter PMAVBGCTRL_B = 5'b00000;
parameter PMAVREFTRIM_A = 4'b0111;
parameter PMAVREFTRIM_B = 4'b0111;
parameter PMA_BIT_SLIP_A = "FALSE";
parameter PMA_BIT_SLIP_B = "FALSE";
parameter POWER_ENABLE_A = "TRUE";
parameter POWER_ENABLE_B = "TRUE";
parameter REPEATER_A = "FALSE";
parameter REPEATER_B = "FALSE";
parameter RXACTST_A = "FALSE";
parameter RXACTST_B = "FALSE";
parameter RXAFEEQ_A = 9'b000000000;
parameter RXAFEEQ_B = 9'b000000000;
parameter RXAFEPD_A = "FALSE";
parameter RXAFEPD_B = "FALSE";
parameter RXAFETST_A = "FALSE";
parameter RXAFETST_B = "FALSE";
parameter RXAPD_A = "FALSE";
parameter RXAPD_B = "FALSE";
parameter RXAREGCTRL_A = 5'b00000;
parameter RXAREGCTRL_B = 5'b00000;
parameter RXASYNCDIVIDE_A = 2'b11;
parameter RXASYNCDIVIDE_B = 2'b11;
parameter RXBY_32_A = "FALSE";
parameter RXBY_32_B = "FALSE";
parameter RXCDRLOS_A = 6'b000000;
parameter RXCDRLOS_B = 6'b000000;
parameter RXCLK0_FORCE_PMACLK_A = "FALSE";
parameter RXCLK0_FORCE_PMACLK_B = "FALSE";
parameter RXCLKMODE_A = 6'b110001;
parameter RXCLKMODE_B = 6'b110001;
parameter RXCLMODE_A = 2'b00;
parameter RXCLMODE_B = 2'b00;
parameter RXCMADJ_A = 2'b01;
parameter RXCMADJ_B = 2'b01;
parameter RXCPSEL_A = "TRUE";
parameter RXCPSEL_B = "TRUE";
parameter RXCPTST_A = "FALSE";
parameter RXCPTST_B = "FALSE";
parameter RXCRCCLOCKDOUBLE_A = "FALSE";
parameter RXCRCCLOCKDOUBLE_B = "FALSE";
parameter RXCRCENABLE_A = "FALSE";
parameter RXCRCENABLE_B = "FALSE";
parameter RXCRCINITVAL_A = 32'h00000000;
parameter RXCRCINITVAL_B = 32'h00000000;
parameter RXCRCINVERTGEN_A = "FALSE";
parameter RXCRCINVERTGEN_B = "FALSE";
parameter RXCRCSAMECLOCK_A = "FALSE";
parameter RXCRCSAMECLOCK_B = "FALSE";
parameter RXCTRL1_A = 10'h200;
parameter RXCTRL1_B = 10'h200;
parameter RXCYCLE_LIMIT_SEL_A = 2'b00;
parameter RXCYCLE_LIMIT_SEL_B = 2'b00;
parameter RXDATA_SEL_A = 2'b00;
parameter RXDATA_SEL_B = 2'b00;
parameter RXDCCOUPLE_A = "FALSE";
parameter RXDCCOUPLE_B = "FALSE";
parameter RXDIGRESET_A = "FALSE";
parameter RXDIGRESET_B = "FALSE";
parameter RXDIGRX_A = "FALSE";
parameter RXDIGRX_B = "FALSE";
parameter RXEQ_A = 64'h4000000000000000;
parameter RXEQ_B = 64'h4000000000000000;
parameter RXFDCAL_CLOCK_DIVIDE_A = "NONE";
parameter RXFDCAL_CLOCK_DIVIDE_B = "NONE";
parameter RXFDET_HYS_CAL_A = 3'b010;
parameter RXFDET_HYS_CAL_B = 3'b010;
parameter RXFDET_HYS_SEL_A = 3'b100;
parameter RXFDET_HYS_SEL_B = 3'b100;
parameter RXFDET_LCK_CAL_A = 3'b100;
parameter RXFDET_LCK_CAL_B = 3'b100;
parameter RXFDET_LCK_SEL_A = 3'b001;
parameter RXFDET_LCK_SEL_B = 3'b001;
parameter RXFECONTROL1_A = 2'b00;
parameter RXFECONTROL1_B = 2'b00;
parameter RXFECONTROL2_A = 3'b000;
parameter RXFECONTROL2_B = 3'b000;
parameter RXFETUNE_A = 2'b01;
parameter RXFETUNE_B = 2'b01;
parameter RXLB_A = "FALSE";
parameter RXLB_B = "FALSE";
parameter RXLKADJ_A = 5'b00000;
parameter RXLKADJ_B = 5'b00000;
parameter RXLKAPD_A = "FALSE";
parameter RXLKAPD_B = "FALSE";
parameter RXLOOPCAL_WAIT_A = 2'b00;
parameter RXLOOPCAL_WAIT_B = 2'b00;
parameter RXLOOPFILT_A = 4'b0111;
parameter RXLOOPFILT_B = 4'b0111;
parameter RXMODE_A = 6'b000000;
parameter RXMODE_B = 6'b000000;
parameter RXPDDTST_A = "TRUE";
parameter RXPDDTST_B = "TRUE";
parameter RXPD_A = "FALSE";
parameter RXPD_B = "FALSE";
parameter RXPMACLKSEL_A = "REFCLK1";
parameter RXPMACLKSEL_B = "REFCLK1";
parameter RXRCPADJ_A = 3'b011;
parameter RXRCPADJ_B = 3'b011;
parameter RXRCPPD_A = "FALSE";
parameter RXRCPPD_B = "FALSE";
parameter RXRECCLK1_USE_SYNC_A = "FALSE";
parameter RXRECCLK1_USE_SYNC_B = "FALSE";
parameter RXRIBADJ_A = 2'b11;
parameter RXRIBADJ_B = 2'b11;
parameter RXRPDPD_A = "FALSE";
parameter RXRPDPD_B = "FALSE";
parameter RXRSDPD_A = "FALSE";
parameter RXRSDPD_B = "FALSE";
parameter RXSLOWDOWN_CAL_A = 2'b00;
parameter RXSLOWDOWN_CAL_B = 2'b00;
parameter RXTUNE_A = 13'h0000;
parameter RXTUNE_B = 13'h0000;
parameter RXVCODAC_INIT_A = 10'b1010000000;
parameter RXVCODAC_INIT_B = 10'b1010000000;
parameter RXVCO_CTRL_ENABLE_A = "FALSE";
parameter RXVCO_CTRL_ENABLE_B = "FALSE";
parameter RX_BUFFER_USE_A = "TRUE";
parameter RX_BUFFER_USE_B = "TRUE";
parameter RX_CLOCK_DIVIDER_A = 2'b00;
parameter RX_CLOCK_DIVIDER_B = 2'b00;
parameter SAMPLE_8X_A = "FALSE";
parameter SAMPLE_8X_B = "FALSE";
parameter SLOWDOWN_CAL_A = 2'b00;
parameter SLOWDOWN_CAL_B = 2'b00;
parameter TXABPMACLKSEL_A = "REFCLK1";
parameter TXABPMACLKSEL_B = "REFCLK1";
parameter TXAPD_A = "FALSE";
parameter TXAPD_B = "FALSE";
parameter TXAREFBIASSEL_A = "TRUE";
parameter TXAREFBIASSEL_B = "TRUE";
parameter TXASYNCDIVIDE_A = 2'b11;
parameter TXASYNCDIVIDE_B = 2'b11;
parameter TXCLK0_FORCE_PMACLK_A = "FALSE";
parameter TXCLK0_FORCE_PMACLK_B = "FALSE";
parameter TXCLKMODE_A = 4'b1001;
parameter TXCLKMODE_B = 4'b1001;
parameter TXCLMODE_A = 2'b00;
parameter TXCLMODE_B = 2'b00;
parameter TXCPSEL_A = "TRUE";
parameter TXCPSEL_B = "TRUE";
parameter TXCRCCLOCKDOUBLE_A = "FALSE";
parameter TXCRCCLOCKDOUBLE_B = "FALSE";
parameter TXCRCENABLE_A = "FALSE";
parameter TXCRCENABLE_B = "FALSE";
parameter TXCRCINITVAL_A = 32'h00000000;
parameter TXCRCINITVAL_B = 32'h00000000;
parameter TXCRCINVERTGEN_A = "FALSE";
parameter TXCRCINVERTGEN_B = "FALSE";
parameter TXCRCSAMECLOCK_A = "FALSE";
parameter TXCRCSAMECLOCK_B = "FALSE";
parameter TXCTRL1_A = 10'h200;
parameter TXCTRL1_B = 10'h200;
parameter TXDATA_SEL_A = 2'b00;
parameter TXDATA_SEL_B = 2'b00;
parameter TXDAT_PRDRV_DAC_A = 3'b111;
parameter TXDAT_PRDRV_DAC_B = 3'b111;
parameter TXDAT_TAP_DAC_A = 5'b10110;
parameter TXDAT_TAP_DAC_B = 5'b10110;
parameter TXDIGPD_A = "FALSE";
parameter TXDIGPD_B = "FALSE";
parameter TXFDCAL_CLOCK_DIVIDE_A = "NONE";
parameter TXFDCAL_CLOCK_DIVIDE_B = "NONE";
parameter TXHIGHSIGNALEN_A = "TRUE";
parameter TXHIGHSIGNALEN_B = "TRUE";
parameter TXLOOPFILT_A = 4'b0111;
parameter TXLOOPFILT_B = 4'b0111;
parameter TXLVLSHFTPD_A = "FALSE";
parameter TXLVLSHFTPD_B = "FALSE";
parameter TXOUTCLK1_USE_SYNC_A = "FALSE";
parameter TXOUTCLK1_USE_SYNC_B = "FALSE";
parameter TXPD_A = "FALSE";
parameter TXPD_B = "FALSE";
parameter TXPHASESEL_A = "FALSE";
parameter TXPHASESEL_B = "FALSE";
parameter TXPOST_PRDRV_DAC_A = 3'b111;
parameter TXPOST_PRDRV_DAC_B = 3'b111;
parameter TXPOST_TAP_DAC_A = 5'b01110;
parameter TXPOST_TAP_DAC_B = 5'b01110;
parameter TXPOST_TAP_PD_A = "TRUE";
parameter TXPOST_TAP_PD_B = "TRUE";
parameter TXPRE_PRDRV_DAC_A = 3'b111;
parameter TXPRE_PRDRV_DAC_B = 3'b111;
parameter TXPRE_TAP_DAC_A = 5'b00000;
parameter TXPRE_TAP_DAC_B = 5'b00000;
parameter TXPRE_TAP_PD_A = "TRUE";
parameter TXPRE_TAP_PD_B = "TRUE";
parameter TXSLEWRATE_A = "FALSE";
parameter TXSLEWRATE_B = "FALSE";
parameter TXTERMTRIM_A = 4'b1100;
parameter TXTERMTRIM_B = 4'b1100;
parameter TXTUNE_A = 13'h0000;
parameter TXTUNE_B = 13'h0000;
parameter TX_BUFFER_USE_A = "TRUE";
parameter TX_BUFFER_USE_B = "TRUE";
parameter TX_CLOCK_DIVIDER_A = 2'b00;
parameter TX_CLOCK_DIVIDER_B = 2'b00;
parameter VCODAC_INIT_A = 10'b1010000000;
parameter VCODAC_INIT_B = 10'b1010000000;
parameter VCO_CTRL_ENABLE_A = "FALSE";
parameter VCO_CTRL_ENABLE_B = "FALSE";
parameter VREFBIASMODE_A = 2'b11;
parameter VREFBIASMODE_B = 2'b11;
parameter integer ALIGN_COMMA_WORD_A = 4;
parameter integer ALIGN_COMMA_WORD_B = 4;
parameter integer CHAN_BOND_LIMIT_A = 16;
parameter integer CHAN_BOND_LIMIT_B = 16;
parameter integer CHAN_BOND_SEQ_LEN_A = 1;
parameter integer CHAN_BOND_SEQ_LEN_B = 1;
parameter integer CLK_COR_MAX_LAT_A = 48;
parameter integer CLK_COR_MAX_LAT_B = 48;
parameter integer CLK_COR_MIN_LAT_A = 36;
parameter integer CLK_COR_MIN_LAT_B = 36;
parameter integer CLK_COR_SEQ_LEN_A = 1;
parameter integer CLK_COR_SEQ_LEN_B = 1;
parameter integer RXOUTDIV2SEL_A = 1;
parameter integer RXOUTDIV2SEL_B = 1;
parameter integer RXPLLNDIVSEL_A = 8;
parameter integer RXPLLNDIVSEL_B = 8;
parameter integer RXUSRDIVISOR_A = 1;
parameter integer RXUSRDIVISOR_B = 1;
parameter integer SH_CNT_MAX_A = 64;
parameter integer SH_CNT_MAX_B = 64;
parameter integer SH_INVALID_CNT_MAX_A = 16;
parameter integer SH_INVALID_CNT_MAX_B = 16;
parameter integer TXOUTDIV2SEL_A = 1;
parameter integer TXOUTDIV2SEL_B = 1;
parameter integer TXPLLNDIVSEL_A = 8;
parameter integer TXPLLNDIVSEL_B = 8;
output [4:0] CHBONDOA;
output [4:0] CHBONDOB;
output [15:0] DOA;
output [15:0] DOB;
output DRDYA;
output DRDYB;
output RXBUFERRA;
output RXBUFERRB;
output RXCALFAILA;
output RXCALFAILB;
output [7:0] RXCHARISCOMMAA;
output [7:0] RXCHARISCOMMAB;
output [7:0] RXCHARISKA;
output [7:0] RXCHARISKB;
output RXCOMMADETA;
output RXCOMMADETB;
output [31:0] RXCRCOUTA;
output [31:0] RXCRCOUTB;
output RXCYCLELIMITA;
output RXCYCLELIMITB;
output [63:0] RXDATAA;
output [63:0] RXDATAB;
output [7:0] RXDISPERRA;
output [7:0] RXDISPERRB;
output RXLOCKA;
output RXLOCKB;
output [1:0] RXLOSSOFSYNCA;
output [1:0] RXLOSSOFSYNCB;
output RXMCLKA;
output RXMCLKB;
output [7:0] RXNOTINTABLEA;
output [7:0] RXNOTINTABLEB;
output RXPCSHCLKOUTA;
output RXPCSHCLKOUTB;
output RXREALIGNA;
output RXREALIGNB;
output RXRECCLK1A;
output RXRECCLK1B;
output RXRECCLK2A;
output RXRECCLK2B;
output [7:0] RXRUNDISPA;
output [7:0] RXRUNDISPB;
output RXSIGDETA;
output RXSIGDETB;
output [5:0] RXSTATUSA;
output [5:0] RXSTATUSB;
output TX1NA;
output TX1NB;
output TX1PA;
output TX1PB;
output TXBUFERRA;
output TXBUFERRB;
output TXCALFAILA;
output TXCALFAILB;
output [31:0] TXCRCOUTA;
output [31:0] TXCRCOUTB;
output TXCYCLELIMITA;
output TXCYCLELIMITB;
output [7:0] TXKERRA;
output [7:0] TXKERRB;
output TXLOCKA;
output TXLOCKB;
output TXOUTCLK1A;
output TXOUTCLK1B;
output TXOUTCLK2A;
output TXOUTCLK2B;
output TXPCSHCLKOUTA;
output TXPCSHCLKOUTB;
output [7:0] TXRUNDISPA;
output [7:0] TXRUNDISPB;
input [4:0] CHBONDIA;
input [4:0] CHBONDIB;
input [7:0] DADDRA;
input [7:0] DADDRB;
input DCLKA;
input DCLKB;
input DENA;
input DENB;
input [15:0] DIA;
input [15:0] DIB;
input DWEA;
input DWEB;
input ENCHANSYNCA;
input ENCHANSYNCB;
input ENMCOMMAALIGNA;
input ENMCOMMAALIGNB;
input ENPCOMMAALIGNA;
input ENPCOMMAALIGNB;
input GREFCLKA;
input GREFCLKB;
input [1:0] LOOPBACKA;
input [1:0] LOOPBACKB;
input POWERDOWNA;
input POWERDOWNB;
input REFCLK1A;
input REFCLK1B;
input REFCLK2A;
input REFCLK2B;
input RX1NA;
input RX1NB;
input RX1PA;
input RX1PB;
input RXBLOCKSYNC64B66BUSEA;
input RXBLOCKSYNC64B66BUSEB;
input RXCLKSTABLEA;
input RXCLKSTABLEB;
input RXCOMMADETUSEA;
input RXCOMMADETUSEB;
input RXCRCCLKA;
input RXCRCCLKB;
input RXCRCDATAVALIDA;
input RXCRCDATAVALIDB;
input [2:0] RXCRCDATAWIDTHA;
input [2:0] RXCRCDATAWIDTHB;
input [63:0] RXCRCINA;
input [63:0] RXCRCINB;
input RXCRCINITA;
input RXCRCINITB;
input RXCRCINTCLKA;
input RXCRCINTCLKB;
input RXCRCPDA;
input RXCRCPDB;
input RXCRCRESETA;
input RXCRCRESETB;
input [1:0] RXDATAWIDTHA;
input [1:0] RXDATAWIDTHB;
input RXDEC64B66BUSEA;
input RXDEC64B66BUSEB;
input RXDEC8B10BUSEA;
input RXDEC8B10BUSEB;
input RXDESCRAM64B66BUSEA;
input RXDESCRAM64B66BUSEB;
input RXIGNOREBTFA;
input RXIGNOREBTFB;
input [1:0] RXINTDATAWIDTHA;
input [1:0] RXINTDATAWIDTHB;
input RXPMARESETA;
input RXPMARESETB;
input RXPOLARITYA;
input RXPOLARITYB;
input RXRESETA;
input RXRESETB;
input RXSLIDEA;
input RXSLIDEB;
input RXSYNCA;
input RXSYNCB;
input RXUSRCLK2A;
input RXUSRCLK2B;
input RXUSRCLKA;
input RXUSRCLKB;
input [7:0] TXBYPASS8B10BA;
input [7:0] TXBYPASS8B10BB;
input [7:0] TXCHARDISPMODEA;
input [7:0] TXCHARDISPMODEB;
input [7:0] TXCHARDISPVALA;
input [7:0] TXCHARDISPVALB;
input [7:0] TXCHARISKA;
input [7:0] TXCHARISKB;
input TXCLKSTABLEA;
input TXCLKSTABLEB;
input TXCRCCLKA;
input TXCRCCLKB;
input TXCRCDATAVALIDA;
input TXCRCDATAVALIDB;
input [2:0] TXCRCDATAWIDTHA;
input [2:0] TXCRCDATAWIDTHB;
input [63:0] TXCRCINA;
input [63:0] TXCRCINB;
input TXCRCINITA;
input TXCRCINITB;
input TXCRCINTCLKA;
input TXCRCINTCLKB;
input TXCRCPDA;
input TXCRCPDB;
input TXCRCRESETA;
input TXCRCRESETB;
input [63:0] TXDATAA;
input [63:0] TXDATAB;
input [1:0] TXDATAWIDTHA;
input [1:0] TXDATAWIDTHB;
input TXENC64B66BUSEA;
input TXENC64B66BUSEB;
input TXENC8B10BUSEA;
input TXENC8B10BUSEB;
input TXENOOBA;
input TXENOOBB;
input TXGEARBOX64B66BUSEA;
input TXGEARBOX64B66BUSEB;
input TXINHIBITA;
input TXINHIBITB;
input [1:0] TXINTDATAWIDTHA;
input [1:0] TXINTDATAWIDTHB;
input TXPMARESETA;
input TXPMARESETB;
input TXPOLARITYA;
input TXPOLARITYB;
input TXRESETA;
input TXRESETB;
input TXSCRAM64B66BUSEA;
input TXSCRAM64B66BUSEB;
input TXSYNCA;
input TXSYNCB;
input TXUSRCLK2A;
input TXUSRCLK2B;
input TXUSRCLKA;
input TXUSRCLKB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT11 (CHBONDO, COMBUSOUT, DO, DRDY, RXBUFERR, RXCALFAIL, RXCHARISCOMMA, RXCHARISK, RXCOMMADET, RXCRCOUT, RXCYCLELIMIT, RXDATA, RXDISPERR, RXLOCK, RXLOSSOFSYNC, RXMCLK, RXNOTINTABLE, RXPCSHCLKOUT, RXREALIGN, RXRECCLK1, RXRECCLK2, RXRUNDISP, RXSIGDET, RXSTATUS, TX1N, TX1P, TXBUFERR, TXCALFAIL, TXCRCOUT, TXCYCLELIMIT, TXKERR, TXLOCK, TXOUTCLK1, TXOUTCLK2, TXPCSHCLKOUT, TXRUNDISP, CHBONDI, COMBUSIN, DADDR, DCLK, DEN, DI, DWE, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, GREFCLK, LOOPBACK, POWERDOWN, REFCLK1, REFCLK2, RX1N, RX1P, RXBLOCKSYNC64B66BUSE, RXCLKSTABLE, RXCOMMADETUSE, RXCRCCLK, RXCRCDATAVALID, RXCRCDATAWIDTH, RXCRCIN, RXCRCINIT, RXCRCINTCLK, RXCRCPD, RXCRCRESET, RXDATAWIDTH, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXINTDATAWIDTH, RXPMARESET, RXPOLARITY, RXRESET, RXSLIDE, RXSYNC, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXCLKSTABLE, TXCRCCLK, TXCRCDATAVALID, TXCRCDATAWIDTH, TXCRCIN, TXCRCINIT, TXCRCINTCLK, TXCRCPD, TXCRCRESET, TXDATA, TXDATAWIDTH, TXENC64B66BUSE, TXENC8B10BUSE, TXENOOB, TXGEARBOX64B66BUSE, TXINHIBIT, TXINTDATAWIDTH, TXPMARESET, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXSYNC, TXUSRCLK, TXUSRCLK2);
parameter BANDGAPSEL = "FALSE";
parameter BIASRESSEL = "FALSE";
parameter CCCB_ARBITRATOR_DISABLE = "FALSE";
parameter CHAN_BOND_MODE = "NONE";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_MASK = 4'b1110;
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b1110;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter CLK_CORRECT_USE = "FALSE";
parameter CLK_COR_8B10B_DE = "FALSE";
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
parameter CLK_COR_SEQ_1_MASK = 4'b1110;
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
parameter CLK_COR_SEQ_2_MASK = 4'b1110;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter COMMA32 = "FALSE";
parameter COMMA_10B_MASK = 10'h3FF;
parameter CYCLE_LIMIT_SEL = 2'b00;
parameter DCDR_FILTER = 3'b010;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter DIGRX_FWDCLK = 2'b00;
parameter DIGRX_SYNC_MODE = "FALSE";
parameter ENABLE_DCDR = "FALSE";
parameter FDET_HYS_CAL = 3'b010;
parameter FDET_HYS_SEL = 3'b100;
parameter FDET_LCK_CAL = 3'b100;
parameter FDET_LCK_SEL = 3'b001;
parameter GT11_MODE = "DONT_CARE";
parameter IREFBIASMODE = 2'b11;
parameter LOOPCAL_WAIT = 2'b00;
parameter MCOMMA_32B_VALUE = 32'h00000000;
parameter MCOMMA_DETECT = "TRUE";
parameter OPPOSITE_SELECT = "FALSE";
parameter PCOMMA_32B_VALUE = 32'h00000000;
parameter PCOMMA_DETECT = "TRUE";
parameter PCS_BIT_SLIP = "FALSE";
parameter PMACLKENABLE = "TRUE";
parameter PMACOREPWRENABLE = "TRUE";
parameter PMAIREFTRIM = 4'b0111;
parameter PMAVBGCTRL = 5'b00000;
parameter PMAVREFTRIM = 4'b0111;
parameter PMA_BIT_SLIP = "FALSE";
parameter POWER_ENABLE = "TRUE";
parameter REPEATER = "FALSE";
parameter RXACTST = "FALSE";
parameter RXAFEEQ = 9'b000000000;
parameter RXAFEPD = "FALSE";
parameter RXAFETST = "FALSE";
parameter RXAPD = "FALSE";
parameter RXAREGCTRL = 5'b00000;
parameter RXASYNCDIVIDE = 2'b11;
parameter RXBY_32 = "FALSE";
parameter RXCDRLOS = 6'b000000;
parameter RXCLK0_FORCE_PMACLK = "FALSE";
parameter RXCLKMODE = 6'b110001;
parameter RXCLMODE = 2'b00;
parameter RXCMADJ = 2'b01;
parameter RXCPSEL = "TRUE";
parameter RXCPTST = "FALSE";
parameter RXCRCCLOCKDOUBLE = "FALSE";
parameter RXCRCENABLE = "FALSE";
parameter RXCRCINITVAL = 32'h00000000;
parameter RXCRCINVERTGEN = "FALSE";
parameter RXCRCSAMECLOCK = "FALSE";
parameter RXCTRL1 = 10'h200;
parameter RXCYCLE_LIMIT_SEL = 2'b00;
parameter RXDATA_SEL = 2'b00;
parameter RXDCCOUPLE = "FALSE";
parameter RXDIGRESET = "FALSE";
parameter RXDIGRX = "FALSE";
parameter RXEQ = 64'h4000000000000000;
parameter RXFDCAL_CLOCK_DIVIDE = "NONE";
parameter RXFDET_HYS_CAL = 3'b010;
parameter RXFDET_HYS_SEL = 3'b100;
parameter RXFDET_LCK_CAL = 3'b100;
parameter RXFDET_LCK_SEL = 3'b001;
parameter RXFECONTROL1 = 2'b00;
parameter RXFECONTROL2 = 3'b000;
parameter RXFETUNE = 2'b01;
parameter RXLB = "FALSE";
parameter RXLKADJ = 5'b00000;
parameter RXLKAPD = "FALSE";
parameter RXLOOPCAL_WAIT = 2'b00;
parameter RXLOOPFILT = 4'b0111;
parameter RXMODE = 6'b000000;
parameter RXPD = "FALSE";
parameter RXPDDTST = "TRUE";
parameter RXPMACLKSEL = "REFCLK1";
parameter RXRCPADJ = 3'b011;
parameter RXRCPPD = "FALSE";
parameter RXRECCLK1_USE_SYNC = "FALSE";
parameter RXRIBADJ = 2'b11;
parameter RXRPDPD = "FALSE";
parameter RXRSDPD = "FALSE";
parameter RXSLOWDOWN_CAL = 2'b00;
parameter RXTUNE = 13'h0000;
parameter RXVCODAC_INIT = 10'b1010000000;
parameter RXVCO_CTRL_ENABLE = "FALSE";
parameter RX_BUFFER_USE = "TRUE";
parameter RX_CLOCK_DIVIDER = 2'b00;
parameter SAMPLE_8X = "FALSE";
parameter SLOWDOWN_CAL = 2'b00;
parameter TXABPMACLKSEL = "REFCLK1";
parameter TXAPD = "FALSE";
parameter TXAREFBIASSEL = "TRUE";
parameter TXASYNCDIVIDE = 2'b11;
parameter TXCLK0_FORCE_PMACLK = "FALSE";
parameter TXCLKMODE = 4'b1001;
parameter TXCLMODE = 2'b00;
parameter TXCPSEL = "TRUE";
parameter TXCRCCLOCKDOUBLE = "FALSE";
parameter TXCRCENABLE = "FALSE";
parameter TXCRCINITVAL = 32'h00000000;
parameter TXCRCINVERTGEN = "FALSE";
parameter TXCRCSAMECLOCK = "FALSE";
parameter TXCTRL1 = 10'h200;
parameter TXDATA_SEL = 2'b00;
parameter TXDAT_PRDRV_DAC = 3'b111;
parameter TXDAT_TAP_DAC = 5'b10110;
parameter TXDIGPD = "FALSE";
parameter TXFDCAL_CLOCK_DIVIDE = "NONE";
parameter TXHIGHSIGNALEN = "TRUE";
parameter TXLOOPFILT = 4'b0111;
parameter TXLVLSHFTPD = "FALSE";
parameter TXOUTCLK1_USE_SYNC = "FALSE";
parameter TXPD = "FALSE";
parameter TXPHASESEL = "FALSE";
parameter TXPOST_PRDRV_DAC = 3'b111;
parameter TXPOST_TAP_DAC = 5'b01110;
parameter TXPOST_TAP_PD = "TRUE";
parameter TXPRE_PRDRV_DAC = 3'b111;
parameter TXPRE_TAP_DAC = 5'b00000;
parameter TXPRE_TAP_PD = "TRUE";
parameter TXSLEWRATE = "FALSE";
parameter TXTERMTRIM = 4'b1100;
parameter TXTUNE = 13'h0000;
parameter TX_BUFFER_USE = "TRUE";
parameter TX_CLOCK_DIVIDER = 2'b00;
parameter VCODAC_INIT = 10'b1010000000;
parameter VCO_CTRL_ENABLE = "FALSE";
parameter VREFBIASMODE = 2'b11;
parameter integer ALIGN_COMMA_WORD = 4;
parameter integer CHAN_BOND_LIMIT = 16;
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter integer CLK_COR_MAX_LAT = 48;
parameter integer CLK_COR_MIN_LAT = 36;
parameter integer CLK_COR_SEQ_LEN = 1;
parameter integer RXOUTDIV2SEL = 1;
parameter integer RXPLLNDIVSEL = 8;
parameter integer RXUSRDIVISOR = 1;
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter integer TXOUTDIV2SEL = 1;
parameter integer TXPLLNDIVSEL = 8;
output [4:0] CHBONDO;
output [15:0] COMBUSOUT;
output [15:0] DO;
output DRDY;
output RXBUFERR;
output RXCALFAIL;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output RXCOMMADET;
output [31:0] RXCRCOUT;
output RXCYCLELIMIT;
output [63:0] RXDATA;
output [7:0] RXDISPERR;
output RXLOCK;
output [1:0] RXLOSSOFSYNC;
output RXMCLK;
output [7:0] RXNOTINTABLE;
output RXPCSHCLKOUT;
output RXREALIGN;
output RXRECCLK1;
output RXRECCLK2;
output [7:0] RXRUNDISP;
output RXSIGDET;
output [5:0] RXSTATUS;
output TX1N;
output TX1P;
output TXBUFERR;
output TXCALFAIL;
output [31:0] TXCRCOUT;
output TXCYCLELIMIT;
output [7:0] TXKERR;
output TXLOCK;
output TXOUTCLK1;
output TXOUTCLK2;
output TXPCSHCLKOUT;
output [7:0] TXRUNDISP;
input [4:0] CHBONDI;
input [15:0] COMBUSIN;
input [7:0] DADDR;
input DCLK;
input DEN;
input [15:0] DI;
input DWE;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input GREFCLK;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK1;
input REFCLK2;
input RX1N;
input RX1P;
input RXBLOCKSYNC64B66BUSE;
input RXCLKSTABLE;
input RXCOMMADETUSE;
input RXCRCCLK;
input RXCRCDATAVALID;
input [2:0] RXCRCDATAWIDTH;
input [63:0] RXCRCIN;
input RXCRCINIT;
input RXCRCINTCLK;
input RXCRCPD;
input RXCRCRESET;
input [1:0] RXDATAWIDTH;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input [1:0] RXINTDATAWIDTH;
input RXPMARESET;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXSYNC;
input RXUSRCLK;
input RXUSRCLK2;
input [7:0] TXBYPASS8B10B;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
input TXCLKSTABLE;
input TXCRCCLK;
input TXCRCDATAVALID;
input [2:0] TXCRCDATAWIDTH;
input [63:0] TXCRCIN;
input TXCRCINIT;
input TXCRCINTCLK;
input TXCRCPD;
input TXCRCRESET;
input [63:0] TXDATA;
input [1:0] TXDATAWIDTH;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXENOOB;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input [1:0] TXINTDATAWIDTH;
input TXPMARESET;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXSYNC;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_AURORA_1 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_AURORA_2 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_AURORA_4 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_CUSTOM (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter ALIGN_COMMA_MSB = "FALSE";
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter integer CHAN_BOND_OFFSET = 8;
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter integer CHAN_BOND_WAIT = 8;
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter CLK_CORRECT_USE = "TRUE";
parameter COMMA_10B_MASK = 10'b1111111000;
parameter CRC_END_OF_PKT = "K29_7";
parameter CRC_FORMAT = "USER_MODE";
parameter CRC_START_OF_PKT = "K27_7";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter MCOMMA_10B_VALUE = 10'b1100000000;
parameter MCOMMA_DETECT = "TRUE";
parameter PCOMMA_10B_VALUE = 10'b0011111000;
parameter PCOMMA_DETECT = "TRUE";
parameter integer REF_CLK_V_SEL = 0;
parameter RX_BUFFER_USE = "TRUE";
parameter RX_CRC_USE = "FALSE";
parameter integer RX_DATA_WIDTH = 2;
parameter RX_DECODE_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_BUFFER_USE = "TRUE";
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DATA_WIDTH = 2;
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_ETHERNET_1 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_ETHERNET_2 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_ETHERNET_4 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_FIBRE_CHAN_1 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 2;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_FIBRE_CHAN_2 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 2;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_FIBRE_CHAN_4 (CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 2;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_INFINIBAND_1 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter LANE_ID = 11'b00000000000;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_INFINIBAND_2 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter LANE_ID = 11'b00000000000;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_INFINIBAND_4 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter LANE_ID = 11'b00000000000;
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GTP_DUAL (DO, DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBUFSTATUS0, RXBUFSTATUS1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXCHBONDO0, RXCHBONDO1, RXCLKCORCNT0, RXCLKCORCNT1, RXCOMMADET0, RXCOMMADET1, RXDATA0, RXDATA1, RXDISPERR0, RXDISPERR1, RXELECIDLE0, RXELECIDLE1, RXLOSSOFSYNC0, RXLOSSOFSYNC1, RXNOTINTABLE0, RXNOTINTABLE1, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXRUNDISP0, RXRUNDISP1, RXSTATUS0, RXSTATUS1, RXVALID0, RXVALID1, TXBUFSTATUS0, TXBUFSTATUS1, TXKERR0, TXKERR1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, TXRUNDISP0, TXRUNDISP1, CLKIN, DADDR, DCLK, DEN, DI, DWE, GTPRESET, GTPTEST, INTDATAWIDTH, LOOPBACK0, LOOPBACK1, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCHBONDI0, RXCHBONDI1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDATAWIDTH0, RXDATAWIDTH1, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXELECIDLERESET0, RXELECIDLERESET1, RXENCHANSYNC0, RXENCHANSYNC1, RXENELECIDLERESETB, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENPRBSTST0, RXENPRBSTST1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXEQMIX0, RXEQMIX1, RXEQPOLE0, RXEQPOLE1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXPOWERDOWN0, RXPOWERDOWN1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDATA0, TXDATA1, TXDATAWIDTH0, TXDATAWIDTH1, TXDETECTRX0, TXDETECTRX1, TXDIFFCTRL0, TXDIFFCTRL1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1, TXENPMAPHASEALIGN, TXENPRBSTST0, TXENPRBSTST1, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE, TXPOLARITY0, TXPOLARITY1, TXPOWERDOWN0, TXPOWERDOWN1, TXPREEMPHASIS0, TXPREEMPHASIS1, TXRESET0, TXRESET1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21);
parameter AC_CAP_DIS_0 = "TRUE";
parameter AC_CAP_DIS_1 = "TRUE";
parameter CHAN_BOND_MODE_0 = "OFF";
parameter CHAN_BOND_MODE_1 = "OFF";
parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE";
parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE";
parameter CLKINDC_B = "TRUE";
parameter CLK_CORRECT_USE_0 = "TRUE";
parameter CLK_CORRECT_USE_1 = "TRUE";
parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
parameter CLK_COR_KEEP_IDLE_0 = "FALSE";
parameter CLK_COR_KEEP_IDLE_1 = "FALSE";
parameter CLK_COR_PRECEDENCE_0 = "TRUE";
parameter CLK_COR_PRECEDENCE_1 = "TRUE";
parameter CLK_COR_SEQ_2_USE_0 = "FALSE";
parameter CLK_COR_SEQ_2_USE_1 = "FALSE";
parameter COMMA_DOUBLE_0 = "FALSE";
parameter COMMA_DOUBLE_1 = "FALSE";
parameter DEC_MCOMMA_DETECT_0 = "TRUE";
parameter DEC_MCOMMA_DETECT_1 = "TRUE";
parameter DEC_PCOMMA_DETECT_0 = "TRUE";
parameter DEC_PCOMMA_DETECT_1 = "TRUE";
parameter DEC_VALID_COMMA_ONLY_0 = "TRUE";
parameter DEC_VALID_COMMA_ONLY_1 = "TRUE";
parameter MCOMMA_DETECT_0 = "TRUE";
parameter MCOMMA_DETECT_1 = "TRUE";
parameter OVERSAMPLE_MODE = "FALSE";
parameter PCI_EXPRESS_MODE_0 = "TRUE";
parameter PCI_EXPRESS_MODE_1 = "TRUE";
parameter PCOMMA_DETECT_0 = "TRUE";
parameter PCOMMA_DETECT_1 = "TRUE";
parameter PLL_SATA_0 = "FALSE";
parameter PLL_SATA_1 = "FALSE";
parameter RCV_TERM_GND_0 = "TRUE";
parameter RCV_TERM_GND_1 = "TRUE";
parameter RCV_TERM_MID_0 = "FALSE";
parameter RCV_TERM_MID_1 = "FALSE";
parameter RCV_TERM_VTTRX_0 = "FALSE";
parameter RCV_TERM_VTTRX_1 = "FALSE";
parameter RX_BUFFER_USE_0 = "TRUE";
parameter RX_BUFFER_USE_1 = "TRUE";
parameter RX_DECODE_SEQ_MATCH_0 = "TRUE";
parameter RX_DECODE_SEQ_MATCH_1 = "TRUE";
parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE";
parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE";
parameter RX_SLIDE_MODE_0 = "PCS";
parameter RX_SLIDE_MODE_1 = "PCS";
parameter RX_STATUS_FMT_0 = "PCIE";
parameter RX_STATUS_FMT_1 = "PCIE";
parameter RX_XCLK_SEL_0 = "RXREC";
parameter RX_XCLK_SEL_1 = "RXREC";
parameter SIM_MODE = "FAST";
parameter SIM_PLL_PERDIV2 = 9'h190;
parameter SIM_RECEIVER_DETECT_PASS0 = "FALSE";
parameter SIM_RECEIVER_DETECT_PASS1 = "FALSE";
parameter TERMINATION_OVRD = "FALSE";
parameter TX_BUFFER_USE_0 = "TRUE";
parameter TX_BUFFER_USE_1 = "TRUE";
parameter TX_DIFF_BOOST_0 = "TRUE";
parameter TX_DIFF_BOOST_1 = "TRUE";
parameter TX_XCLK_SEL_0 = "TXUSR";
parameter TX_XCLK_SEL_1 = "TXUSR";
parameter [15:0] TRANS_TIME_FROM_P2_0 = 16'h003c;
parameter [15:0] TRANS_TIME_FROM_P2_1 = 16'h003c;
parameter [15:0] TRANS_TIME_NON_P2_0 = 16'h0019;
parameter [15:0] TRANS_TIME_NON_P2_1 = 16'h0019;
parameter [15:0] TRANS_TIME_TO_P2_0 = 16'h0064;
parameter [15:0] TRANS_TIME_TO_P2_1 = 16'h0064;
parameter [24:0] PMA_RX_CFG_0 = 25'h09f0089;
parameter [24:0] PMA_RX_CFG_1 = 25'h09f0089;
parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c07640;
parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c07640;
parameter [27:0] PCS_COM_CFG = 28'h1680a0e;
parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b001;
parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b001;
parameter [2:0] SATA_BURST_VAL_0 = 3'b100;
parameter [2:0] SATA_BURST_VAL_1 = 3'b100;
parameter [2:0] SATA_IDLE_VAL_0 = 3'b011;
parameter [2:0] SATA_IDLE_VAL_1 = 3'b011;
parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1;
parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111;
parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111;
parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111;
parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111;
parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111;
parameter [3:0] COM_BURST_VAL_0 = 4'b1111;
parameter [3:0] COM_BURST_VAL_1 = 4'b1111;
parameter [4:0] TERMINATION_CTRL = 5'b10100;
parameter [4:0] TXRX_INVERT_0 = 5'b00000;
parameter [4:0] TXRX_INVERT_1 = 5'b00000;
parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010;
parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010;
parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010;
parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010;
parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010;
parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010;
parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100;
parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100;
parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100;
parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100;
parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100;
parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100;
parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100;
parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100;
parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100;
parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100;
parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0;
parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0;
parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0;
parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0;
parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0;
parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0;
parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0;
parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0;
parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0;
parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0;
parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0;
parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0;
parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0;
parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0;
parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111;
parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111;
parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011;
parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011;
parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100;
parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100;
parameter integer ALIGN_COMMA_WORD_0 = 1;
parameter integer ALIGN_COMMA_WORD_1 = 1;
parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7;
parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7;
parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1;
parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1;
parameter integer CHAN_BOND_LEVEL_0 = 0;
parameter integer CHAN_BOND_LEVEL_1 = 0;
parameter integer CHAN_BOND_SEQ_LEN_0 = 4;
parameter integer CHAN_BOND_SEQ_LEN_1 = 4;
parameter integer CLK25_DIVIDER = 4;
parameter integer CLK_COR_ADJ_LEN_0 = 1;
parameter integer CLK_COR_ADJ_LEN_1 = 1;
parameter integer CLK_COR_DET_LEN_0 = 1;
parameter integer CLK_COR_DET_LEN_1 = 1;
parameter integer CLK_COR_MAX_LAT_0 = 18;
parameter integer CLK_COR_MAX_LAT_1 = 18;
parameter integer CLK_COR_MIN_LAT_0 = 16;
parameter integer CLK_COR_MIN_LAT_1 = 16;
parameter integer CLK_COR_REPEAT_WAIT_0 = 5;
parameter integer CLK_COR_REPEAT_WAIT_1 = 5;
parameter integer OOB_CLK_DIVIDER = 4;
parameter integer PLL_DIVSEL_FB = 5;
parameter integer PLL_DIVSEL_REF = 2;
parameter integer PLL_RXDIVSEL_OUT_0 = 1;
parameter integer PLL_RXDIVSEL_OUT_1 = 1;
parameter integer PLL_TXDIVSEL_COMM_OUT = 1;
parameter integer PLL_TXDIVSEL_OUT_0 = 1;
parameter integer PLL_TXDIVSEL_OUT_1 = 1;
parameter integer RX_LOS_INVALID_INCR_0 = 8;
parameter integer RX_LOS_INVALID_INCR_1 = 8;
parameter integer RX_LOS_THRESHOLD_0 = 128;
parameter integer RX_LOS_THRESHOLD_1 = 128;
parameter integer SATA_MAX_BURST_0 = 7;
parameter integer SATA_MAX_BURST_1 = 7;
parameter integer SATA_MAX_INIT_0 = 22;
parameter integer SATA_MAX_INIT_1 = 22;
parameter integer SATA_MAX_WAKE_0 = 7;
parameter integer SATA_MAX_WAKE_1 = 7;
parameter integer SATA_MIN_BURST_0 = 4;
parameter integer SATA_MIN_BURST_1 = 4;
parameter integer SATA_MIN_INIT_0 = 12;
parameter integer SATA_MIN_INIT_1 = 12;
parameter integer SATA_MIN_WAKE_0 = 4;
parameter integer SATA_MIN_WAKE_1 = 4;
parameter integer SIM_GTPRESET_SPEEDUP = 0;
parameter integer TERMINATION_IMP_0 = 50;
parameter integer TERMINATION_IMP_1 = 50;
parameter integer TX_SYNC_FILTERB = 1;
output [15:0] DO;
output DRDY;
output PHYSTATUS0;
output PHYSTATUS1;
output PLLLKDET;
output REFCLKOUT;
output RESETDONE0;
output RESETDONE1;
output [2:0] RXBUFSTATUS0;
output [2:0] RXBUFSTATUS1;
output RXBYTEISALIGNED0;
output RXBYTEISALIGNED1;
output RXBYTEREALIGN0;
output RXBYTEREALIGN1;
output RXCHANBONDSEQ0;
output RXCHANBONDSEQ1;
output RXCHANISALIGNED0;
output RXCHANISALIGNED1;
output RXCHANREALIGN0;
output RXCHANREALIGN1;
output [1:0] RXCHARISCOMMA0;
output [1:0] RXCHARISCOMMA1;
output [1:0] RXCHARISK0;
output [1:0] RXCHARISK1;
output [2:0] RXCHBONDO0;
output [2:0] RXCHBONDO1;
output [2:0] RXCLKCORCNT0;
output [2:0] RXCLKCORCNT1;
output RXCOMMADET0;
output RXCOMMADET1;
output [15:0] RXDATA0;
output [15:0] RXDATA1;
output [1:0] RXDISPERR0;
output [1:0] RXDISPERR1;
output RXELECIDLE0;
output RXELECIDLE1;
output [1:0] RXLOSSOFSYNC0;
output [1:0] RXLOSSOFSYNC1;
output [1:0] RXNOTINTABLE0;
output [1:0] RXNOTINTABLE1;
output RXOVERSAMPLEERR0;
output RXOVERSAMPLEERR1;
output RXPRBSERR0;
output RXPRBSERR1;
output RXRECCLK0;
output RXRECCLK1;
output [1:0] RXRUNDISP0;
output [1:0] RXRUNDISP1;
output [2:0] RXSTATUS0;
output [2:0] RXSTATUS1;
output RXVALID0;
output RXVALID1;
output [1:0] TXBUFSTATUS0;
output [1:0] TXBUFSTATUS1;
output [1:0] TXKERR0;
output [1:0] TXKERR1;
output TXN0;
output TXN1;
output TXOUTCLK0;
output TXOUTCLK1;
output TXP0;
output TXP1;
output [1:0] TXRUNDISP0;
output [1:0] TXRUNDISP1;
input CLKIN;
input [6:0] DADDR;
input DCLK;
input DEN;
input [15:0] DI;
input DWE;
input GTPRESET;
input [3:0] GTPTEST;
input INTDATAWIDTH;
input [2:0] LOOPBACK0;
input [2:0] LOOPBACK1;
input PLLLKDETEN;
input PLLPOWERDOWN;
input PRBSCNTRESET0;
input PRBSCNTRESET1;
input REFCLKPWRDNB;
input RXBUFRESET0;
input RXBUFRESET1;
input RXCDRRESET0;
input RXCDRRESET1;
input [2:0] RXCHBONDI0;
input [2:0] RXCHBONDI1;
input RXCOMMADETUSE0;
input RXCOMMADETUSE1;
input RXDATAWIDTH0;
input RXDATAWIDTH1;
input RXDEC8B10BUSE0;
input RXDEC8B10BUSE1;
input RXELECIDLERESET0;
input RXELECIDLERESET1;
input RXENCHANSYNC0;
input RXENCHANSYNC1;
input RXENELECIDLERESETB;
input RXENEQB0;
input RXENEQB1;
input RXENMCOMMAALIGN0;
input RXENMCOMMAALIGN1;
input RXENPCOMMAALIGN0;
input RXENPCOMMAALIGN1;
input [1:0] RXENPRBSTST0;
input [1:0] RXENPRBSTST1;
input RXENSAMPLEALIGN0;
input RXENSAMPLEALIGN1;
input [1:0] RXEQMIX0;
input [1:0] RXEQMIX1;
input [3:0] RXEQPOLE0;
input [3:0] RXEQPOLE1;
input RXN0;
input RXN1;
input RXP0;
input RXP1;
input RXPMASETPHASE0;
input RXPMASETPHASE1;
input RXPOLARITY0;
input RXPOLARITY1;
input [1:0] RXPOWERDOWN0;
input [1:0] RXPOWERDOWN1;
input RXRESET0;
input RXRESET1;
input RXSLIDE0;
input RXSLIDE1;
input RXUSRCLK0;
input RXUSRCLK1;
input RXUSRCLK20;
input RXUSRCLK21;
input [2:0] TXBUFDIFFCTRL0;
input [2:0] TXBUFDIFFCTRL1;
input [1:0] TXBYPASS8B10B0;
input [1:0] TXBYPASS8B10B1;
input [1:0] TXCHARDISPMODE0;
input [1:0] TXCHARDISPMODE1;
input [1:0] TXCHARDISPVAL0;
input [1:0] TXCHARDISPVAL1;
input [1:0] TXCHARISK0;
input [1:0] TXCHARISK1;
input TXCOMSTART0;
input TXCOMSTART1;
input TXCOMTYPE0;
input TXCOMTYPE1;
input [15:0] TXDATA0;
input [15:0] TXDATA1;
input TXDATAWIDTH0;
input TXDATAWIDTH1;
input TXDETECTRX0;
input TXDETECTRX1;
input [2:0] TXDIFFCTRL0;
input [2:0] TXDIFFCTRL1;
input TXELECIDLE0;
input TXELECIDLE1;
input TXENC8B10BUSE0;
input TXENC8B10BUSE1;
input TXENPMAPHASEALIGN;
input [1:0] TXENPRBSTST0;
input [1:0] TXENPRBSTST1;
input TXINHIBIT0;
input TXINHIBIT1;
input TXPMASETPHASE;
input TXPOLARITY0;
input TXPOLARITY1;
input [1:0] TXPOWERDOWN0;
input [1:0] TXPOWERDOWN1;
input [2:0] TXPREEMPHASIS0;
input [2:0] TXPREEMPHASIS1;
input TXRESET0;
input TXRESET1;
input TXUSRCLK0;
input TXUSRCLK1;
input TXUSRCLK20;
input TXUSRCLK21;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter ALIGN_COMMA_MSB = "FALSE";
parameter integer CHAN_BOND_LIMIT = 16;
parameter CHAN_BOND_MODE = "OFF";
parameter integer CHAN_BOND_OFFSET = 8;
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter integer CHAN_BOND_WAIT = 8;
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter CLK_CORRECT_USE = "TRUE";
parameter COMMA_10B_MASK = 10'b1111111000;
parameter CRC_END_OF_PKT = "K29_7";
parameter CRC_FORMAT = "USER_MODE";
parameter CRC_START_OF_PKT = "K27_7";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter MCOMMA_10B_VALUE = 10'b1100000000;
parameter MCOMMA_DETECT = "TRUE";
parameter PCOMMA_10B_VALUE = 10'b0011111000;
parameter PCOMMA_DETECT = "TRUE";
parameter integer REF_CLK_V_SEL = 0;
parameter RX_BUFFER_USE = "TRUE";
parameter RX_CRC_USE = "FALSE";
parameter integer RX_DATA_WIDTH = 2;
parameter RX_DECODE_USE = "TRUE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_BUFFER_USE = "TRUE";
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DATA_WIDTH = 2;
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_XAUI_1 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter CRC_END_OF_PKT = "K29_7";
parameter CRC_FORMAT = "USER_MODE";
parameter CRC_START_OF_PKT = "K27_7";
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [0:0] RXCHARISCOMMA;
output [0:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [7:0] RXDATA;
output [0:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [0:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [0:0] RXRUNDISP;
output TXBUFERR;
output [0:0] TXKERR;
output TXN;
output TXP;
output [0:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [0:0] TXBYPASS8B10B;
input [0:0] TXCHARDISPMODE;
input [0:0] TXCHARDISPVAL;
input [0:0] TXCHARISK;
input [7:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_XAUI_2 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter CRC_END_OF_PKT = "K29_7";
parameter CRC_FORMAT = "USER_MODE";
parameter CRC_START_OF_PKT = "K27_7";
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXP;
output [1:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GT_XAUI_4 (CHBONDDONE, CHBONDO, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP, BREFCLK, BREFCLK2, CHBONDI, CONFIGENABLE, CONFIGIN, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2);
parameter CHAN_BOND_MODE = "OFF";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_REPEAT_WAIT = 1;
parameter CRC_END_OF_PKT = "K29_7";
parameter CRC_FORMAT = "USER_MODE";
parameter CRC_START_OF_PKT = "K27_7";
parameter integer REF_CLK_V_SEL = 0;
parameter RX_CRC_USE = "FALSE";
parameter integer RX_LOS_INVALID_INCR = 1;
parameter integer RX_LOS_THRESHOLD = 4;
parameter RX_LOSS_OF_SYNC_FSM = "TRUE";
parameter SERDES_10B = "FALSE";
parameter integer TERMINATION_IMP = 50;
parameter TX_CRC_FORCE_VALUE = 8'b11010110;
parameter TX_CRC_USE = "FALSE";
parameter integer TX_DIFF_CTRL = 500;
parameter integer TX_PREEMPHASIS = 0;
output CHBONDDONE;
output [3:0] CHBONDO;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [3:0] RXCHARISCOMMA;
output [3:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [31:0] RXDATA;
output [3:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [3:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [3:0] RXRUNDISP;
output TXBUFERR;
output [3:0] TXKERR;
output TXN;
output TXP;
output [3:0] TXRUNDISP;
input BREFCLK;
input BREFCLK2;
input [3:0] CHBONDI;
input CONFIGENABLE;
input CONFIGIN;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [3:0] TXBYPASS8B10B;
input [3:0] TXCHARDISPMODE;
input [3:0] TXCHARDISPVAL;
input [3:0] TXCHARISK;
input [31:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module GTX_DUAL (DFECLKDLYADJMONITOR0, DFECLKDLYADJMONITOR1, DFEEYEDACMONITOR0, DFEEYEDACMONITOR1, DFESENSCAL0, DFESENSCAL1, DFETAP1MONITOR0, DFETAP1MONITOR1, DFETAP2MONITOR0, DFETAP2MONITOR1, DFETAP3MONITOR0, DFETAP3MONITOR1, DFETAP4MONITOR0, DFETAP4MONITOR1, DO, DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBUFSTATUS0, RXBUFSTATUS1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXCHBONDO0, RXCHBONDO1, RXCLKCORCNT0, RXCLKCORCNT1, RXCOMMADET0, RXCOMMADET1, RXDATA0, RXDATA1, RXDATAVALID0, RXDATAVALID1, RXDISPERR0, RXDISPERR1, RXELECIDLE0, RXELECIDLE1, RXHEADER0, RXHEADER1, RXHEADERVALID0, RXHEADERVALID1, RXLOSSOFSYNC0, RXLOSSOFSYNC1, RXNOTINTABLE0, RXNOTINTABLE1, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXRUNDISP0, RXRUNDISP1, RXSTARTOFSEQ0, RXSTARTOFSEQ1, RXSTATUS0, RXSTATUS1, RXVALID0, RXVALID1, TXBUFSTATUS0, TXBUFSTATUS1, TXGEARBOXREADY0, TXGEARBOXREADY1, TXKERR0, TXKERR1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, TXRUNDISP0, TXRUNDISP1, CLKIN, DADDR, DCLK, DEN, DFECLKDLYADJ0, DFECLKDLYADJ1, DFETAP10, DFETAP11, DFETAP20, DFETAP21, DFETAP30, DFETAP31, DFETAP40, DFETAP41, DI, DWE, GTXRESET, GTXTEST, INTDATAWIDTH, LOOPBACK0, LOOPBACK1, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCHBONDI0, RXCHBONDI1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDATAWIDTH0, RXDATAWIDTH1, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXENCHANSYNC0, RXENCHANSYNC1, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENPMAPHASEALIGN0, RXENPMAPHASEALIGN1, RXENPRBSTST0, RXENPRBSTST1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXEQMIX0, RXEQMIX1, RXEQPOLE0, RXEQPOLE1, RXGEARBOXSLIP0, RXGEARBOXSLIP1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXPOWERDOWN0, RXPOWERDOWN1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDATA0, TXDATA1, TXDATAWIDTH0, TXDATAWIDTH1, TXDETECTRX0, TXDETECTRX1, TXDIFFCTRL0, TXDIFFCTRL1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1, TXENPMAPHASEALIGN0, TXENPMAPHASEALIGN1, TXENPRBSTST0, TXENPRBSTST1, TXHEADER0, TXHEADER1, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE0, TXPMASETPHASE1, TXPOLARITY0, TXPOLARITY1, TXPOWERDOWN0, TXPOWERDOWN1, TXPREEMPHASIS0, TXPREEMPHASIS1, TXRESET0, TXRESET1, TXSEQUENCE0, TXSEQUENCE1, TXSTARTSEQ0, TXSTARTSEQ1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21);
parameter AC_CAP_DIS_0 = "TRUE";
parameter AC_CAP_DIS_1 = "TRUE";
parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE";
parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE";
parameter CHAN_BOND_MODE_0 = "OFF";
parameter CHAN_BOND_MODE_1 = "OFF";
parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE";
parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE";
parameter CLKINDC_B = "TRUE";
parameter CLKRCV_TRST = "TRUE";
parameter CLK_CORRECT_USE_0 = "TRUE";
parameter CLK_CORRECT_USE_1 = "TRUE";
parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
parameter CLK_COR_KEEP_IDLE_0 = "FALSE";
parameter CLK_COR_KEEP_IDLE_1 = "FALSE";
parameter CLK_COR_PRECEDENCE_0 = "TRUE";
parameter CLK_COR_PRECEDENCE_1 = "TRUE";
parameter CLK_COR_SEQ_2_USE_0 = "FALSE";
parameter CLK_COR_SEQ_2_USE_1 = "FALSE";
parameter COMMA_DOUBLE_0 = "FALSE";
parameter COMMA_DOUBLE_1 = "FALSE";
parameter DEC_MCOMMA_DETECT_0 = "TRUE";
parameter DEC_MCOMMA_DETECT_1 = "TRUE";
parameter DEC_PCOMMA_DETECT_0 = "TRUE";
parameter DEC_PCOMMA_DETECT_1 = "TRUE";
parameter DEC_VALID_COMMA_ONLY_0 = "TRUE";
parameter DEC_VALID_COMMA_ONLY_1 = "TRUE";
parameter MCOMMA_DETECT_0 = "TRUE";
parameter MCOMMA_DETECT_1 = "TRUE";
parameter OVERSAMPLE_MODE = "FALSE";
parameter PCI_EXPRESS_MODE_0 = "FALSE";
parameter PCI_EXPRESS_MODE_1 = "FALSE";
parameter PCOMMA_DETECT_0 = "TRUE";
parameter PCOMMA_DETECT_1 = "TRUE";
parameter PLL_FB_DCCEN = "FALSE";
parameter PLL_SATA_0 = "FALSE";
parameter PLL_SATA_1 = "FALSE";
parameter RCV_TERM_GND_0 = "FALSE";
parameter RCV_TERM_GND_1 = "FALSE";
parameter RCV_TERM_VTTRX_0 = "FALSE";
parameter RCV_TERM_VTTRX_1 = "FALSE";
parameter RXGEARBOX_USE_0 = "FALSE";
parameter RXGEARBOX_USE_1 = "FALSE";
parameter RX_BUFFER_USE_0 = "TRUE";
parameter RX_BUFFER_USE_1 = "TRUE";
parameter RX_DECODE_SEQ_MATCH_0 = "TRUE";
parameter RX_DECODE_SEQ_MATCH_1 = "TRUE";
parameter RX_EN_IDLE_HOLD_CDR = "FALSE";
parameter RX_EN_IDLE_HOLD_DFE_0 = "TRUE";
parameter RX_EN_IDLE_HOLD_DFE_1 = "TRUE";
parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE";
parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE";
parameter RX_EN_IDLE_RESET_FR = "TRUE";
parameter RX_EN_IDLE_RESET_PH = "TRUE";
parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE";
parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE";
parameter RX_SLIDE_MODE_0 = "PCS";
parameter RX_SLIDE_MODE_1 = "PCS";
parameter RX_STATUS_FMT_0 = "PCIE";
parameter RX_STATUS_FMT_1 = "PCIE";
parameter RX_XCLK_SEL_0 = "RXREC";
parameter RX_XCLK_SEL_1 = "RXREC";
parameter SIM_MODE = "FAST";
parameter SIM_PLL_PERDIV2 = 9'h140;
parameter SIM_RECEIVER_DETECT_PASS_0 = "TRUE";
parameter SIM_RECEIVER_DETECT_PASS_1 = "TRUE";
parameter TERMINATION_OVRD = "FALSE";
parameter TXGEARBOX_USE_0 = "FALSE";
parameter TXGEARBOX_USE_1 = "FALSE";
parameter TX_BUFFER_USE_0 = "TRUE";
parameter TX_BUFFER_USE_1 = "TRUE";
parameter TX_XCLK_SEL_0 = "TXOUT";
parameter TX_XCLK_SEL_1 = "TXOUT";
parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03c;
parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03c;
parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832;
parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832;
parameter [19:0] PMA_TX_CFG_0 = 20'h80082;
parameter [19:0] PMA_TX_CFG_1 = 20'h80082;
parameter [1:0] CM_TRIM_0 = 2'b10;
parameter [1:0] CM_TRIM_1 = 2'b10;
parameter [23:0] PLL_COM_CFG = 24'h21680a;
parameter [24:0] PMA_RX_CFG_0 = 25'h0f44089;
parameter [24:0] PMA_RX_CFG_1 = 25'h0f44089;
parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404035;
parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404035;
parameter [2:0] GEARBOX_ENDEC_0 = 3'b000;
parameter [2:0] GEARBOX_ENDEC_1 = 3'b000;
parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110;
parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110;
parameter [2:0] PLL_LKDET_CFG = 3'b101;
parameter [2:0] PLL_TDCC_CFG = 3'b000;
parameter [2:0] SATA_BURST_VAL_0 = 3'b100;
parameter [2:0] SATA_BURST_VAL_1 = 3'b100;
parameter [2:0] SATA_IDLE_VAL_0 = 3'b100;
parameter [2:0] SATA_IDLE_VAL_1 = 3'b100;
parameter [2:0] TXRX_INVERT_0 = 3'b011;
parameter [2:0] TXRX_INVERT_1 = 3'b011;
parameter [2:0] TX_IDLE_DELAY_0 = 3'b010;
parameter [2:0] TX_IDLE_DELAY_1 = 3'b010;
parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h00000001;
parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h00000001;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b0001;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b0001;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b0000;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b0000;
parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b0001;
parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b0001;
parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b0000;
parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b0000;
parameter [3:0] COM_BURST_VAL_0 = 4'b1111;
parameter [3:0] COM_BURST_VAL_1 = 4'b1111;
parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000;
parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000;
parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000;
parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000;
parameter [4:0] CDR_PH_ADJ_TIME = 5'b01010;
parameter [4:0] DFE_CAL_TIME = 5'b00110;
parameter [4:0] TERMINATION_CTRL = 5'b10100;
parameter [68:0] PMA_COM_CFG = 69'h0;
parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h0;
parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h0;
parameter [7:0] PLL_CP_CFG = 8'h00;
parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19;
parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19;
parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100;
parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100;
parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000;
parameter [9:0] COMMA_10B_ENABLE_0 = 10'b0001111111;
parameter [9:0] COMMA_10B_ENABLE_1 = 10'b0001111111;
parameter [9:0] DFE_CFG_0 = 10'b1101111011;
parameter [9:0] DFE_CFG_1 = 10'b1101111011;
parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011;
parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011;
parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100;
parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100;
parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064;
parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064;
parameter integer ALIGN_COMMA_WORD_0 = 1;
parameter integer ALIGN_COMMA_WORD_1 = 1;
parameter integer CB2_INH_CC_PERIOD_0 = 8;
parameter integer CB2_INH_CC_PERIOD_1 = 8;
parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7;
parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7;
parameter integer CHAN_BOND_2_MAX_SKEW_0 = 7;
parameter integer CHAN_BOND_2_MAX_SKEW_1 = 7;
parameter integer CHAN_BOND_LEVEL_0 = 0;
parameter integer CHAN_BOND_LEVEL_1 = 0;
parameter integer CHAN_BOND_SEQ_LEN_0 = 1;
parameter integer CHAN_BOND_SEQ_LEN_1 = 1;
parameter integer CLK25_DIVIDER = 10;
parameter integer CLK_COR_ADJ_LEN_0 = 1;
parameter integer CLK_COR_ADJ_LEN_1 = 1;
parameter integer CLK_COR_DET_LEN_0 = 1;
parameter integer CLK_COR_DET_LEN_1 = 1;
parameter integer CLK_COR_MAX_LAT_0 = 20;
parameter integer CLK_COR_MAX_LAT_1 = 20;
parameter integer CLK_COR_MIN_LAT_0 = 18;
parameter integer CLK_COR_MIN_LAT_1 = 18;
parameter integer CLK_COR_REPEAT_WAIT_0 = 0;
parameter integer CLK_COR_REPEAT_WAIT_1 = 0;
parameter integer OOB_CLK_DIVIDER = 6;
parameter integer PLL_DIVSEL_FB = 2;
parameter integer PLL_DIVSEL_REF = 1;
parameter integer PLL_RXDIVSEL_OUT_0 = 1;
parameter integer PLL_RXDIVSEL_OUT_1 = 1;
parameter integer PLL_TXDIVSEL_OUT_0 = 1;
parameter integer PLL_TXDIVSEL_OUT_1 = 1;
parameter integer RX_LOS_INVALID_INCR_0 = 1;
parameter integer RX_LOS_INVALID_INCR_1 = 1;
parameter integer RX_LOS_THRESHOLD_0 = 4;
parameter integer RX_LOS_THRESHOLD_1 = 4;
parameter integer SATA_MAX_BURST_0 = 7;
parameter integer SATA_MAX_BURST_1 = 7;
parameter integer SATA_MAX_INIT_0 = 22;
parameter integer SATA_MAX_INIT_1 = 22;
parameter integer SATA_MAX_WAKE_0 = 7;
parameter integer SATA_MAX_WAKE_1 = 7;
parameter integer SATA_MIN_BURST_0 = 4;
parameter integer SATA_MIN_BURST_1 = 4;
parameter integer SATA_MIN_INIT_0 = 12;
parameter integer SATA_MIN_INIT_1 = 12;
parameter integer SATA_MIN_WAKE_0 = 4;
parameter integer SATA_MIN_WAKE_1 = 4;
parameter integer SIM_GTXRESET_SPEEDUP = 1;
parameter integer TERMINATION_IMP_0 = 50;
parameter integer TERMINATION_IMP_1 = 50;
output [5:0] DFECLKDLYADJMONITOR0;
output [5:0] DFECLKDLYADJMONITOR1;
output [4:0] DFEEYEDACMONITOR0;
output [4:0] DFEEYEDACMONITOR1;
output [2:0] DFESENSCAL0;
output [2:0] DFESENSCAL1;
output [4:0] DFETAP1MONITOR0;
output [4:0] DFETAP1MONITOR1;
output [4:0] DFETAP2MONITOR0;
output [4:0] DFETAP2MONITOR1;
output [3:0] DFETAP3MONITOR0;
output [3:0] DFETAP3MONITOR1;
output [3:0] DFETAP4MONITOR0;
output [3:0] DFETAP4MONITOR1;
output [15:0] DO;
output DRDY;
output PHYSTATUS0;
output PHYSTATUS1;
output PLLLKDET;
output REFCLKOUT;
output RESETDONE0;
output RESETDONE1;
output [2:0] RXBUFSTATUS0;
output [2:0] RXBUFSTATUS1;
output RXBYTEISALIGNED0;
output RXBYTEISALIGNED1;
output RXBYTEREALIGN0;
output RXBYTEREALIGN1;
output RXCHANBONDSEQ0;
output RXCHANBONDSEQ1;
output RXCHANISALIGNED0;
output RXCHANISALIGNED1;
output RXCHANREALIGN0;
output RXCHANREALIGN1;
output [3:0] RXCHARISCOMMA0;
output [3:0] RXCHARISCOMMA1;
output [3:0] RXCHARISK0;
output [3:0] RXCHARISK1;
output [3:0] RXCHBONDO0;
output [3:0] RXCHBONDO1;
output [2:0] RXCLKCORCNT0;
output [2:0] RXCLKCORCNT1;
output RXCOMMADET0;
output RXCOMMADET1;
output [31:0] RXDATA0;
output [31:0] RXDATA1;
output RXDATAVALID0;
output RXDATAVALID1;
output [3:0] RXDISPERR0;
output [3:0] RXDISPERR1;
output RXELECIDLE0;
output RXELECIDLE1;
output [2:0] RXHEADER0;
output [2:0] RXHEADER1;
output RXHEADERVALID0;
output RXHEADERVALID1;
output [1:0] RXLOSSOFSYNC0;
output [1:0] RXLOSSOFSYNC1;
output [3:0] RXNOTINTABLE0;
output [3:0] RXNOTINTABLE1;
output RXOVERSAMPLEERR0;
output RXOVERSAMPLEERR1;
output RXPRBSERR0;
output RXPRBSERR1;
output RXRECCLK0;
output RXRECCLK1;
output [3:0] RXRUNDISP0;
output [3:0] RXRUNDISP1;
output RXSTARTOFSEQ0;
output RXSTARTOFSEQ1;
output [2:0] RXSTATUS0;
output [2:0] RXSTATUS1;
output RXVALID0;
output RXVALID1;
output [1:0] TXBUFSTATUS0;
output [1:0] TXBUFSTATUS1;
output TXGEARBOXREADY0;
output TXGEARBOXREADY1;
output [3:0] TXKERR0;
output [3:0] TXKERR1;
output TXN0;
output TXN1;
output TXOUTCLK0;
output TXOUTCLK1;
output TXP0;
output TXP1;
output [3:0] TXRUNDISP0;
output [3:0] TXRUNDISP1;
input CLKIN;
input [6:0] DADDR;
input DCLK;
input DEN;
input [5:0] DFECLKDLYADJ0;
input [5:0] DFECLKDLYADJ1;
input [4:0] DFETAP10;
input [4:0] DFETAP11;
input [4:0] DFETAP20;
input [4:0] DFETAP21;
input [3:0] DFETAP30;
input [3:0] DFETAP31;
input [3:0] DFETAP40;
input [3:0] DFETAP41;
input [15:0] DI;
input DWE;
input GTXRESET;
input [13:0] GTXTEST;
input INTDATAWIDTH;
input [2:0] LOOPBACK0;
input [2:0] LOOPBACK1;
input PLLLKDETEN;
input PLLPOWERDOWN;
input PRBSCNTRESET0;
input PRBSCNTRESET1;
input REFCLKPWRDNB;
input RXBUFRESET0;
input RXBUFRESET1;
input RXCDRRESET0;
input RXCDRRESET1;
input [3:0] RXCHBONDI0;
input [3:0] RXCHBONDI1;
input RXCOMMADETUSE0;
input RXCOMMADETUSE1;
input [1:0] RXDATAWIDTH0;
input [1:0] RXDATAWIDTH1;
input RXDEC8B10BUSE0;
input RXDEC8B10BUSE1;
input RXENCHANSYNC0;
input RXENCHANSYNC1;
input RXENEQB0;
input RXENEQB1;
input RXENMCOMMAALIGN0;
input RXENMCOMMAALIGN1;
input RXENPCOMMAALIGN0;
input RXENPCOMMAALIGN1;
input RXENPMAPHASEALIGN0;
input RXENPMAPHASEALIGN1;
input [1:0] RXENPRBSTST0;
input [1:0] RXENPRBSTST1;
input RXENSAMPLEALIGN0;
input RXENSAMPLEALIGN1;
input [1:0] RXEQMIX0;
input [1:0] RXEQMIX1;
input [3:0] RXEQPOLE0;
input [3:0] RXEQPOLE1;
input RXGEARBOXSLIP0;
input RXGEARBOXSLIP1;
input RXN0;
input RXN1;
input RXP0;
input RXP1;
input RXPMASETPHASE0;
input RXPMASETPHASE1;
input RXPOLARITY0;
input RXPOLARITY1;
input [1:0] RXPOWERDOWN0;
input [1:0] RXPOWERDOWN1;
input RXRESET0;
input RXRESET1;
input RXSLIDE0;
input RXSLIDE1;
input RXUSRCLK0;
input RXUSRCLK1;
input RXUSRCLK20;
input RXUSRCLK21;
input [2:0] TXBUFDIFFCTRL0;
input [2:0] TXBUFDIFFCTRL1;
input [3:0] TXBYPASS8B10B0;
input [3:0] TXBYPASS8B10B1;
input [3:0] TXCHARDISPMODE0;
input [3:0] TXCHARDISPMODE1;
input [3:0] TXCHARDISPVAL0;
input [3:0] TXCHARDISPVAL1;
input [3:0] TXCHARISK0;
input [3:0] TXCHARISK1;
input TXCOMSTART0;
input TXCOMSTART1;
input TXCOMTYPE0;
input TXCOMTYPE1;
input [31:0] TXDATA0;
input [31:0] TXDATA1;
input [1:0] TXDATAWIDTH0;
input [1:0] TXDATAWIDTH1;
input TXDETECTRX0;
input TXDETECTRX1;
input [2:0] TXDIFFCTRL0;
input [2:0] TXDIFFCTRL1;
input TXELECIDLE0;
input TXELECIDLE1;
input TXENC8B10BUSE0;
input TXENC8B10BUSE1;
input TXENPMAPHASEALIGN0;
input TXENPMAPHASEALIGN1;
input [1:0] TXENPRBSTST0;
input [1:0] TXENPRBSTST1;
input [2:0] TXHEADER0;
input [2:0] TXHEADER1;
input TXINHIBIT0;
input TXINHIBIT1;
input TXPMASETPHASE0;
input TXPMASETPHASE1;
input TXPOLARITY0;
input TXPOLARITY1;
input [1:0] TXPOWERDOWN0;
input [1:0] TXPOWERDOWN1;
input [3:0] TXPREEMPHASIS0;
input [3:0] TXPREEMPHASIS1;
input TXRESET0;
input TXRESET1;
input [6:0] TXSEQUENCE0;
input [6:0] TXSEQUENCE1;
input TXSTARTSEQ0;
input TXSTARTSEQ1;
input TXUSRCLK0;
input TXUSRCLK1;
input TXUSRCLK20;
input TXUSRCLK21;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_AGP (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_CTT (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_DLY_ADJ (O, I, S);
parameter DELAY_OFFSET = "OFF";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
input [2:0] S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_BLVDS_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_DIFF_OUT (O, OB, I, IB);
parameter IOSTANDARD = "LVDS_25";
output O;
output OB;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_DLY_ADJ (O, I, IB, S);
parameter DELAY_OFFSET = "OFF";
parameter DIFF_TERM = "FALSE";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
input IB;
input [2:0] S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LDT_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVDS_25_DCI (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVDS_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVDS_33_DCI (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVDS_33 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVDSEXT_25_DCI (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVDSEXT_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVDSEXT_33_DCI (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVDSEXT_33 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVPECL_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_LVPECL_33 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS_ULVDS_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFDS (O, I, IB);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
parameter IBUF_DELAY_VALUE = "0";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_AGP (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_CTT (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_BLVDS_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_DIFF_OUT (O, OB, I, IB);
parameter IOSTANDARD = "LVDS_25";
output O;
output OB;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LDT_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVDS_25_DCI (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVDS_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVDS_33_DCI (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVDS_33 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVDSEXT_25_DCI (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVDSEXT_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVDSEXT_33_DCI (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVDSEXT_33 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVPECL_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_LVPECL_33 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS_ULVDS_25 (O, I, IB);
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFGDS (O, I, IB);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
parameter IBUF_DELAY_VALUE = "0";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
input IB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_GTL_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_GTLP_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_GTLP (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_GTL (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_I_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_I_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_II_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_II_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_III_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_III_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_III_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_III (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_IV_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_IV_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_IV_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_HSTL_IV (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVCMOS12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVCMOS15 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVCMOS18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVCMOS25 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVCMOS2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVCMOS33 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVDCI_15 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVDCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVDCI_25 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVDCI_33 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVDCI_DV2_15 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVDCI_DV2_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVDCI_DV2_25 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVDCI_DV2_33 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVDS (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVPECL (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_LVTTL (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_PCI33_3 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_PCI33_5 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_PCI66_3 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_PCIX66_3 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_PCIX (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL18_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL18_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL18_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL18_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL2_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL2_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL2_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL2_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL3_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL3_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL3_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG_SSTL3_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_GTL_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_GTLP_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_GTLP (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_GTL (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUFG (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_I_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_I_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_II_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_II_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_III_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_III_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_III_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_III (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_IV_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_IV_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_IV_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_HSTL_IV (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVCMOS12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVCMOS15 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVCMOS18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVCMOS25 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVCMOS2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVCMOS33 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVDCI_15 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVDCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVDCI_25 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVDCI_33 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVDCI_DV2_15 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVDCI_DV2_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVDCI_DV2_25 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVDCI_DV2_33 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVDS (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVPECL (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_LVTTL (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_PCI33_3 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_PCI33_5 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_PCI66_3 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_PCIX66_3 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_PCIX (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL18_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL18_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL18_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL18_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL2_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL2_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL2_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL2_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL3_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL3_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL3_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF_SSTL3_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ICAP_SPARTAN3A (BUSY, O, CE, CLK, I, WRITE);
output BUSY;
output [7:0] O;
input CE;
input CLK;
input [7:0] I;
input WRITE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ICAP_VIRTEX2 (BUSY, O, CE, CLK, I, WRITE);
output BUSY;
output [7:0] O;
input CE;
input CLK;
input [7:0] I;
input WRITE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ICAP_VIRTEX4 (BUSY, O, CE, CLK, I, WRITE);
parameter ICAP_WIDTH = "X8";
output BUSY;
output [31:0] O;
input CE;
input CLK;
input [31:0] I;
input WRITE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ICAP_VIRTEX5 (BUSY, O, CE, CLK, I, WRITE);
parameter ICAP_WIDTH = "X8";
output BUSY;
output [31:0] O;
input CE;
input CLK;
input [31:0] I;
input WRITE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IDDR_2CLK (Q1, Q2, C, CB, CE, D, R, S);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter SRTYPE = "SYNC";
output Q1;
output Q2;
input C;
input CB;
input CE;
input D;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S);
parameter DDR_ALIGNMENT = "NONE";
parameter INIT_Q0 = 1'b0;
parameter INIT_Q1 = 1'b0;
parameter SRTYPE = "SYNC";
output Q0;
output Q1;
input C0;
input C1;
input CE;
input D;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IDDR (Q1, Q2, C, CE, D, R, S);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter SRTYPE = "SYNC";
output Q1;
output Q2;
input C;
input CE;
input D;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IDELAYCTRL (RDY, REFCLK, RST);
output RDY;
input REFCLK;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IDELAY (O, C, CE, I, INC, RST);
parameter IOBDELAY_TYPE = "DEFAULT";
parameter integer IOBDELAY_VALUE = 0;
output O;
input C;
input CE;
input I;
input INC;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IFDDRCPE (Q0, Q1, C0, C1, CE, CLR, D, PRE);
output Q0;
output Q1;
input C0;
input C1;
input CE;
input CLR;
input D;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IFDDRRSE (Q0, Q1, C0, C1, CE, D, R, S);
output Q0;
output Q1;
input C0;
input C1;
input CE;
input D;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ILD (Q, D, G);
output Q;
input D;
input G;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module INV (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_AGP (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_CTT (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUFDS_BLVDS_25 (O, IO, IOB, I, T);
output O;
inout IO;
inout IOB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUFDS (O, IO, IOB, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
output O;
inout IO;
inout IOB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUFE_F (O, IO, I, E);
output O;
inout IO;
input I;
input E;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUFE_S (O, IO, I, E);
output O;
inout IO;
input I;
input E;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUFE (O, IO, I, E);
output O;
inout IO;
input I;
input E;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_F_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_F_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_F_24 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_F_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_F_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_F_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_F_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_GTL_DCI (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_GTLP_DCI (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_GTLP (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_GTL (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_I_18 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_II_18 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_II_DCI_18 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_II_DCI (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_III_18 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_III (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_II (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_I (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_IV_18 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_IV_DCI_18 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_IV_DCI (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_HSTL_IV (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS12_F_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS12_F_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS12_F_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS12_F_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS12_S_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS12_S_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS12_S_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS12_S_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_F_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_F_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_F_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_F_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_F_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_F_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_S_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_S_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_S_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_S_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_S_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15_S_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS15 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_F_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_F_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_F_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_F_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_F_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_F_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_S_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_S_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_S_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_S_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_S_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18_S_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS18 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_F_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_F_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_F_24 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_F_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_F_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_F_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_F_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_S_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_S_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_S_24 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_S_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_S_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_S_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25_S_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS25 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_F_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_F_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_F_24 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_F_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_F_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_F_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_F_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_S_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_S_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_S_24 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_S_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_S_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_S_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33_S_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVCMOS33 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVDCI_15 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVDCI_18 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVDCI_25 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVDCI_33 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVDCI_DV2_15 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVDCI_DV2_18 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVDCI_DV2_25 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVDCI_DV2_33 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVDS (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVPECL (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_F_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_F_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_F_24 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_F_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_F_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_F_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_F_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_S_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_S_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_S_24 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_S_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_S_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_S_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL_S_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_LVTTL (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_PCI33_3 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_PCI33_5 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_PCI66_3 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_PCIX66_3 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_PCIX (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_S_12 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_S_16 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_S_24 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_S_2 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_S_4 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_S_6 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_S_8 (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_SSTL18_II_DCI (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_SSTL18_II (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_SSTL18_I (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_SSTL2_II_DCI (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_SSTL2_II (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_SSTL2_I (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_SSTL3_II_DCI (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_SSTL3_II (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF_SSTL3_I (O, IO, I, T);
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IOBUF (O, IO, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IBUF_DELAY_VALUE = "0";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
inout IO;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module IODELAY (DATAOUT, C, CE, DATAIN, IDATAIN, INC, ODATAIN, RST, T);
parameter DELAY_SRC = "I";
parameter HIGH_PERFORMANCE_MODE = "TRUE";
parameter IDELAY_TYPE = "DEFAULT";
parameter integer IDELAY_VALUE = 0;
parameter integer ODELAY_VALUE = 0;
parameter real REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
output DATAOUT;
input C;
input CE;
input DATAIN;
input IDATAIN;
input INC;
input ODATAIN;
input RST;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ISERDES_NODELAY (Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2);
parameter BITSLIP_ENABLE = "FALSE";
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter INIT_Q3 = 1'b0;
parameter INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter integer NUM_CE = 2;
parameter SERDES_MODE = "MASTER";
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKB;
input CLKDIV;
input D;
input OCLK;
input RST;
input SHIFTIN1;
input SHIFTIN2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ISERDES (O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKDIV, D, DLYCE, DLYINC, DLYRST, OCLK, REV, SHIFTIN1, SHIFTIN2, SR);
parameter BITSLIP_ENABLE = "FALSE";
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter INIT_Q3 = 1'b0;
parameter INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter IOBDELAY = "NONE";
parameter IOBDELAY_TYPE = "DEFAULT";
parameter integer IOBDELAY_VALUE = 0;
parameter integer NUM_CE = 2;
parameter SERDES_MODE = "MASTER";
parameter SRVAL_Q1 = 1'b0;
parameter SRVAL_Q2 = 1'b0;
parameter SRVAL_Q3 = 1'b0;
parameter SRVAL_Q4 = 1'b0;
output O;
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKDIV;
input D;
input DLYCE;
input DLYINC;
input DLYRST;
input OCLK;
input REV;
input SHIFTIN1;
input SHIFTIN2;
input SR;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module JTAGPPC440 (TCK, TDIPPC, TMS, TDOPPC);
output TCK;
output TDIPPC;
output TMS;
input TDOPPC;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module JTAGPPC (TCK, TDIPPC, TMS, TDOPPC, TDOTSPPC);
output TCK;
output TDIPPC;
output TMS;
input TDOPPC;
input TDOTSPPC;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module JTAG_SIM_SPARTAN3A (TDO, TCK, TDI, TMS);
parameter PART_NAME = "3S200A";
output TDO;
input TCK;
input TDI;
input TMS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module JTAG_SIM_VIRTEX4 (TDO, TCK, TDI, TMS);
parameter PART_NAME = "LX15";
output TDO;
input TCK;
input TDI;
input TMS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module JTAG_SIM_VIRTEX5 (TDO, TCK, TDI, TMS);
parameter PART_NAME = "LX30";
output TDO;
input TCK;
input TDI;
input TMS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module KEEPER (O);
inout O;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module KEEP (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module KEY_CLEAR (KEYCLEARB);
input KEYCLEARB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LD_1 (Q, D, G);
parameter INIT = 1'b0;
output Q;
input D;
input G;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDC_1 (Q, CLR, D, G);
parameter INIT = 1'b0;
output Q;
input CLR;
input D;
input G;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDCE_1 (Q, CLR, D, G, GE);
parameter INIT = 1'b0;
output Q;
input CLR;
input D;
input G;
input GE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDCE (Q, CLR, D, G, GE);
parameter INIT = 1'b0;
output Q;
input CLR;
input D;
input G;
input GE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDCP_1 (Q, CLR, D, G, PRE);
parameter INIT = 1'b0;
output Q;
input CLR;
input D;
input G;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDCPE_1 (Q, CLR, D, G, GE, PRE);
parameter INIT = 1'b0;
output Q;
input CLR;
input D;
input G;
input GE;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDCPE (Q, CLR, D, G, GE, PRE);
parameter INIT = 1'b0;
output Q;
input CLR;
input D;
input G;
input GE;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDCP (Q, CLR, D, G, PRE);
parameter INIT = 1'b0;
output Q;
input CLR;
input D;
input G;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDC (Q, CLR, D, G);
parameter INIT = 1'b0;
output Q;
input CLR;
input D;
input G;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDE_1 (Q, D, G, GE);
parameter INIT = 1'b0;
output Q;
input D;
input G;
input GE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDE (Q, D, G, GE);
parameter INIT = 1'b0;
output Q;
input D;
input G;
input GE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDG (Q, D, G);
parameter INIT = 1'b0;
output Q;
input D;
input G;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDP_1 (Q, D, G, PRE);
parameter INIT = 1'b1;
output Q;
input D;
input G;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDPE_1 (Q, D, G, GE, PRE);
parameter INIT = 1'b1;
output Q;
input D;
input G;
input GE;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDPE (Q, D, G, GE, PRE);
parameter INIT = 1'b1;
output Q;
input D;
input G;
input GE;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LDP (Q, D, G, PRE);
parameter INIT = 1'b1;
output Q;
input D;
input G;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LD (Q, D, G);
parameter INIT = 1'b0;
output Q;
input D;
input G;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT1_D (LO, O, I0);
parameter INIT = 2'h0;
output LO;
output O;
input I0;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT1_L (LO, I0);
parameter INIT = 2'h0;
output LO;
input I0;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT1 (O, I0);
parameter INIT = 2'h0;
output O;
input I0;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT2_D (LO, O, I0, I1);
parameter INIT = 4'h0;
output LO;
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT2_L (LO, I0, I1);
parameter INIT = 4'h0;
output LO;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT2 (O, I0, I1);
parameter INIT = 4'h0;
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT3_D (LO, O, I0, I1, I2);
parameter INIT = 8'h00;
output LO;
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT3_L (LO, I0, I1, I2);
parameter INIT = 8'h00;
output LO;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT3 (O, I0, I1, I2);
parameter INIT = 8'h00;
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT4_D (LO, O, I0, I1, I2, I3);
parameter INIT = 16'h0000;
output LO;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT4_L (LO, I0, I1, I2, I3);
parameter INIT = 16'h0000;
output LO;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT4 (O, I0, I1, I2, I3);
parameter INIT = 16'h0000;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT5_D (LO, O, I0, I1, I2, I3, I4);
parameter INIT = 32'h00000000;
output LO;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT5_L (LO, I0, I1, I2, I3, I4);
parameter INIT = 32'h00000000;
output LO;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT5 (O, I0, I1, I2, I3, I4);
parameter INIT = 32'h00000000;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT6_2 (O5, O6, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
output O5;
output O6;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT6_D (LO, O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
output LO;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT6_L (LO, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
output LO;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module LUT6 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MERGE (I);
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MIN_OFF (I);
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MULT18X18SIO (BCOUT, P, A, B, BCIN, CEA, CEB, CEP, CLK, RSTA, RSTB, RSTP);
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter B_INPUT = "DIRECT";
parameter integer PREG = 1;
output [17:0] BCOUT;
output [35:0] P;
input [17:0] A;
input [17:0] B;
input [17:0] BCIN;
input CEA;
input CEB;
input CEP;
input CLK;
input RSTA;
input RSTB;
input RSTP;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MULT18X18S (P, A, B, C, CE, R);
output [35:0] P;
input [17:0] A;
input [17:0] B;
input C;
input CE;
input R;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MULT18X18 (P, A, B);
output [35:0] P;
input [17:0] A;
input [17:0] B;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MULT_AND (LO, I0, I1);
output LO;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXCY_D (LO, O, CI, DI, S);
output LO;
output O;
input CI;
input DI;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXCY_L (LO, CI, DI, S);
output LO;
input CI;
input DI;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXCY (O, CI, DI, S);
output O;
input CI;
input DI;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF5_D (LO, O, I0, I1, S);
output LO;
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF5_L (LO, I0, I1, S);
output LO;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF5 (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF6_D (LO, O, I0, I1, S);
output LO;
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF6_L (LO, I0, I1, S);
output LO;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF6 (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF7_D (LO, O, I0, I1, S);
output LO;
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF7_L (LO, I0, I1, S);
output LO;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF7 (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF8_D (LO, O, I0, I1, S);
output LO;
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF8_L (LO, I0, I1, S);
output LO;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module MUXF8 (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND2B1 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND2B2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND3B1 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND3B2 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND3B3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND4B1 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND4B2 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND4B3 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND4B4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND5B1 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND5B2 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND5B3 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND5B4 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND5B5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NAND5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR2B1 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR2B2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR3B1 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR3B2 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR3B3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR4B1 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR4B2 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR4B3 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR4B4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR5B1 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR5B2 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR5B3 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR5B4 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR5B5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module NOR5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_AGP (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_CTT (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS_BLVDS_25 (O, OB, I);
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS_LDT_25 (O, OB, I);
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS_LVDS_25 (O, OB, I);
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS_LVDS_33 (O, OB, I);
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS_LVDSEXT_25 (O, OB, I);
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS_LVDSEXT_33 (O, OB, I);
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS_LVPECL_25 (O, OB, I);
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS_LVPECL_33 (O, OB, I);
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS_ULVDS_25 (O, OB, I);
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFDS (O, OB, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
output O;
output OB;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFE (O, E, I);
output O;
input E;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_F_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_F_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_F_24 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_F_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_F_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_F_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_F_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_GTL_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_GTLP_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_GTLP (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_GTL (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_I_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_I_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_II_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_II_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_III_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_III_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_III_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_III (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_IV_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_IV_DCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_IV_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_HSTL_IV (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS12_F_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS12_F_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS12_F_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS12_F_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS12_S_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS12_S_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS12_S_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS12_S_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_F_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_F_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_F_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_F_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_F_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_F_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_S_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_S_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_S_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_S_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_S_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15_S_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS15 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_F_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_F_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_F_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_F_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_F_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_F_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_S_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_S_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_S_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_S_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_S_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18_S_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_F_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_F_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_F_24 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_F_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_F_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_F_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_F_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_S_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_S_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_S_24 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_S_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_S_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_S_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25_S_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS25 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_F_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_F_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_F_24 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_F_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_F_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_F_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_F_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_S_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_S_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_S_24 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_S_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_S_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_S_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33_S_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVCMOS33 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVDCI_15 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVDCI_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVDCI_25 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVDCI_33 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVDCI_DV2_15 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVDCI_DV2_18 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVDCI_DV2_25 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVDCI_DV2_33 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVDS (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVPECL (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_F_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_F_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_F_24 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_F_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_F_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_F_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_F_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_S_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_S_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_S_24 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_S_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_S_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_S_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL_S_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_LVTTL (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_PCI33_3 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_PCI33_5 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_PCI66_3 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_PCIX66_3 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_PCIX (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_S_12 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_S_16 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_S_24 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_S_2 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_S_4 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_S_6 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_S_8 (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL18_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL18_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL18_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL18_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL2_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL2_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL2_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL2_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL3_I_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL3_II_DCI (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL3_II (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF_SSTL3_I (O, I);
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_AGP (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_CTT (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS_BLVDS_25 (O, OB, I, T);
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS_LDT_25 (O, OB, I, T);
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS_LVDS_25 (O, OB, I, T);
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS_LVDS_33 (O, OB, I, T);
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS_LVDSEXT_25 (O, OB, I, T);
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS_LVDSEXT_33 (O, OB, I, T);
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS_LVPECL_25 (O, OB, I, T);
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS_LVPECL_33 (O, OB, I, T);
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS_ULVDS_25 (O, OB, I, T);
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFTDS (O, OB, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
output O;
output OB;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_F_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_F_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_F_24 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_F_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_F_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_F_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_F_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_GTL_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_GTLP_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_GTLP (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_GTL (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_I_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_I_DCI_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_I_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_II_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_II_DCI_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_II_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_III_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_III_DCI_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_III_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_III (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_II (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_I (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_IV_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_IV_DCI_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_IV_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_HSTL_IV (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS12_F_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS12_F_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS12_F_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS12_F_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS12_S_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS12_S_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS12_S_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS12_S_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_F_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_F_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_F_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_F_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_F_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_F_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_S_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_S_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_S_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_S_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_S_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15_S_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS15 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_F_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_F_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_F_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_F_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_F_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_F_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_S_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_S_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_S_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_S_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_S_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18_S_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_F_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_F_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_F_24 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_F_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_F_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_F_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_F_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_S_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_S_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_S_24 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_S_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_S_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_S_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25_S_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS25 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_F_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_F_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_F_24 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_F_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_F_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_F_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_F_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_S_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_S_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_S_24 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_S_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_S_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_S_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33_S_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVCMOS33 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVDCI_15 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVDCI_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVDCI_25 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVDCI_33 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVDCI_DV2_15 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVDCI_DV2_18 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVDCI_DV2_25 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVDCI_DV2_33 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVDS (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVPECL (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_F_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_F_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_F_24 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_F_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_F_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_F_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_F_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_S_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_S_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_S_24 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_S_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_S_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_S_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL_S_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_LVTTL (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_PCI33_3 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_PCI33_5 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_PCI66_3 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_PCIX66_3 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_PCIX (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_S_12 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_S_16 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_S_24 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_S_2 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_S_4 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_S_6 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_S_8 (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL18_I_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL18_II_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL18_II (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL18_I (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL2_I_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL2_II_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL2_II (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL2_I (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL3_I_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL3_II_DCI (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL3_II (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT_SSTL3_I (O, I, T);
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUFT (O, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
input I;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ODDR2 (Q, C0, C1, CE, D0, D1, R, S);
parameter DDR_ALIGNMENT = "NONE";
parameter INIT = 1'b0;
parameter SRTYPE = "SYNC";
output Q;
input C0;
input C1;
input CE;
input D0;
input D1;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ODDR (Q, C, CE, D1, D2, R, S);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT = 1'b0;
parameter SRTYPE = "SYNC";
output Q;
input C;
input CE;
input D1;
input D2;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OFDDRCPE (Q, C0, C1, CE, CLR, D0, D1, PRE);
output Q;
input C0;
input C1;
input CE;
input CLR;
input D0;
input D1;
input PRE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OFDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
output Q;
input C0;
input C1;
input CE;
input D0;
input D1;
input R;
input S;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OFDDRTCPE (O, C0, C1, CE, CLR, D0, D1, PRE, T);
output O;
input C0;
input C1;
input CE;
input CLR;
input D0;
input D1;
input PRE;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OFDDRTRSE (O, C0, C1, CE, D0, D1, R, S, T);
output O;
input C0;
input C1;
input CE;
input D0;
input D1;
input R;
input S;
input T;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OPT_OFF (I);
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OPT_UIM (I);
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR2B1 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR2B2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR3B1 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR3B2 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR3B3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR4B1 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR4B2 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR4B3 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR4B4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR5B1 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR5B2 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR5B3 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR5B4 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR5B5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR6 (O, I0, I1, I2, I3, I4, I5);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR7 (O, I0, I1, I2, I3, I4, I5, I6);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OR8 (O, I0, I1, I2, I3, I4, I5, I6, I7);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ORCY (O, CI, I);
output O;
input CI;
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module OSERDES (OQ, SHIFTOUT1, SHIFTOUT2, TQ, CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4, TCE);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter integer DATA_WIDTH = 4;
parameter INIT_OQ = 1'b0;
parameter INIT_TQ = 1'b0;
parameter SERDES_MODE = "MASTER";
parameter SRVAL_OQ = 1'b0;
parameter SRVAL_TQ = 1'b0;
parameter integer TRISTATE_WIDTH = 4;
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TQ;
input CLK;
input CLKDIV;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
input OCE;
input REV;
input SHIFTIN1;
input SHIFTIN2;
input SR;
input T1;
input T2;
input T3;
input T4;
input TCE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PCIE_EP (BUSMASTERENABLE, CRMDOHOTRESETN, CRMPWRSOFTRESETN, DLLTXPMDLLPOUTSTANDING, INTERRUPTDISABLE, IOSPACEENABLE, L0CFGLOOPBACKACK, L0COMPLETERID, L0DLLERRORVECTOR, L0DLLRXACKOUTSTANDING, L0DLLTXNONFCOUTSTANDING, L0DLLTXOUTSTANDING, L0DLLVCSTATUS, L0DLUPDOWN, L0FIRSTCFGWRITEOCCURRED, L0LTSSMSTATE, L0MACENTEREDL0, L0MACLINKTRAINING, L0MACLINKUP, L0MACNEGOTIATEDLINKWIDTH, L0MACNEWSTATEACK, L0MACRXL0SSTATE, L0MSIENABLE0, L0MULTIMSGEN0, L0PMEACK, L0PMEEN, L0PMEREQOUT, L0PWRL1STATE, L0PWRL23READYSTATE, L0PWRSTATE0, L0PWRTURNOFFREQ, L0PWRTXL0SSTATE, L0RXDLLPM, L0RXDLLPMTYPE, L0RXMACLINKERROR, L0STATSCFGOTHERRECEIVED, L0STATSCFGOTHERTRANSMITTED, L0STATSCFGRECEIVED, L0STATSCFGTRANSMITTED, L0STATSDLLPRECEIVED, L0STATSDLLPTRANSMITTED, L0STATSOSRECEIVED, L0STATSOSTRANSMITTED, L0STATSTLPRECEIVED, L0STATSTLPTRANSMITTED, L0UNLOCKRECEIVED, LLKRXCHCOMPLETIONAVAILABLEN, LLKRXCHNONPOSTEDAVAILABLEN, LLKRXCHPOSTEDAVAILABLEN, LLKRXDATA, LLKRXEOFN, LLKRXEOPN, LLKRXPREFERREDTYPE, LLKRXSOFN, LLKRXSOPN, LLKRXSRCLASTREQN, LLKRXSRCRDYN, LLKRXVALIDN, LLKTCSTATUS, LLKTXCHANSPACE, LLKTXCHCOMPLETIONREADYN, LLKTXCHNONPOSTEDREADYN, LLKTXCHPOSTEDREADYN, LLKTXCONFIGREADYN, LLKTXDSTRDYN, MAXPAYLOADSIZE, MAXREADREQUESTSIZE, MEMSPACEENABLE, MGMTPSO, MGMTRDATA, MGMTSTATSCREDIT, MIMDLLBRADD, MIMDLLBREN, MIMDLLBWADD, MIMDLLBWDATA, MIMDLLBWEN, MIMRXBRADD, MIMRXBREN, MIMRXBWADD, MIMRXBWDATA, MIMRXBWEN, MIMTXBRADD, MIMTXBREN, MIMTXBWADD, MIMTXBWDATA, MIMTXBWEN, PARITYERRORRESPONSE, PIPEDESKEWLANESL0, PIPEDESKEWLANESL1, PIPEDESKEWLANESL2, PIPEDESKEWLANESL3, PIPEDESKEWLANESL4, PIPEDESKEWLANESL5, PIPEDESKEWLANESL6, PIPEDESKEWLANESL7, PIPEPOWERDOWNL0, PIPEPOWERDOWNL1, PIPEPOWERDOWNL2, PIPEPOWERDOWNL3, PIPEPOWERDOWNL4, PIPEPOWERDOWNL5, PIPEPOWERDOWNL6, PIPEPOWERDOWNL7, PIPERESETL0, PIPERESETL1, PIPERESETL2, PIPERESETL3, PIPERESETL4, PIPERESETL5, PIPERESETL6, PIPERESETL7, PIPERXPOLARITYL0, PIPERXPOLARITYL1, PIPERXPOLARITYL2, PIPERXPOLARITYL3, PIPERXPOLARITYL4, PIPERXPOLARITYL5, PIPERXPOLARITYL6, PIPERXPOLARITYL7, PIPETXCOMPLIANCEL0, PIPETXCOMPLIANCEL1, PIPETXCOMPLIANCEL2, PIPETXCOMPLIANCEL3, PIPETXCOMPLIANCEL4, PIPETXCOMPLIANCEL5, PIPETXCOMPLIANCEL6, PIPETXCOMPLIANCEL7, PIPETXDATAKL0, PIPETXDATAKL1, PIPETXDATAKL2, PIPETXDATAKL3, PIPETXDATAKL4, PIPETXDATAKL5, PIPETXDATAKL6, PIPETXDATAKL7, PIPETXDATAL0, PIPETXDATAL1, PIPETXDATAL2, PIPETXDATAL3, PIPETXDATAL4, PIPETXDATAL5, PIPETXDATAL6, PIPETXDATAL7, PIPETXDETECTRXLOOPBACKL0, PIPETXDETECTRXLOOPBACKL1, PIPETXDETECTRXLOOPBACKL2, PIPETXDETECTRXLOOPBACKL3, PIPETXDETECTRXLOOPBACKL4, PIPETXDETECTRXLOOPBACKL5, PIPETXDETECTRXLOOPBACKL6, PIPETXDETECTRXLOOPBACKL7, PIPETXELECIDLEL0, PIPETXELECIDLEL1, PIPETXELECIDLEL2, PIPETXELECIDLEL3, PIPETXELECIDLEL4, PIPETXELECIDLEL5, PIPETXELECIDLEL6, PIPETXELECIDLEL7, SERRENABLE, URREPORTINGENABLE, AUXPOWER, COMPLIANCEAVOID, CRMCORECLK, CRMCORECLKDLO, CRMCORECLKRXO, CRMCORECLKTXO, CRMLINKRSTN, CRMMACRSTN, CRMMGMTRSTN, CRMNVRSTN, CRMURSTN, CRMUSERCFGRSTN, CRMUSERCLK, CRMUSERCLKRXO, CRMUSERCLKTXO, L0CFGDISABLESCRAMBLE, L0CFGLOOPBACKMASTER, L0LEGACYINTFUNCT0, L0MSIREQUEST0, L0PACKETHEADERFROMUSER, L0PMEREQIN, L0SETCOMPLETERABORTERROR, L0SETCOMPLETIONTIMEOUTCORRERROR, L0SETCOMPLETIONTIMEOUTUNCORRERROR, L0SETDETECTEDCORRERROR, L0SETDETECTEDFATALERROR, L0SETDETECTEDNONFATALERROR, L0SETUNEXPECTEDCOMPLETIONCORRERROR, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR, L0SETUNSUPPORTEDREQUESTOTHERERROR, L0SETUSERDETECTEDPARITYERROR, L0SETUSERMASTERDATAPARITY, L0SETUSERRECEIVEDMASTERABORT, L0SETUSERRECEIVEDTARGETABORT, L0SETUSERSIGNALLEDTARGETABORT, L0SETUSERSYSTEMERROR, L0TRANSACTIONSPENDING, LLKRXCHFIFO, LLKRXCHTC, LLKRXDSTCONTREQN, LLKRXDSTREQN, LLKTXCHFIFO, LLKTXCHTC, LLKTXDATA, LLKTXENABLEN, LLKTXEOFN, LLKTXEOPN, LLKTXSOFN, LLKTXSOPN, LLKTXSRCDSCN, LLKTXSRCRDYN, MGMTADDR, MGMTBWREN, MGMTRDEN, MGMTSTATSCREDITSEL, MGMTWDATA, MGMTWREN, MIMDLLBRDATA, MIMRXBRDATA, MIMTXBRDATA, PIPEPHYSTATUSL0, PIPEPHYSTATUSL1, PIPEPHYSTATUSL2, PIPEPHYSTATUSL3, PIPEPHYSTATUSL4, PIPEPHYSTATUSL5, PIPEPHYSTATUSL6, PIPEPHYSTATUSL7, PIPERXCHANISALIGNEDL0, PIPERXCHANISALIGNEDL1, PIPERXCHANISALIGNEDL2, PIPERXCHANISALIGNEDL3, PIPERXCHANISALIGNEDL4, PIPERXCHANISALIGNEDL5, PIPERXCHANISALIGNEDL6, PIPERXCHANISALIGNEDL7, PIPERXDATAKL0, PIPERXDATAKL1, PIPERXDATAKL2, PIPERXDATAKL3, PIPERXDATAKL4, PIPERXDATAKL5, PIPERXDATAKL6, PIPERXDATAKL7, PIPERXDATAL0, PIPERXDATAL1, PIPERXDATAL2, PIPERXDATAL3, PIPERXDATAL4, PIPERXDATAL5, PIPERXDATAL6, PIPERXDATAL7, PIPERXELECIDLEL0, PIPERXELECIDLEL1, PIPERXELECIDLEL2, PIPERXELECIDLEL3, PIPERXELECIDLEL4, PIPERXELECIDLEL5, PIPERXELECIDLEL6, PIPERXELECIDLEL7, PIPERXSTATUSL0, PIPERXSTATUSL1, PIPERXSTATUSL2, PIPERXSTATUSL3, PIPERXSTATUSL4, PIPERXSTATUSL5, PIPERXSTATUSL6, PIPERXSTATUSL7, PIPERXVALIDL0, PIPERXVALIDL1, PIPERXVALIDL2, PIPERXVALIDL3, PIPERXVALIDL4, PIPERXVALIDL5, PIPERXVALIDL6, PIPERXVALIDL7);
parameter BAR0EXIST = "TRUE";
parameter BAR0PREFETCHABLE = "TRUE";
parameter BAR1EXIST = "FALSE";
parameter BAR1PREFETCHABLE = "FALSE";
parameter BAR2EXIST = "FALSE";
parameter BAR2PREFETCHABLE = "FALSE";
parameter BAR3EXIST = "FALSE";
parameter BAR3PREFETCHABLE = "FALSE";
parameter BAR4EXIST = "FALSE";
parameter BAR4PREFETCHABLE = "FALSE";
parameter BAR5EXIST = "FALSE";
parameter BAR5PREFETCHABLE = "FALSE";
parameter CLKDIVIDED = "FALSE";
parameter INFINITECOMPLETIONS = "TRUE";
parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE";
parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE";
parameter PMCAPABILITYD1SUPPORT = "FALSE";
parameter PMCAPABILITYD2SUPPORT = "FALSE";
parameter PMCAPABILITYDSI = "TRUE";
parameter RESETMODE = "FALSE";
parameter [10:0] VC0TOTALCREDITSCD = 11'h0;
parameter [10:0] VC0TOTALCREDITSPD = 11'h34;
parameter [10:0] VC1TOTALCREDITSCD = 11'h0;
parameter [10:0] VC1TOTALCREDITSPD = 11'h0;
parameter [11:0] AERBASEPTR = 12'h110;
parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138;
parameter [11:0] DSNBASEPTR = 12'h148;
parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154;
parameter [11:0] MSIBASEPTR = 12'h48;
parameter [11:0] PBBASEPTR = 12'h138;
parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148;
parameter [11:0] PMBASEPTR = 12'h40;
parameter [11:0] RETRYRAMSIZE = 12'h9;
parameter [11:0] VCBASEPTR = 12'h154;
parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0;
parameter [12:0] VC0RXFIFOBASEC = 13'h98;
parameter [12:0] VC0RXFIFOBASENP = 13'h80;
parameter [12:0] VC0RXFIFOBASEP = 13'h0;
parameter [12:0] VC0RXFIFOLIMITC = 13'h117;
parameter [12:0] VC0RXFIFOLIMITNP = 13'h97;
parameter [12:0] VC0RXFIFOLIMITP = 13'h7f;
parameter [12:0] VC0TXFIFOBASEC = 13'h98;
parameter [12:0] VC0TXFIFOBASENP = 13'h80;
parameter [12:0] VC0TXFIFOBASEP = 13'h0;
parameter [12:0] VC0TXFIFOLIMITC = 13'h117;
parameter [12:0] VC0TXFIFOLIMITNP = 13'h97;
parameter [12:0] VC0TXFIFOLIMITP = 13'h7f;
parameter [12:0] VC1RXFIFOBASEC = 13'h118;
parameter [12:0] VC1RXFIFOBASENP = 13'h118;
parameter [12:0] VC1RXFIFOBASEP = 13'h118;
parameter [12:0] VC1RXFIFOLIMITC = 13'h118;
parameter [12:0] VC1RXFIFOLIMITNP = 13'h118;
parameter [12:0] VC1RXFIFOLIMITP = 13'h118;
parameter [12:0] VC1TXFIFOBASEC = 13'h118;
parameter [12:0] VC1TXFIFOBASENP = 13'h118;
parameter [12:0] VC1TXFIFOBASEP = 13'h118;
parameter [12:0] VC1TXFIFOLIMITC = 13'h118;
parameter [12:0] VC1TXFIFOLIMITNP = 13'h118;
parameter [12:0] VC1TXFIFOLIMITP = 13'h118;
parameter [15:0] DEVICEID = 16'h5050;
parameter [15:0] SUBSYSTEMID = 16'h5050;
parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE;
parameter [15:0] VENDORID = 16'h10EE;
parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1;
parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0;
parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0;
parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0;
parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0;
parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0;
parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0;
parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0;
parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0;
parameter [23:0] CLASSCODE = 24'h058000;
parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0;
parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0;
parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0;
parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0;
parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0;
parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0;
parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0;
parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0;
parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0;
parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0;
parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0;
parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0;
parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0;
parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0;
parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0;
parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0;
parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0;
parameter [31:0] CARDBUSCISPOINTER = 32'h0;
parameter [3:0] XPDEVICEPORTTYPE = 4'h0;
parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0;
parameter [5:0] BAR0MASKWIDTH = 6'h14;
parameter [5:0] BAR1MASKWIDTH = 6'h0;
parameter [5:0] BAR2MASKWIDTH = 6'h0;
parameter [5:0] BAR3MASKWIDTH = 6'h0;
parameter [5:0] BAR4MASKWIDTH = 6'h0;
parameter [5:0] BAR5MASKWIDTH = 6'h0;
parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01;
parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35;
parameter [6:0] VC0TOTALCREDITSCH = 7'h0;
parameter [6:0] VC0TOTALCREDITSNPH = 7'h08;
parameter [6:0] VC0TOTALCREDITSPH = 7'h08;
parameter [6:0] VC1TOTALCREDITSCH = 7'h0;
parameter [6:0] VC1TOTALCREDITSNPH = 7'h0;
parameter [6:0] VC1TOTALCREDITSPH = 7'h0;
parameter [7:0] ACTIVELANESIN = 8'h1;
parameter [7:0] CAPABILITIESPOINTER = 8'h40;
parameter [7:0] INTERRUPTPIN = 8'h0;
parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60;
parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0;
parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0;
parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0;
parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0;
parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0;
parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60;
parameter [7:0] PMDATA0 = 8'h0;
parameter [7:0] PMDATA1 = 8'h0;
parameter [7:0] PMDATA2 = 8'h0;
parameter [7:0] PMDATA3 = 8'h0;
parameter [7:0] PMDATA4 = 8'h0;
parameter [7:0] PMDATA5 = 8'h0;
parameter [7:0] PMDATA6 = 8'h0;
parameter [7:0] PMDATA7 = 8'h0;
parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0;
parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0;
parameter [7:0] REVISIONID = 8'h0;
parameter [7:0] XPBASEPTR = 8'h60;
parameter integer BAR0ADDRWIDTH = 0;
parameter integer BAR0IOMEMN = 0;
parameter integer BAR1ADDRWIDTH = 0;
parameter integer BAR1IOMEMN = 0;
parameter integer BAR2ADDRWIDTH = 0;
parameter integer BAR2IOMEMN = 0;
parameter integer BAR3ADDRWIDTH = 0;
parameter integer BAR3IOMEMN = 0;
parameter integer BAR4ADDRWIDTH = 0;
parameter integer BAR4IOMEMN = 0;
parameter integer BAR5IOMEMN = 0;
parameter integer L0SEXITLATENCY = 7;
parameter integer L0SEXITLATENCYCOMCLK = 7;
parameter integer L1EXITLATENCY = 7;
parameter integer L1EXITLATENCYCOMCLK = 7;
parameter integer LOWPRIORITYVCCOUNT = 0;
parameter integer PMDATASCALE0 = 0;
parameter integer PMDATASCALE1 = 0;
parameter integer PMDATASCALE2 = 0;
parameter integer PMDATASCALE3 = 0;
parameter integer PMDATASCALE4 = 0;
parameter integer PMDATASCALE5 = 0;
parameter integer PMDATASCALE6 = 0;
parameter integer PMDATASCALE7 = 0;
parameter integer RETRYRAMREADLATENCY = 3;
parameter integer RETRYRAMWRITELATENCY = 1;
parameter integer TLRAMREADLATENCY = 3;
parameter integer TLRAMWRITELATENCY = 1;
parameter integer TXTSNFTS = 255;
parameter integer TXTSNFTSCOMCLK = 255;
parameter integer XPMAXPAYLOAD = 0;
output BUSMASTERENABLE;
output CRMDOHOTRESETN;
output CRMPWRSOFTRESETN;
output DLLTXPMDLLPOUTSTANDING;
output INTERRUPTDISABLE;
output IOSPACEENABLE;
output L0CFGLOOPBACKACK;
output [12:0] L0COMPLETERID;
output [6:0] L0DLLERRORVECTOR;
output L0DLLRXACKOUTSTANDING;
output L0DLLTXNONFCOUTSTANDING;
output L0DLLTXOUTSTANDING;
output [7:0] L0DLLVCSTATUS;
output [7:0] L0DLUPDOWN;
output L0FIRSTCFGWRITEOCCURRED;
output [3:0] L0LTSSMSTATE;
output L0MACENTEREDL0;
output L0MACLINKTRAINING;
output L0MACLINKUP;
output [3:0] L0MACNEGOTIATEDLINKWIDTH;
output L0MACNEWSTATEACK;
output L0MACRXL0SSTATE;
output L0MSIENABLE0;
output [2:0] L0MULTIMSGEN0;
output L0PMEACK;
output L0PMEEN;
output L0PMEREQOUT;
output L0PWRL1STATE;
output L0PWRL23READYSTATE;
output [1:0] L0PWRSTATE0;
output L0PWRTURNOFFREQ;
output L0PWRTXL0SSTATE;
output L0RXDLLPM;
output [2:0] L0RXDLLPMTYPE;
output [1:0] L0RXMACLINKERROR;
output L0STATSCFGOTHERRECEIVED;
output L0STATSCFGOTHERTRANSMITTED;
output L0STATSCFGRECEIVED;
output L0STATSCFGTRANSMITTED;
output L0STATSDLLPRECEIVED;
output L0STATSDLLPTRANSMITTED;
output L0STATSOSRECEIVED;
output L0STATSOSTRANSMITTED;
output L0STATSTLPRECEIVED;
output L0STATSTLPTRANSMITTED;
output L0UNLOCKRECEIVED;
output [7:0] LLKRXCHCOMPLETIONAVAILABLEN;
output [7:0] LLKRXCHNONPOSTEDAVAILABLEN;
output [7:0] LLKRXCHPOSTEDAVAILABLEN;
output [63:0] LLKRXDATA;
output LLKRXEOFN;
output LLKRXEOPN;
output [15:0] LLKRXPREFERREDTYPE;
output LLKRXSOFN;
output LLKRXSOPN;
output LLKRXSRCLASTREQN;
output LLKRXSRCRDYN;
output [1:0] LLKRXVALIDN;
output [7:0] LLKTCSTATUS;
output [9:0] LLKTXCHANSPACE;
output [7:0] LLKTXCHCOMPLETIONREADYN;
output [7:0] LLKTXCHNONPOSTEDREADYN;
output [7:0] LLKTXCHPOSTEDREADYN;
output LLKTXCONFIGREADYN;
output LLKTXDSTRDYN;
output [2:0] MAXPAYLOADSIZE;
output [2:0] MAXREADREQUESTSIZE;
output MEMSPACEENABLE;
output [16:0] MGMTPSO;
output [31:0] MGMTRDATA;
output [11:0] MGMTSTATSCREDIT;
output [11:0] MIMDLLBRADD;
output MIMDLLBREN;
output [11:0] MIMDLLBWADD;
output [63:0] MIMDLLBWDATA;
output MIMDLLBWEN;
output [12:0] MIMRXBRADD;
output MIMRXBREN;
output [12:0] MIMRXBWADD;
output [63:0] MIMRXBWDATA;
output MIMRXBWEN;
output [12:0] MIMTXBRADD;
output MIMTXBREN;
output [12:0] MIMTXBWADD;
output [63:0] MIMTXBWDATA;
output MIMTXBWEN;
output PARITYERRORRESPONSE;
output PIPEDESKEWLANESL0;
output PIPEDESKEWLANESL1;
output PIPEDESKEWLANESL2;
output PIPEDESKEWLANESL3;
output PIPEDESKEWLANESL4;
output PIPEDESKEWLANESL5;
output PIPEDESKEWLANESL6;
output PIPEDESKEWLANESL7;
output [1:0] PIPEPOWERDOWNL0;
output [1:0] PIPEPOWERDOWNL1;
output [1:0] PIPEPOWERDOWNL2;
output [1:0] PIPEPOWERDOWNL3;
output [1:0] PIPEPOWERDOWNL4;
output [1:0] PIPEPOWERDOWNL5;
output [1:0] PIPEPOWERDOWNL6;
output [1:0] PIPEPOWERDOWNL7;
output PIPERESETL0;
output PIPERESETL1;
output PIPERESETL2;
output PIPERESETL3;
output PIPERESETL4;
output PIPERESETL5;
output PIPERESETL6;
output PIPERESETL7;
output PIPERXPOLARITYL0;
output PIPERXPOLARITYL1;
output PIPERXPOLARITYL2;
output PIPERXPOLARITYL3;
output PIPERXPOLARITYL4;
output PIPERXPOLARITYL5;
output PIPERXPOLARITYL6;
output PIPERXPOLARITYL7;
output PIPETXCOMPLIANCEL0;
output PIPETXCOMPLIANCEL1;
output PIPETXCOMPLIANCEL2;
output PIPETXCOMPLIANCEL3;
output PIPETXCOMPLIANCEL4;
output PIPETXCOMPLIANCEL5;
output PIPETXCOMPLIANCEL6;
output PIPETXCOMPLIANCEL7;
output PIPETXDATAKL0;
output PIPETXDATAKL1;
output PIPETXDATAKL2;
output PIPETXDATAKL3;
output PIPETXDATAKL4;
output PIPETXDATAKL5;
output PIPETXDATAKL6;
output PIPETXDATAKL7;
output [7:0] PIPETXDATAL0;
output [7:0] PIPETXDATAL1;
output [7:0] PIPETXDATAL2;
output [7:0] PIPETXDATAL3;
output [7:0] PIPETXDATAL4;
output [7:0] PIPETXDATAL5;
output [7:0] PIPETXDATAL6;
output [7:0] PIPETXDATAL7;
output PIPETXDETECTRXLOOPBACKL0;
output PIPETXDETECTRXLOOPBACKL1;
output PIPETXDETECTRXLOOPBACKL2;
output PIPETXDETECTRXLOOPBACKL3;
output PIPETXDETECTRXLOOPBACKL4;
output PIPETXDETECTRXLOOPBACKL5;
output PIPETXDETECTRXLOOPBACKL6;
output PIPETXDETECTRXLOOPBACKL7;
output PIPETXELECIDLEL0;
output PIPETXELECIDLEL1;
output PIPETXELECIDLEL2;
output PIPETXELECIDLEL3;
output PIPETXELECIDLEL4;
output PIPETXELECIDLEL5;
output PIPETXELECIDLEL6;
output PIPETXELECIDLEL7;
output SERRENABLE;
output URREPORTINGENABLE;
input AUXPOWER;
input COMPLIANCEAVOID;
input CRMCORECLK;
input CRMCORECLKDLO;
input CRMCORECLKRXO;
input CRMCORECLKTXO;
input CRMLINKRSTN;
input CRMMACRSTN;
input CRMMGMTRSTN;
input CRMNVRSTN;
input CRMURSTN;
input CRMUSERCFGRSTN;
input CRMUSERCLK;
input CRMUSERCLKRXO;
input CRMUSERCLKTXO;
input L0CFGDISABLESCRAMBLE;
input L0CFGLOOPBACKMASTER;
input L0LEGACYINTFUNCT0;
input [3:0] L0MSIREQUEST0;
input [127:0] L0PACKETHEADERFROMUSER;
input L0PMEREQIN;
input L0SETCOMPLETERABORTERROR;
input L0SETCOMPLETIONTIMEOUTCORRERROR;
input L0SETCOMPLETIONTIMEOUTUNCORRERROR;
input L0SETDETECTEDCORRERROR;
input L0SETDETECTEDFATALERROR;
input L0SETDETECTEDNONFATALERROR;
input L0SETUNEXPECTEDCOMPLETIONCORRERROR;
input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR;
input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR;
input L0SETUNSUPPORTEDREQUESTOTHERERROR;
input L0SETUSERDETECTEDPARITYERROR;
input L0SETUSERMASTERDATAPARITY;
input L0SETUSERRECEIVEDMASTERABORT;
input L0SETUSERRECEIVEDTARGETABORT;
input L0SETUSERSIGNALLEDTARGETABORT;
input L0SETUSERSYSTEMERROR;
input L0TRANSACTIONSPENDING;
input [1:0] LLKRXCHFIFO;
input [2:0] LLKRXCHTC;
input LLKRXDSTCONTREQN;
input LLKRXDSTREQN;
input [1:0] LLKTXCHFIFO;
input [2:0] LLKTXCHTC;
input [63:0] LLKTXDATA;
input [1:0] LLKTXENABLEN;
input LLKTXEOFN;
input LLKTXEOPN;
input LLKTXSOFN;
input LLKTXSOPN;
input LLKTXSRCDSCN;
input LLKTXSRCRDYN;
input [10:0] MGMTADDR;
input [3:0] MGMTBWREN;
input MGMTRDEN;
input [6:0] MGMTSTATSCREDITSEL;
input [31:0] MGMTWDATA;
input MGMTWREN;
input [63:0] MIMDLLBRDATA;
input [63:0] MIMRXBRDATA;
input [63:0] MIMTXBRDATA;
input PIPEPHYSTATUSL0;
input PIPEPHYSTATUSL1;
input PIPEPHYSTATUSL2;
input PIPEPHYSTATUSL3;
input PIPEPHYSTATUSL4;
input PIPEPHYSTATUSL5;
input PIPEPHYSTATUSL6;
input PIPEPHYSTATUSL7;
input PIPERXCHANISALIGNEDL0;
input PIPERXCHANISALIGNEDL1;
input PIPERXCHANISALIGNEDL2;
input PIPERXCHANISALIGNEDL3;
input PIPERXCHANISALIGNEDL4;
input PIPERXCHANISALIGNEDL5;
input PIPERXCHANISALIGNEDL6;
input PIPERXCHANISALIGNEDL7;
input PIPERXDATAKL0;
input PIPERXDATAKL1;
input PIPERXDATAKL2;
input PIPERXDATAKL3;
input PIPERXDATAKL4;
input PIPERXDATAKL5;
input PIPERXDATAKL6;
input PIPERXDATAKL7;
input [7:0] PIPERXDATAL0;
input [7:0] PIPERXDATAL1;
input [7:0] PIPERXDATAL2;
input [7:0] PIPERXDATAL3;
input [7:0] PIPERXDATAL4;
input [7:0] PIPERXDATAL5;
input [7:0] PIPERXDATAL6;
input [7:0] PIPERXDATAL7;
input PIPERXELECIDLEL0;
input PIPERXELECIDLEL1;
input PIPERXELECIDLEL2;
input PIPERXELECIDLEL3;
input PIPERXELECIDLEL4;
input PIPERXELECIDLEL5;
input PIPERXELECIDLEL6;
input PIPERXELECIDLEL7;
input [2:0] PIPERXSTATUSL0;
input [2:0] PIPERXSTATUSL1;
input [2:0] PIPERXSTATUSL2;
input [2:0] PIPERXSTATUSL3;
input [2:0] PIPERXSTATUSL4;
input [2:0] PIPERXSTATUSL5;
input [2:0] PIPERXSTATUSL6;
input [2:0] PIPERXSTATUSL7;
input PIPERXVALIDL0;
input PIPERXVALIDL1;
input PIPERXVALIDL2;
input PIPERXVALIDL3;
input PIPERXVALIDL4;
input PIPERXVALIDL5;
input PIPERXVALIDL6;
input PIPERXVALIDL7;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PCIE_INTERNAL_1_1 (BUSMASTERENABLE, CRMDOHOTRESETN, CRMPWRSOFTRESETN, CRMRXHOTRESETN, DLLTXPMDLLPOUTSTANDING, INTERRUPTDISABLE, IOSPACEENABLE, L0ASAUTONOMOUSINITCOMPLETED, L0ATTENTIONINDICATORCONTROL, L0CFGLOOPBACKACK, L0COMPLETERID, L0CORRERRMSGRCVD, L0DLLASRXSTATE, L0DLLASTXSTATE, L0DLLERRORVECTOR, L0DLLRXACKOUTSTANDING, L0DLLTXNONFCOUTSTANDING, L0DLLTXOUTSTANDING, L0DLLVCSTATUS, L0DLUPDOWN, L0ERRMSGREQID, L0FATALERRMSGRCVD, L0FIRSTCFGWRITEOCCURRED, L0FWDCORRERROUT, L0FWDFATALERROUT, L0FWDNONFATALERROUT, L0LTSSMSTATE, L0MACENTEREDL0, L0MACLINKTRAINING, L0MACLINKUP, L0MACNEGOTIATEDLINKWIDTH, L0MACNEWSTATEACK, L0MACRXL0SSTATE, L0MACUPSTREAMDOWNSTREAM, L0MCFOUND, L0MSIENABLE0, L0MULTIMSGEN0, L0NONFATALERRMSGRCVD, L0PMEACK, L0PMEEN, L0PMEREQOUT, L0POWERCONTROLLERCONTROL, L0POWERINDICATORCONTROL, L0PWRINHIBITTRANSFERS, L0PWRL1STATE, L0PWRL23READYDEVICE, L0PWRL23READYSTATE, L0PWRSTATE0, L0PWRTURNOFFREQ, L0PWRTXL0SSTATE, L0RECEIVEDASSERTINTALEGACYINT, L0RECEIVEDASSERTINTBLEGACYINT, L0RECEIVEDASSERTINTCLEGACYINT, L0RECEIVEDASSERTINTDLEGACYINT, L0RECEIVEDDEASSERTINTALEGACYINT, L0RECEIVEDDEASSERTINTBLEGACYINT, L0RECEIVEDDEASSERTINTCLEGACYINT, L0RECEIVEDDEASSERTINTDLEGACYINT, L0RXBEACON, L0RXDLLFCCMPLMCCRED, L0RXDLLFCCMPLMCUPDATE, L0RXDLLFCNPOSTBYPCRED, L0RXDLLFCNPOSTBYPUPDATE, L0RXDLLFCPOSTORDCRED, L0RXDLLFCPOSTORDUPDATE, L0RXDLLPM, L0RXDLLPMTYPE, L0RXDLLSBFCDATA, L0RXDLLSBFCUPDATE, L0RXDLLTLPECRCOK, L0RXDLLTLPEND, L0RXMACLINKERROR, L0STATSCFGOTHERRECEIVED, L0STATSCFGOTHERTRANSMITTED, L0STATSCFGRECEIVED, L0STATSCFGTRANSMITTED, L0STATSDLLPRECEIVED, L0STATSDLLPTRANSMITTED, L0STATSOSRECEIVED, L0STATSOSTRANSMITTED, L0STATSTLPRECEIVED, L0STATSTLPTRANSMITTED, L0TOGGLEELECTROMECHANICALINTERLOCK, L0TRANSFORMEDVC, L0TXDLLFCCMPLMCUPDATED, L0TXDLLFCNPOSTBYPUPDATED, L0TXDLLFCPOSTORDUPDATED, L0TXDLLPMUPDATED, L0TXDLLSBFCUPDATED, L0UCBYPFOUND, L0UCORDFOUND, L0UNLOCKRECEIVED, LLKRX4DWHEADERN, LLKRXCHCOMPLETIONAVAILABLEN, LLKRXCHCOMPLETIONPARTIALN, LLKRXCHCONFIGAVAILABLEN, LLKRXCHCONFIGPARTIALN, LLKRXCHNONPOSTEDAVAILABLEN, LLKRXCHNONPOSTEDPARTIALN, LLKRXCHPOSTEDAVAILABLEN, LLKRXCHPOSTEDPARTIALN, LLKRXDATA, LLKRXECRCBADN, LLKRXEOFN, LLKRXEOPN, LLKRXPREFERREDTYPE, LLKRXSOFN, LLKRXSOPN, LLKRXSRCDSCN, LLKRXSRCLASTREQN, LLKRXSRCRDYN, LLKRXVALIDN, LLKTCSTATUS, LLKTXCHANSPACE, LLKTXCHCOMPLETIONREADYN, LLKTXCHNONPOSTEDREADYN, LLKTXCHPOSTEDREADYN, LLKTXCONFIGREADYN, LLKTXDSTRDYN, MAXPAYLOADSIZE, MAXREADREQUESTSIZE, MEMSPACEENABLE, MGMTPSO, MGMTRDATA, MGMTSTATSCREDIT, MIMDLLBRADD, MIMDLLBREN, MIMDLLBWADD, MIMDLLBWDATA, MIMDLLBWEN, MIMRXBRADD, MIMRXBREN, MIMRXBWADD, MIMRXBWDATA, MIMRXBWEN, MIMTXBRADD, MIMTXBREN, MIMTXBWADD, MIMTXBWDATA, MIMTXBWEN, PARITYERRORRESPONSE, PIPEDESKEWLANESL0, PIPEDESKEWLANESL1, PIPEDESKEWLANESL2, PIPEDESKEWLANESL3, PIPEDESKEWLANESL4, PIPEDESKEWLANESL5, PIPEDESKEWLANESL6, PIPEDESKEWLANESL7, PIPEPOWERDOWNL0, PIPEPOWERDOWNL1, PIPEPOWERDOWNL2, PIPEPOWERDOWNL3, PIPEPOWERDOWNL4, PIPEPOWERDOWNL5, PIPEPOWERDOWNL6, PIPEPOWERDOWNL7, PIPERESETL0, PIPERESETL1, PIPERESETL2, PIPERESETL3, PIPERESETL4, PIPERESETL5, PIPERESETL6, PIPERESETL7, PIPERXPOLARITYL0, PIPERXPOLARITYL1, PIPERXPOLARITYL2, PIPERXPOLARITYL3, PIPERXPOLARITYL4, PIPERXPOLARITYL5, PIPERXPOLARITYL6, PIPERXPOLARITYL7, PIPETXCOMPLIANCEL0, PIPETXCOMPLIANCEL1, PIPETXCOMPLIANCEL2, PIPETXCOMPLIANCEL3, PIPETXCOMPLIANCEL4, PIPETXCOMPLIANCEL5, PIPETXCOMPLIANCEL6, PIPETXCOMPLIANCEL7, PIPETXDATAKL0, PIPETXDATAKL1, PIPETXDATAKL2, PIPETXDATAKL3, PIPETXDATAKL4, PIPETXDATAKL5, PIPETXDATAKL6, PIPETXDATAKL7, PIPETXDATAL0, PIPETXDATAL1, PIPETXDATAL2, PIPETXDATAL3, PIPETXDATAL4, PIPETXDATAL5, PIPETXDATAL6, PIPETXDATAL7, PIPETXDETECTRXLOOPBACKL0, PIPETXDETECTRXLOOPBACKL1, PIPETXDETECTRXLOOPBACKL2, PIPETXDETECTRXLOOPBACKL3, PIPETXDETECTRXLOOPBACKL4, PIPETXDETECTRXLOOPBACKL5, PIPETXDETECTRXLOOPBACKL6, PIPETXDETECTRXLOOPBACKL7, PIPETXELECIDLEL0, PIPETXELECIDLEL1, PIPETXELECIDLEL2, PIPETXELECIDLEL3, PIPETXELECIDLEL4, PIPETXELECIDLEL5, PIPETXELECIDLEL6, PIPETXELECIDLEL7, SERRENABLE, URREPORTINGENABLE, AUXPOWER, CFGNEGOTIATEDLINKWIDTH, COMPLIANCEAVOID, CRMCFGBRIDGEHOTRESET, CRMCORECLK, CRMCORECLKDLO, CRMCORECLKRXO, CRMCORECLKTXO, CRMLINKRSTN, CRMMACRSTN, CRMMGMTRSTN, CRMNVRSTN, CRMTXHOTRESETN, CRMURSTN, CRMUSERCFGRSTN, CRMUSERCLK, CRMUSERCLKRXO, CRMUSERCLKTXO, CROSSLINKSEED, L0ACKNAKTIMERADJUSTMENT, L0ALLDOWNPORTSINL1, L0ALLDOWNRXPORTSINL0S, L0ASE, L0ASPORTCOUNT, L0ASTURNPOOLBITSCONSUMED, L0ATTENTIONBUTTONPRESSED, L0CFGASSPANTREEOWNEDSTATE, L0CFGASSTATECHANGECMD, L0CFGDISABLESCRAMBLE, L0CFGEXTENDEDSYNC, L0CFGL0SENTRYENABLE, L0CFGL0SENTRYSUP, L0CFGL0SEXITLAT, L0CFGLINKDISABLE, L0CFGLOOPBACKMASTER, L0CFGNEGOTIATEDMAXP, L0CFGVCENABLE, L0CFGVCID, L0DLLHOLDLINKUP, L0ELECTROMECHANICALINTERLOCKENGAGED, L0FWDASSERTINTALEGACYINT, L0FWDASSERTINTBLEGACYINT, L0FWDASSERTINTCLEGACYINT, L0FWDASSERTINTDLEGACYINT, L0FWDCORRERRIN, L0FWDDEASSERTINTALEGACYINT, L0FWDDEASSERTINTBLEGACYINT, L0FWDDEASSERTINTCLEGACYINT, L0FWDDEASSERTINTDLEGACYINT, L0FWDFATALERRIN, L0FWDNONFATALERRIN, L0LEGACYINTFUNCT0, L0MRLSENSORCLOSEDN, L0MSIREQUEST0, L0PACKETHEADERFROMUSER, L0PMEREQIN, L0PORTNUMBER, L0POWERFAULTDETECTED, L0PRESENCEDETECTSLOTEMPTYN, L0PWRNEWSTATEREQ, L0PWRNEXTLINKSTATE, L0REPLAYTIMERADJUSTMENT, L0ROOTTURNOFFREQ, L0RXTLTLPNONINITIALIZEDVC, L0SENDUNLOCKMESSAGE, L0SETCOMPLETERABORTERROR, L0SETCOMPLETIONTIMEOUTCORRERROR, L0SETCOMPLETIONTIMEOUTUNCORRERROR, L0SETDETECTEDCORRERROR, L0SETDETECTEDFATALERROR, L0SETDETECTEDNONFATALERROR, L0SETLINKDETECTEDPARITYERROR, L0SETLINKMASTERDATAPARITY, L0SETLINKRECEIVEDMASTERABORT, L0SETLINKRECEIVEDTARGETABORT, L0SETLINKSIGNALLEDTARGETABORT, L0SETLINKSYSTEMERROR, L0SETUNEXPECTEDCOMPLETIONCORRERROR, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR, L0SETUNSUPPORTEDREQUESTOTHERERROR, L0SETUSERDETECTEDPARITYERROR, L0SETUSERMASTERDATAPARITY, L0SETUSERRECEIVEDMASTERABORT, L0SETUSERRECEIVEDTARGETABORT, L0SETUSERSIGNALLEDTARGETABORT, L0SETUSERSYSTEMERROR, L0TLASFCCREDSTARVATION, L0TLLINKRETRAIN, L0TRANSACTIONSPENDING, L0TXBEACON, L0TXCFGPM, L0TXCFGPMTYPE, L0TXTLFCCMPLMCCRED, L0TXTLFCCMPLMCUPDATE, L0TXTLFCNPOSTBYPCRED, L0TXTLFCNPOSTBYPUPDATE, L0TXTLFCPOSTORDCRED, L0TXTLFCPOSTORDUPDATE, L0TXTLSBFCDATA, L0TXTLSBFCUPDATE, L0TXTLTLPDATA, L0TXTLTLPEDB, L0TXTLTLPENABLE, L0TXTLTLPEND, L0TXTLTLPLATENCY, L0TXTLTLPREQ, L0TXTLTLPREQEND, L0TXTLTLPWIDTH, L0UPSTREAMRXPORTINL0S, L0VC0PREVIEWEXPAND, L0WAKEN, LLKRXCHFIFO, LLKRXCHTC, LLKRXDSTCONTREQN, LLKRXDSTREQN, LLKTX4DWHEADERN, LLKTXCHFIFO, LLKTXCHTC, LLKTXCOMPLETEN, LLKTXCREATEECRCN, LLKTXDATA, LLKTXENABLEN, LLKTXEOFN, LLKTXEOPN, LLKTXSOFN, LLKTXSOPN, LLKTXSRCDSCN, LLKTXSRCRDYN, MAINPOWER, MGMTADDR, MGMTBWREN, MGMTRDEN, MGMTSTATSCREDITSEL, MGMTWDATA, MGMTWREN, MIMDLLBRDATA, MIMRXBRDATA, MIMTXBRDATA, PIPEPHYSTATUSL0, PIPEPHYSTATUSL1, PIPEPHYSTATUSL2, PIPEPHYSTATUSL3, PIPEPHYSTATUSL4, PIPEPHYSTATUSL5, PIPEPHYSTATUSL6, PIPEPHYSTATUSL7, PIPERXCHANISALIGNEDL0, PIPERXCHANISALIGNEDL1, PIPERXCHANISALIGNEDL2, PIPERXCHANISALIGNEDL3, PIPERXCHANISALIGNEDL4, PIPERXCHANISALIGNEDL5, PIPERXCHANISALIGNEDL6, PIPERXCHANISALIGNEDL7, PIPERXDATAKL0, PIPERXDATAKL1, PIPERXDATAKL2, PIPERXDATAKL3, PIPERXDATAKL4, PIPERXDATAKL5, PIPERXDATAKL6, PIPERXDATAKL7, PIPERXDATAL0, PIPERXDATAL1, PIPERXDATAL2, PIPERXDATAL3, PIPERXDATAL4, PIPERXDATAL5, PIPERXDATAL6, PIPERXDATAL7, PIPERXELECIDLEL0, PIPERXELECIDLEL1, PIPERXELECIDLEL2, PIPERXELECIDLEL3, PIPERXELECIDLEL4, PIPERXELECIDLEL5, PIPERXELECIDLEL6, PIPERXELECIDLEL7, PIPERXSTATUSL0, PIPERXSTATUSL1, PIPERXSTATUSL2, PIPERXSTATUSL3, PIPERXSTATUSL4, PIPERXSTATUSL5, PIPERXSTATUSL6, PIPERXSTATUSL7, PIPERXVALIDL0, PIPERXVALIDL1, PIPERXVALIDL2, PIPERXVALIDL3, PIPERXVALIDL4, PIPERXVALIDL5, PIPERXVALIDL6, PIPERXVALIDL7);
parameter AERCAPABILITYECRCCHECKCAPABLE = "FALSE";
parameter AERCAPABILITYECRCGENCAPABLE = "FALSE";
parameter BAR0EXIST = "TRUE";
parameter BAR0PREFETCHABLE = "TRUE";
parameter BAR1EXIST = "FALSE";
parameter BAR1PREFETCHABLE = "FALSE";
parameter BAR2EXIST = "FALSE";
parameter BAR2PREFETCHABLE = "FALSE";
parameter BAR3EXIST = "FALSE";
parameter BAR3PREFETCHABLE = "FALSE";
parameter BAR4EXIST = "FALSE";
parameter BAR4PREFETCHABLE = "FALSE";
parameter BAR5EXIST = "FALSE";
parameter BAR5PREFETCHABLE = "FALSE";
parameter CLKDIVIDED = "FALSE";
parameter DUALCOREENABLE = "FALSE";
parameter DUALCORESLAVE = "FALSE";
parameter INFINITECOMPLETIONS = "TRUE";
parameter ISSWITCH = "FALSE";
parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE";
parameter LLKBYPASS = "FALSE";
parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE";
parameter PCIECAPABILITYSLOTIMPL = "FALSE";
parameter PMCAPABILITYD1SUPPORT = "FALSE";
parameter PMCAPABILITYD2SUPPORT = "FALSE";
parameter PMCAPABILITYDSI = "TRUE";
parameter RAMSHARETXRX = "FALSE";
parameter RESETMODE = "FALSE";
parameter RETRYREADADDRPIPE = "FALSE";
parameter RETRYREADDATAPIPE = "FALSE";
parameter RETRYWRITEPIPE = "FALSE";
parameter RXREADADDRPIPE = "FALSE";
parameter RXREADDATAPIPE = "FALSE";
parameter RXWRITEPIPE = "FALSE";
parameter SELECTASMODE = "FALSE";
parameter SELECTDLLIF = "FALSE";
parameter SLOTCAPABILITYATTBUTTONPRESENT = "FALSE";
parameter SLOTCAPABILITYATTINDICATORPRESENT = "FALSE";
parameter SLOTCAPABILITYHOTPLUGCAPABLE = "FALSE";
parameter SLOTCAPABILITYHOTPLUGSURPRISE = "FALSE";
parameter SLOTCAPABILITYMSLSENSORPRESENT = "FALSE";
parameter SLOTCAPABILITYPOWERCONTROLLERPRESENT = "FALSE";
parameter SLOTCAPABILITYPOWERINDICATORPRESENT = "FALSE";
parameter SLOTIMPLEMENTED = "FALSE";
parameter TXREADADDRPIPE = "FALSE";
parameter TXREADDATAPIPE = "FALSE";
parameter TXWRITEPIPE = "FALSE";
parameter UPSTREAMFACING = "TRUE";
parameter XLINKSUPPORTED = "FALSE";
parameter [10:0] VC0TOTALCREDITSCD = 11'h0;
parameter [10:0] VC0TOTALCREDITSPD = 11'h34;
parameter [10:0] VC1TOTALCREDITSCD = 11'h0;
parameter [10:0] VC1TOTALCREDITSPD = 11'h0;
parameter [11:0] AERBASEPTR = 12'h110;
parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138;
parameter [11:0] DSNBASEPTR = 12'h148;
parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154;
parameter [11:0] EXTCFGXPCAPPTR = 12'h0;
parameter [11:0] MSIBASEPTR = 12'h48;
parameter [11:0] PBBASEPTR = 12'h138;
parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148;
parameter [11:0] PMBASEPTR = 12'h40;
parameter [11:0] RETRYRAMSIZE = 12'h9;
parameter [11:0] VCBASEPTR = 12'h154;
parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0;
parameter [12:0] SLOTCAPABILITYPHYSICALSLOTNUM = 13'h0;
parameter [12:0] VC0RXFIFOBASEC = 13'h98;
parameter [12:0] VC0RXFIFOBASENP = 13'h80;
parameter [12:0] VC0RXFIFOBASEP = 13'h0;
parameter [12:0] VC0RXFIFOLIMITC = 13'h117;
parameter [12:0] VC0RXFIFOLIMITNP = 13'h97;
parameter [12:0] VC0RXFIFOLIMITP = 13'h7f;
parameter [12:0] VC0TXFIFOBASEC = 13'h98;
parameter [12:0] VC0TXFIFOBASENP = 13'h80;
parameter [12:0] VC0TXFIFOBASEP = 13'h0;
parameter [12:0] VC0TXFIFOLIMITC = 13'h117;
parameter [12:0] VC0TXFIFOLIMITNP = 13'h97;
parameter [12:0] VC0TXFIFOLIMITP = 13'h7f;
parameter [12:0] VC1RXFIFOBASEC = 13'h118;
parameter [12:0] VC1RXFIFOBASENP = 13'h118;
parameter [12:0] VC1RXFIFOBASEP = 13'h118;
parameter [12:0] VC1RXFIFOLIMITC = 13'h118;
parameter [12:0] VC1RXFIFOLIMITNP = 13'h118;
parameter [12:0] VC1RXFIFOLIMITP = 13'h118;
parameter [12:0] VC1TXFIFOBASEC = 13'h118;
parameter [12:0] VC1TXFIFOBASENP = 13'h118;
parameter [12:0] VC1TXFIFOBASEP = 13'h118;
parameter [12:0] VC1TXFIFOLIMITC = 13'h118;
parameter [12:0] VC1TXFIFOLIMITNP = 13'h118;
parameter [12:0] VC1TXFIFOLIMITP = 13'h118;
parameter [15:0] DEVICEID = 16'h5050;
parameter [15:0] SUBSYSTEMID = 16'h5050;
parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE;
parameter [15:0] VENDORID = 16'h10EE;
parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1;
parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0;
parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0;
parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0;
parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0;
parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0;
parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0;
parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0;
parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0;
parameter [1:0] PMSTATUSCONTROLDATASCALE = 2'h0;
parameter [1:0] SLOTCAPABILITYSLOTPOWERLIMITSCALE = 2'h0;
parameter [23:0] CLASSCODE = 24'h058000;
parameter [2:0] CONFIGROUTING = 3'h1;
parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0;
parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0;
parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0;
parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0;
parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0;
parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0;
parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0;
parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0;
parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0;
parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0;
parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0;
parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0;
parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0;
parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0;
parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0;
parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0;
parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0;
parameter [31:0] CARDBUSCISPOINTER = 32'h0;
parameter [3:0] XPDEVICEPORTTYPE = 4'h0;
parameter [4:0] PCIECAPABILITYINTMSGNUM = 5'h0;
parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0;
parameter [5:0] BAR0MASKWIDTH = 6'h14;
parameter [5:0] BAR1MASKWIDTH = 6'h0;
parameter [5:0] BAR2MASKWIDTH = 6'h0;
parameter [5:0] BAR3MASKWIDTH = 6'h0;
parameter [5:0] BAR4MASKWIDTH = 6'h0;
parameter [5:0] BAR5MASKWIDTH = 6'h0;
parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01;
parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35;
parameter [6:0] VC0TOTALCREDITSCH = 7'h0;
parameter [6:0] VC0TOTALCREDITSNPH = 7'h08;
parameter [6:0] VC0TOTALCREDITSPH = 7'h08;
parameter [6:0] VC1TOTALCREDITSCH = 7'h0;
parameter [6:0] VC1TOTALCREDITSNPH = 7'h0;
parameter [6:0] VC1TOTALCREDITSPH = 7'h0;
parameter [7:0] ACTIVELANESIN = 8'h1;
parameter [7:0] CAPABILITIESPOINTER = 8'h40;
parameter [7:0] EXTCFGCAPPTR = 8'h0;
parameter [7:0] HEADERTYPE = 8'h0;
parameter [7:0] INTERRUPTPIN = 8'h0;
parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60;
parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0;
parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0;
parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0;
parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0;
parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0;
parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60;
parameter [7:0] PMDATA0 = 8'h0;
parameter [7:0] PMDATA1 = 8'h0;
parameter [7:0] PMDATA2 = 8'h0;
parameter [7:0] PMDATA3 = 8'h0;
parameter [7:0] PMDATA4 = 8'h0;
parameter [7:0] PMDATA5 = 8'h0;
parameter [7:0] PMDATA6 = 8'h0;
parameter [7:0] PMDATA7 = 8'h0;
parameter [7:0] PMDATA8 = 8'h0;
parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0;
parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0;
parameter [7:0] REVISIONID = 8'h0;
parameter [7:0] SLOTCAPABILITYSLOTPOWERLIMITVALUE = 8'h0;
parameter [7:0] XPBASEPTR = 8'h60;
parameter integer BAR0ADDRWIDTH = 0;
parameter integer BAR0IOMEMN = 0;
parameter integer BAR1ADDRWIDTH = 0;
parameter integer BAR1IOMEMN = 0;
parameter integer BAR2ADDRWIDTH = 0;
parameter integer BAR2IOMEMN = 0;
parameter integer BAR3ADDRWIDTH = 0;
parameter integer BAR3IOMEMN = 0;
parameter integer BAR4ADDRWIDTH = 0;
parameter integer BAR4IOMEMN = 0;
parameter integer BAR5IOMEMN = 0;
parameter integer DUALROLECFGCNTRLROOTEPN = 0;
parameter integer L0SEXITLATENCY = 7;
parameter integer L0SEXITLATENCYCOMCLK = 7;
parameter integer L1EXITLATENCY = 7;
parameter integer L1EXITLATENCYCOMCLK = 7;
parameter integer LOWPRIORITYVCCOUNT = 0;
parameter integer PCIEREVISION = 1;
parameter integer PMDATASCALE0 = 0;
parameter integer PMDATASCALE1 = 0;
parameter integer PMDATASCALE2 = 0;
parameter integer PMDATASCALE3 = 0;
parameter integer PMDATASCALE4 = 0;
parameter integer PMDATASCALE5 = 0;
parameter integer PMDATASCALE6 = 0;
parameter integer PMDATASCALE7 = 0;
parameter integer PMDATASCALE8 = 0;
parameter integer RETRYRAMREADLATENCY = 3;
parameter integer RETRYRAMWIDTH = 0;
parameter integer RETRYRAMWRITELATENCY = 1;
parameter integer TLRAMREADLATENCY = 3;
parameter integer TLRAMWIDTH = 0;
parameter integer TLRAMWRITELATENCY = 1;
parameter integer TXTSNFTS = 255;
parameter integer TXTSNFTSCOMCLK = 255;
parameter integer XPMAXPAYLOAD = 0;
parameter integer XPRCBCONTROL = 0;
output BUSMASTERENABLE;
output CRMDOHOTRESETN;
output CRMPWRSOFTRESETN;
output CRMRXHOTRESETN;
output DLLTXPMDLLPOUTSTANDING;
output INTERRUPTDISABLE;
output IOSPACEENABLE;
output L0ASAUTONOMOUSINITCOMPLETED;
output [1:0] L0ATTENTIONINDICATORCONTROL;
output L0CFGLOOPBACKACK;
output [12:0] L0COMPLETERID;
output L0CORRERRMSGRCVD;
output [1:0] L0DLLASRXSTATE;
output L0DLLASTXSTATE;
output [6:0] L0DLLERRORVECTOR;
output L0DLLRXACKOUTSTANDING;
output L0DLLTXNONFCOUTSTANDING;
output L0DLLTXOUTSTANDING;
output [7:0] L0DLLVCSTATUS;
output [7:0] L0DLUPDOWN;
output [15:0] L0ERRMSGREQID;
output L0FATALERRMSGRCVD;
output L0FIRSTCFGWRITEOCCURRED;
output L0FWDCORRERROUT;
output L0FWDFATALERROUT;
output L0FWDNONFATALERROUT;
output [3:0] L0LTSSMSTATE;
output L0MACENTEREDL0;
output L0MACLINKTRAINING;
output L0MACLINKUP;
output [3:0] L0MACNEGOTIATEDLINKWIDTH;
output L0MACNEWSTATEACK;
output L0MACRXL0SSTATE;
output L0MACUPSTREAMDOWNSTREAM;
output [2:0] L0MCFOUND;
output L0MSIENABLE0;
output [2:0] L0MULTIMSGEN0;
output L0NONFATALERRMSGRCVD;
output L0PMEACK;
output L0PMEEN;
output L0PMEREQOUT;
output L0POWERCONTROLLERCONTROL;
output [1:0] L0POWERINDICATORCONTROL;
output L0PWRINHIBITTRANSFERS;
output L0PWRL1STATE;
output L0PWRL23READYDEVICE;
output L0PWRL23READYSTATE;
output [1:0] L0PWRSTATE0;
output L0PWRTURNOFFREQ;
output L0PWRTXL0SSTATE;
output L0RECEIVEDASSERTINTALEGACYINT;
output L0RECEIVEDASSERTINTBLEGACYINT;
output L0RECEIVEDASSERTINTCLEGACYINT;
output L0RECEIVEDASSERTINTDLEGACYINT;
output L0RECEIVEDDEASSERTINTALEGACYINT;
output L0RECEIVEDDEASSERTINTBLEGACYINT;
output L0RECEIVEDDEASSERTINTCLEGACYINT;
output L0RECEIVEDDEASSERTINTDLEGACYINT;
output L0RXBEACON;
output [23:0] L0RXDLLFCCMPLMCCRED;
output [7:0] L0RXDLLFCCMPLMCUPDATE;
output [19:0] L0RXDLLFCNPOSTBYPCRED;
output [7:0] L0RXDLLFCNPOSTBYPUPDATE;
output [23:0] L0RXDLLFCPOSTORDCRED;
output [7:0] L0RXDLLFCPOSTORDUPDATE;
output L0RXDLLPM;
output [2:0] L0RXDLLPMTYPE;
output [18:0] L0RXDLLSBFCDATA;
output L0RXDLLSBFCUPDATE;
output L0RXDLLTLPECRCOK;
output [1:0] L0RXDLLTLPEND;
output [1:0] L0RXMACLINKERROR;
output L0STATSCFGOTHERRECEIVED;
output L0STATSCFGOTHERTRANSMITTED;
output L0STATSCFGRECEIVED;
output L0STATSCFGTRANSMITTED;
output L0STATSDLLPRECEIVED;
output L0STATSDLLPTRANSMITTED;
output L0STATSOSRECEIVED;
output L0STATSOSTRANSMITTED;
output L0STATSTLPRECEIVED;
output L0STATSTLPTRANSMITTED;
output L0TOGGLEELECTROMECHANICALINTERLOCK;
output [2:0] L0TRANSFORMEDVC;
output [7:0] L0TXDLLFCCMPLMCUPDATED;
output [7:0] L0TXDLLFCNPOSTBYPUPDATED;
output [7:0] L0TXDLLFCPOSTORDUPDATED;
output L0TXDLLPMUPDATED;
output L0TXDLLSBFCUPDATED;
output [3:0] L0UCBYPFOUND;
output [3:0] L0UCORDFOUND;
output L0UNLOCKRECEIVED;
output LLKRX4DWHEADERN;
output [7:0] LLKRXCHCOMPLETIONAVAILABLEN;
output [7:0] LLKRXCHCOMPLETIONPARTIALN;
output LLKRXCHCONFIGAVAILABLEN;
output LLKRXCHCONFIGPARTIALN;
output [7:0] LLKRXCHNONPOSTEDAVAILABLEN;
output [7:0] LLKRXCHNONPOSTEDPARTIALN;
output [7:0] LLKRXCHPOSTEDAVAILABLEN;
output [7:0] LLKRXCHPOSTEDPARTIALN;
output [63:0] LLKRXDATA;
output LLKRXECRCBADN;
output LLKRXEOFN;
output LLKRXEOPN;
output [15:0] LLKRXPREFERREDTYPE;
output LLKRXSOFN;
output LLKRXSOPN;
output LLKRXSRCDSCN;
output LLKRXSRCLASTREQN;
output LLKRXSRCRDYN;
output [1:0] LLKRXVALIDN;
output [7:0] LLKTCSTATUS;
output [9:0] LLKTXCHANSPACE;
output [7:0] LLKTXCHCOMPLETIONREADYN;
output [7:0] LLKTXCHNONPOSTEDREADYN;
output [7:0] LLKTXCHPOSTEDREADYN;
output LLKTXCONFIGREADYN;
output LLKTXDSTRDYN;
output [2:0] MAXPAYLOADSIZE;
output [2:0] MAXREADREQUESTSIZE;
output MEMSPACEENABLE;
output [16:0] MGMTPSO;
output [31:0] MGMTRDATA;
output [11:0] MGMTSTATSCREDIT;
output [11:0] MIMDLLBRADD;
output MIMDLLBREN;
output [11:0] MIMDLLBWADD;
output [63:0] MIMDLLBWDATA;
output MIMDLLBWEN;
output [12:0] MIMRXBRADD;
output MIMRXBREN;
output [12:0] MIMRXBWADD;
output [63:0] MIMRXBWDATA;
output MIMRXBWEN;
output [12:0] MIMTXBRADD;
output MIMTXBREN;
output [12:0] MIMTXBWADD;
output [63:0] MIMTXBWDATA;
output MIMTXBWEN;
output PARITYERRORRESPONSE;
output PIPEDESKEWLANESL0;
output PIPEDESKEWLANESL1;
output PIPEDESKEWLANESL2;
output PIPEDESKEWLANESL3;
output PIPEDESKEWLANESL4;
output PIPEDESKEWLANESL5;
output PIPEDESKEWLANESL6;
output PIPEDESKEWLANESL7;
output [1:0] PIPEPOWERDOWNL0;
output [1:0] PIPEPOWERDOWNL1;
output [1:0] PIPEPOWERDOWNL2;
output [1:0] PIPEPOWERDOWNL3;
output [1:0] PIPEPOWERDOWNL4;
output [1:0] PIPEPOWERDOWNL5;
output [1:0] PIPEPOWERDOWNL6;
output [1:0] PIPEPOWERDOWNL7;
output PIPERESETL0;
output PIPERESETL1;
output PIPERESETL2;
output PIPERESETL3;
output PIPERESETL4;
output PIPERESETL5;
output PIPERESETL6;
output PIPERESETL7;
output PIPERXPOLARITYL0;
output PIPERXPOLARITYL1;
output PIPERXPOLARITYL2;
output PIPERXPOLARITYL3;
output PIPERXPOLARITYL4;
output PIPERXPOLARITYL5;
output PIPERXPOLARITYL6;
output PIPERXPOLARITYL7;
output PIPETXCOMPLIANCEL0;
output PIPETXCOMPLIANCEL1;
output PIPETXCOMPLIANCEL2;
output PIPETXCOMPLIANCEL3;
output PIPETXCOMPLIANCEL4;
output PIPETXCOMPLIANCEL5;
output PIPETXCOMPLIANCEL6;
output PIPETXCOMPLIANCEL7;
output PIPETXDATAKL0;
output PIPETXDATAKL1;
output PIPETXDATAKL2;
output PIPETXDATAKL3;
output PIPETXDATAKL4;
output PIPETXDATAKL5;
output PIPETXDATAKL6;
output PIPETXDATAKL7;
output [7:0] PIPETXDATAL0;
output [7:0] PIPETXDATAL1;
output [7:0] PIPETXDATAL2;
output [7:0] PIPETXDATAL3;
output [7:0] PIPETXDATAL4;
output [7:0] PIPETXDATAL5;
output [7:0] PIPETXDATAL6;
output [7:0] PIPETXDATAL7;
output PIPETXDETECTRXLOOPBACKL0;
output PIPETXDETECTRXLOOPBACKL1;
output PIPETXDETECTRXLOOPBACKL2;
output PIPETXDETECTRXLOOPBACKL3;
output PIPETXDETECTRXLOOPBACKL4;
output PIPETXDETECTRXLOOPBACKL5;
output PIPETXDETECTRXLOOPBACKL6;
output PIPETXDETECTRXLOOPBACKL7;
output PIPETXELECIDLEL0;
output PIPETXELECIDLEL1;
output PIPETXELECIDLEL2;
output PIPETXELECIDLEL3;
output PIPETXELECIDLEL4;
output PIPETXELECIDLEL5;
output PIPETXELECIDLEL6;
output PIPETXELECIDLEL7;
output SERRENABLE;
output URREPORTINGENABLE;
input AUXPOWER;
input [5:0] CFGNEGOTIATEDLINKWIDTH;
input COMPLIANCEAVOID;
input CRMCFGBRIDGEHOTRESET;
input CRMCORECLK;
input CRMCORECLKDLO;
input CRMCORECLKRXO;
input CRMCORECLKTXO;
input CRMLINKRSTN;
input CRMMACRSTN;
input CRMMGMTRSTN;
input CRMNVRSTN;
input CRMTXHOTRESETN;
input CRMURSTN;
input CRMUSERCFGRSTN;
input CRMUSERCLK;
input CRMUSERCLKRXO;
input CRMUSERCLKTXO;
input CROSSLINKSEED;
input [11:0] L0ACKNAKTIMERADJUSTMENT;
input L0ALLDOWNPORTSINL1;
input L0ALLDOWNRXPORTSINL0S;
input L0ASE;
input [7:0] L0ASPORTCOUNT;
input [2:0] L0ASTURNPOOLBITSCONSUMED;
input L0ATTENTIONBUTTONPRESSED;
input L0CFGASSPANTREEOWNEDSTATE;
input [3:0] L0CFGASSTATECHANGECMD;
input L0CFGDISABLESCRAMBLE;
input L0CFGEXTENDEDSYNC;
input L0CFGL0SENTRYENABLE;
input L0CFGL0SENTRYSUP;
input [2:0] L0CFGL0SEXITLAT;
input L0CFGLINKDISABLE;
input L0CFGLOOPBACKMASTER;
input [2:0] L0CFGNEGOTIATEDMAXP;
input [7:0] L0CFGVCENABLE;
input [23:0] L0CFGVCID;
input L0DLLHOLDLINKUP;
input L0ELECTROMECHANICALINTERLOCKENGAGED;
input L0FWDASSERTINTALEGACYINT;
input L0FWDASSERTINTBLEGACYINT;
input L0FWDASSERTINTCLEGACYINT;
input L0FWDASSERTINTDLEGACYINT;
input L0FWDCORRERRIN;
input L0FWDDEASSERTINTALEGACYINT;
input L0FWDDEASSERTINTBLEGACYINT;
input L0FWDDEASSERTINTCLEGACYINT;
input L0FWDDEASSERTINTDLEGACYINT;
input L0FWDFATALERRIN;
input L0FWDNONFATALERRIN;
input L0LEGACYINTFUNCT0;
input L0MRLSENSORCLOSEDN;
input [3:0] L0MSIREQUEST0;
input [127:0] L0PACKETHEADERFROMUSER;
input L0PMEREQIN;
input [7:0] L0PORTNUMBER;
input L0POWERFAULTDETECTED;
input L0PRESENCEDETECTSLOTEMPTYN;
input L0PWRNEWSTATEREQ;
input [1:0] L0PWRNEXTLINKSTATE;
input [11:0] L0REPLAYTIMERADJUSTMENT;
input L0ROOTTURNOFFREQ;
input [7:0] L0RXTLTLPNONINITIALIZEDVC;
input L0SENDUNLOCKMESSAGE;
input L0SETCOMPLETERABORTERROR;
input L0SETCOMPLETIONTIMEOUTCORRERROR;
input L0SETCOMPLETIONTIMEOUTUNCORRERROR;
input L0SETDETECTEDCORRERROR;
input L0SETDETECTEDFATALERROR;
input L0SETDETECTEDNONFATALERROR;
input L0SETLINKDETECTEDPARITYERROR;
input L0SETLINKMASTERDATAPARITY;
input L0SETLINKRECEIVEDMASTERABORT;
input L0SETLINKRECEIVEDTARGETABORT;
input L0SETLINKSIGNALLEDTARGETABORT;
input L0SETLINKSYSTEMERROR;
input L0SETUNEXPECTEDCOMPLETIONCORRERROR;
input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR;
input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR;
input L0SETUNSUPPORTEDREQUESTOTHERERROR;
input L0SETUSERDETECTEDPARITYERROR;
input L0SETUSERMASTERDATAPARITY;
input L0SETUSERRECEIVEDMASTERABORT;
input L0SETUSERRECEIVEDTARGETABORT;
input L0SETUSERSIGNALLEDTARGETABORT;
input L0SETUSERSYSTEMERROR;
input L0TLASFCCREDSTARVATION;
input L0TLLINKRETRAIN;
input L0TRANSACTIONSPENDING;
input L0TXBEACON;
input L0TXCFGPM;
input [2:0] L0TXCFGPMTYPE;
input [159:0] L0TXTLFCCMPLMCCRED;
input [15:0] L0TXTLFCCMPLMCUPDATE;
input [191:0] L0TXTLFCNPOSTBYPCRED;
input [15:0] L0TXTLFCNPOSTBYPUPDATE;
input [159:0] L0TXTLFCPOSTORDCRED;
input [15:0] L0TXTLFCPOSTORDUPDATE;
input [18:0] L0TXTLSBFCDATA;
input L0TXTLSBFCUPDATE;
input [63:0] L0TXTLTLPDATA;
input L0TXTLTLPEDB;
input [1:0] L0TXTLTLPENABLE;
input [1:0] L0TXTLTLPEND;
input [3:0] L0TXTLTLPLATENCY;
input L0TXTLTLPREQ;
input L0TXTLTLPREQEND;
input L0TXTLTLPWIDTH;
input L0UPSTREAMRXPORTINL0S;
input L0VC0PREVIEWEXPAND;
input L0WAKEN;
input [1:0] LLKRXCHFIFO;
input [2:0] LLKRXCHTC;
input LLKRXDSTCONTREQN;
input LLKRXDSTREQN;
input LLKTX4DWHEADERN;
input [1:0] LLKTXCHFIFO;
input [2:0] LLKTXCHTC;
input LLKTXCOMPLETEN;
input LLKTXCREATEECRCN;
input [63:0] LLKTXDATA;
input [1:0] LLKTXENABLEN;
input LLKTXEOFN;
input LLKTXEOPN;
input LLKTXSOFN;
input LLKTXSOPN;
input LLKTXSRCDSCN;
input LLKTXSRCRDYN;
input MAINPOWER;
input [10:0] MGMTADDR;
input [3:0] MGMTBWREN;
input MGMTRDEN;
input [6:0] MGMTSTATSCREDITSEL;
input [31:0] MGMTWDATA;
input MGMTWREN;
input [63:0] MIMDLLBRDATA;
input [63:0] MIMRXBRDATA;
input [63:0] MIMTXBRDATA;
input PIPEPHYSTATUSL0;
input PIPEPHYSTATUSL1;
input PIPEPHYSTATUSL2;
input PIPEPHYSTATUSL3;
input PIPEPHYSTATUSL4;
input PIPEPHYSTATUSL5;
input PIPEPHYSTATUSL6;
input PIPEPHYSTATUSL7;
input PIPERXCHANISALIGNEDL0;
input PIPERXCHANISALIGNEDL1;
input PIPERXCHANISALIGNEDL2;
input PIPERXCHANISALIGNEDL3;
input PIPERXCHANISALIGNEDL4;
input PIPERXCHANISALIGNEDL5;
input PIPERXCHANISALIGNEDL6;
input PIPERXCHANISALIGNEDL7;
input PIPERXDATAKL0;
input PIPERXDATAKL1;
input PIPERXDATAKL2;
input PIPERXDATAKL3;
input PIPERXDATAKL4;
input PIPERXDATAKL5;
input PIPERXDATAKL6;
input PIPERXDATAKL7;
input [7:0] PIPERXDATAL0;
input [7:0] PIPERXDATAL1;
input [7:0] PIPERXDATAL2;
input [7:0] PIPERXDATAL3;
input [7:0] PIPERXDATAL4;
input [7:0] PIPERXDATAL5;
input [7:0] PIPERXDATAL6;
input [7:0] PIPERXDATAL7;
input PIPERXELECIDLEL0;
input PIPERXELECIDLEL1;
input PIPERXELECIDLEL2;
input PIPERXELECIDLEL3;
input PIPERXELECIDLEL4;
input PIPERXELECIDLEL5;
input PIPERXELECIDLEL6;
input PIPERXELECIDLEL7;
input [2:0] PIPERXSTATUSL0;
input [2:0] PIPERXSTATUSL1;
input [2:0] PIPERXSTATUSL2;
input [2:0] PIPERXSTATUSL3;
input [2:0] PIPERXSTATUSL4;
input [2:0] PIPERXSTATUSL5;
input [2:0] PIPERXSTATUSL6;
input [2:0] PIPERXSTATUSL7;
input PIPERXVALIDL0;
input PIPERXVALIDL1;
input PIPERXVALIDL2;
input PIPERXVALIDL3;
input PIPERXVALIDL4;
input PIPERXVALIDL5;
input PIPERXVALIDL6;
input PIPERXVALIDL7;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PLL_ADV (CLKFBDCM, CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUTDCM0, CLKOUTDCM1, CLKOUTDCM2, CLKOUTDCM3, CLKOUTDCM4, CLKOUTDCM5, DO, DRDY, LOCKED, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, REL, RST);
parameter BANDWIDTH = "OPTIMIZED";
parameter CLKFBOUT_DESKEW_ADJUST = "NONE";
parameter CLKOUT0_DESKEW_ADJUST = "NONE";
parameter CLKOUT1_DESKEW_ADJUST = "NONE";
parameter CLKOUT2_DESKEW_ADJUST = "NONE";
parameter CLKOUT3_DESKEW_ADJUST = "NONE";
parameter CLKOUT4_DESKEW_ADJUST = "NONE";
parameter CLKOUT5_DESKEW_ADJUST = "NONE";
parameter integer CLKFBOUT_MULT = 1;
parameter real CLKFBOUT_PHASE = 0.0;
parameter real CLKIN1_PERIOD = 0.000;
parameter real CLKIN2_PERIOD = 0.000;
parameter integer CLKOUT0_DIVIDE = 1;
parameter real CLKOUT0_DUTY_CYCLE = 0.5;
parameter real CLKOUT0_PHASE = 0.0;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.5;
parameter real CLKOUT1_PHASE = 0.0;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.5;
parameter real CLKOUT2_PHASE = 0.0;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.5;
parameter real CLKOUT3_PHASE = 0.0;
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.5;
parameter real CLKOUT4_PHASE = 0.0;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.5;
parameter real CLKOUT5_PHASE = 0.0;
parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
parameter integer DIVCLK_DIVIDE = 1;
parameter EN_REL = "FALSE";
parameter PLL_PMCD_MODE = "FALSE";
parameter real REF_JITTER = 0.100;
parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
parameter RST_DEASSERT_CLK = "CLKIN1";
output CLKFBDCM;
output CLKFBOUT;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output CLKOUTDCM0;
output CLKOUTDCM1;
output CLKOUTDCM2;
output CLKOUTDCM3;
output CLKOUTDCM4;
output CLKOUTDCM5;
output [15:0] DO;
output DRDY;
output LOCKED;
input CLKFBIN;
input CLKIN1;
input CLKIN2;
input CLKINSEL;
input [4:0] DADDR;
input DCLK;
input DEN;
input [15:0] DI;
input DWE;
input REL;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PLL_BASE (CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, LOCKED, CLKFBIN, CLKIN, RST);
parameter BANDWIDTH = "OPTIMIZED";
parameter integer CLKFBOUT_MULT = 1;
parameter real CLKFBOUT_PHASE = 0.0;
parameter real CLKIN_PERIOD = 0.000;
parameter integer CLKOUT0_DIVIDE = 1;
parameter real CLKOUT0_DUTY_CYCLE = 0.5;
parameter real CLKOUT0_PHASE = 0.0;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.5;
parameter real CLKOUT1_PHASE = 0.0;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.5;
parameter real CLKOUT2_PHASE = 0.0;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.5;
parameter real CLKOUT3_PHASE = 0.0;
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.5;
parameter real CLKOUT4_PHASE = 0.0;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.5;
parameter real CLKOUT5_PHASE = 0.0;
parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER = 0.100;
parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
output CLKFBOUT;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output LOCKED;
input CLKFBIN;
input CLKIN;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PMCD (CLKA1, CLKA1D2, CLKA1D4, CLKA1D8, CLKB1, CLKC1, CLKD1, CLKA, CLKB, CLKC, CLKD, REL, RST);
parameter EN_REL = "FALSE";
parameter RST_DEASSERT_CLK = "CLKA";
output CLKA1;
output CLKA1D2;
output CLKA1D4;
output CLKA1D8;
output CLKB1;
output CLKC1;
output CLKD1;
input CLKA;
input CLKB;
input CLKC;
input CLKD;
input REL;
input RST;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PPC405_ADV (APUFCMDECODED, APUFCMDECUDI, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRUCTION, APUFCMINSTRVALID, APUFCMLOADBYTEEN, APUFCMLOADDATA, APUFCMLOADDVALID, APUFCMOPERANDVALID, APUFCMRADATA, APUFCMRBDATA, APUFCMWRITEBACKOK, APUFCMXERCA, C405CPMCORESLEEPREQ, C405CPMMSRCE, C405CPMMSREE, C405CPMTIMERIRQ, C405CPMTIMERRESETREQ, C405DBGLOADDATAONAPUDBUS, C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, C405DBGWBIAR, C405JTGCAPTUREDR, C405JTGEXTEST, C405JTGPGMOUT, C405JTGSHIFTDR, C405JTGTDO, C405JTGTDOEN, C405JTGUPDATEDR, C405PLBDCUABORT, C405PLBDCUABUS, C405PLBDCUBE, C405PLBDCUCACHEABLE, C405PLBDCUGUARDED, C405PLBDCUPRIORITY, C405PLBDCUREQUEST, C405PLBDCURNW, C405PLBDCUSIZE2, C405PLBDCUU0ATTR, C405PLBDCUWRDBUS, C405PLBDCUWRITETHRU, C405PLBICUABORT, C405PLBICUABUS, C405PLBICUCACHEABLE, C405PLBICUPRIORITY, C405PLBICUREQUEST, C405PLBICUSIZE, C405PLBICUU0ATTR, C405RSTCHIPRESETREQ, C405RSTCORERESETREQ, C405RSTSYSRESETREQ, C405TRCCYCLE, C405TRCEVENEXECUTIONSTATUS, C405TRCODDEXECUTIONSTATUS, C405TRCTRACESTATUS, C405TRCTRIGGEREVENTOUT, C405TRCTRIGGEREVENTTYPE, C405XXXMACHINECHECK, DCREMACABUS, DCREMACCLK, DCREMACDBUS, DCREMACENABLER, DCREMACREAD, DCREMACWRITE, DSOCMBRAMABUS, DSOCMBRAMBYTEWRITE, DSOCMBRAMEN, DSOCMBRAMWRDBUS, DSOCMBUSY, DSOCMRDADDRVALID, DSOCMWRADDRVALID, EXTDCRABUS, EXTDCRDBUSOUT, EXTDCRREAD, EXTDCRWRITE, ISOCMBRAMEN, ISOCMBRAMEVENWRITEEN, ISOCMBRAMODDWRITEEN, ISOCMBRAMRDABUS, ISOCMBRAMWRABUS, ISOCMBRAMWRDBUS, ISOCMDCRBRAMEVENEN, ISOCMDCRBRAMODDEN, ISOCMDCRBRAMRDSELECT, BRAMDSOCMCLK, BRAMDSOCMRDDBUS, BRAMISOCMCLK, BRAMISOCMDCRRDDBUS, BRAMISOCMRDDBUS, CPMC405CLOCK, CPMC405CORECLKINACTIVE, CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405SYNCBYPASS, CPMC405TIMERCLKEN, CPMC405TIMERTICK, CPMDCRCLK, CPMFCMCLK, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT, DSARCVALUE, DSCNTLVALUE, DSOCMRWCOMPLETE, EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ, EMACDCRACK, EMACDCRDBUS, EXTDCRACK, EXTDCRDBUSIN, FCMAPUCR, FCMAPUDCDCREN, FCMAPUDCDFORCEALIGN, FCMAPUDCDFORCEBESTEERING, FCMAPUDCDFPUOP, FCMAPUDCDGPRWRITE, FCMAPUDCDLDSTBYTE, FCMAPUDCDLDSTDW, FCMAPUDCDLDSTHW, FCMAPUDCDLDSTQW, FCMAPUDCDLDSTWD, FCMAPUDCDLOAD, FCMAPUDCDPRIVOP, FCMAPUDCDRAEN, FCMAPUDCDRBEN, FCMAPUDCDSTORE, FCMAPUDCDTRAPBE, FCMAPUDCDTRAPLE, FCMAPUDCDUPDATE, FCMAPUDCDXERCAEN, FCMAPUDCDXEROVEN, FCMAPUDECODEBUSY, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUEXEBLOCKINGMCO, FCMAPUEXECRFIELD, FCMAPUEXENONBLOCKINGMCO, FCMAPUINSTRACK, FCMAPULOADWAIT, FCMAPURESULT, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, FCMAPUXERCA, FCMAPUXEROV, ISARCVALUE, ISCNTLVALUE, JTGC405BNDSCANTDO, JTGC405TCK, JTGC405TDI, JTGC405TMS, JTGC405TRSTNEG, MCBCPUCLKEN, MCBJTAGEN, MCBTIMEREN, MCPPCRST, PLBC405DCUADDRACK, PLBC405DCUBUSY, PLBC405DCUERR, PLBC405DCURDDACK, PLBC405DCURDDBUS, PLBC405DCURDWDADDR, PLBC405DCUSSIZE1, PLBC405DCUWRDACK, PLBC405ICUADDRACK, PLBC405ICUBUSY, PLBC405ICUERR, PLBC405ICURDDACK, PLBC405ICURDDBUS, PLBC405ICURDWDADDR, PLBC405ICUSSIZE1, PLBCLK, RSTC405RESETCHIP, RSTC405RESETCORE, RSTC405RESETSYS, TIEAPUCONTROL, TIEAPUUDI1, TIEAPUUDI2, TIEAPUUDI3, TIEAPUUDI4, TIEAPUUDI5, TIEAPUUDI6, TIEAPUUDI7, TIEAPUUDI8, TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD, TIEC405MMUEN, TIEDCRADDR, TIEPVRBIT10, TIEPVRBIT11, TIEPVRBIT28, TIEPVRBIT29, TIEPVRBIT30, TIEPVRBIT31, TIEPVRBIT8, TIEPVRBIT9, TRCC405TRACEDISABLE, TRCC405TRIGGEREVENTIN);
output APUFCMDECODED;
output [0:2] APUFCMDECUDI;
output APUFCMDECUDIVALID;
output APUFCMENDIAN;
output APUFCMFLUSH;
output [0:31] APUFCMINSTRUCTION;
output APUFCMINSTRVALID;
output [0:3] APUFCMLOADBYTEEN;
output [0:31] APUFCMLOADDATA;
output APUFCMLOADDVALID;
output APUFCMOPERANDVALID;
output [0:31] APUFCMRADATA;
output [0:31] APUFCMRBDATA;
output APUFCMWRITEBACKOK;
output APUFCMXERCA;
output C405CPMCORESLEEPREQ;
output C405CPMMSRCE;
output C405CPMMSREE;
output C405CPMTIMERIRQ;
output C405CPMTIMERRESETREQ;
output C405DBGLOADDATAONAPUDBUS;
output C405DBGMSRWE;
output C405DBGSTOPACK;
output C405DBGWBCOMPLETE;
output C405DBGWBFULL;
output [0:29] C405DBGWBIAR;
output C405JTGCAPTUREDR;
output C405JTGEXTEST;
output C405JTGPGMOUT;
output C405JTGSHIFTDR;
output C405JTGTDO;
output C405JTGTDOEN;
output C405JTGUPDATEDR;
output C405PLBDCUABORT;
output [0:31] C405PLBDCUABUS;
output [0:7] C405PLBDCUBE;
output C405PLBDCUCACHEABLE;
output C405PLBDCUGUARDED;
output [0:1] C405PLBDCUPRIORITY;
output C405PLBDCUREQUEST;
output C405PLBDCURNW;
output C405PLBDCUSIZE2;
output C405PLBDCUU0ATTR;
output [0:63] C405PLBDCUWRDBUS;
output C405PLBDCUWRITETHRU;
output C405PLBICUABORT;
output [0:29] C405PLBICUABUS;
output C405PLBICUCACHEABLE;
output [0:1] C405PLBICUPRIORITY;
output C405PLBICUREQUEST;
output [2:3] C405PLBICUSIZE;
output C405PLBICUU0ATTR;
output C405RSTCHIPRESETREQ;
output C405RSTCORERESETREQ;
output C405RSTSYSRESETREQ;
output C405TRCCYCLE;
output [0:1] C405TRCEVENEXECUTIONSTATUS;
output [0:1] C405TRCODDEXECUTIONSTATUS;
output [0:3] C405TRCTRACESTATUS;
output C405TRCTRIGGEREVENTOUT;
output [0:10] C405TRCTRIGGEREVENTTYPE;
output C405XXXMACHINECHECK;
output [8:9] DCREMACABUS;
output DCREMACCLK;
output [0:31] DCREMACDBUS;
output DCREMACENABLER;
output DCREMACREAD;
output DCREMACWRITE;
output [8:29] DSOCMBRAMABUS;
output [0:3] DSOCMBRAMBYTEWRITE;
output DSOCMBRAMEN;
output [0:31] DSOCMBRAMWRDBUS;
output DSOCMBUSY;
output DSOCMRDADDRVALID;
output DSOCMWRADDRVALID;
output [0:9] EXTDCRABUS;
output [0:31] EXTDCRDBUSOUT;
output EXTDCRREAD;
output EXTDCRWRITE;
output ISOCMBRAMEN;
output ISOCMBRAMEVENWRITEEN;
output ISOCMBRAMODDWRITEEN;
output [8:28] ISOCMBRAMRDABUS;
output [8:28] ISOCMBRAMWRABUS;
output [0:31] ISOCMBRAMWRDBUS;
output ISOCMDCRBRAMEVENEN;
output ISOCMDCRBRAMODDEN;
output ISOCMDCRBRAMRDSELECT;
input BRAMDSOCMCLK;
input [0:31] BRAMDSOCMRDDBUS;
input BRAMISOCMCLK;
input [0:31] BRAMISOCMDCRRDDBUS;
input [0:63] BRAMISOCMRDDBUS;
input CPMC405CLOCK;
input CPMC405CORECLKINACTIVE;
input CPMC405CPUCLKEN;
input CPMC405JTAGCLKEN;
input CPMC405SYNCBYPASS;
input CPMC405TIMERCLKEN;
input CPMC405TIMERTICK;
input CPMDCRCLK;
input CPMFCMCLK;
input DBGC405DEBUGHALT;
input DBGC405EXTBUSHOLDACK;
input DBGC405UNCONDDEBUGEVENT;
input [0:7] DSARCVALUE;
input [0:7] DSCNTLVALUE;
input DSOCMRWCOMPLETE;
input EICC405CRITINPUTIRQ;
input EICC405EXTINPUTIRQ;
input EMACDCRACK;
input [0:31] EMACDCRDBUS;
input EXTDCRACK;
input [0:31] EXTDCRDBUSIN;
input [0:3] FCMAPUCR;
input FCMAPUDCDCREN;
input FCMAPUDCDFORCEALIGN;
input FCMAPUDCDFORCEBESTEERING;
input FCMAPUDCDFPUOP;
input FCMAPUDCDGPRWRITE;
input FCMAPUDCDLDSTBYTE;
input FCMAPUDCDLDSTDW;
input FCMAPUDCDLDSTHW;
input FCMAPUDCDLDSTQW;
input FCMAPUDCDLDSTWD;
input FCMAPUDCDLOAD;
input FCMAPUDCDPRIVOP;
input FCMAPUDCDRAEN;
input FCMAPUDCDRBEN;
input FCMAPUDCDSTORE;
input FCMAPUDCDTRAPBE;
input FCMAPUDCDTRAPLE;
input FCMAPUDCDUPDATE;
input FCMAPUDCDXERCAEN;
input FCMAPUDCDXEROVEN;
input FCMAPUDECODEBUSY;
input FCMAPUDONE;
input FCMAPUEXCEPTION;
input FCMAPUEXEBLOCKINGMCO;
input [0:2] FCMAPUEXECRFIELD;
input FCMAPUEXENONBLOCKINGMCO;
input FCMAPUINSTRACK;
input FCMAPULOADWAIT;
input [0:31] FCMAPURESULT;
input FCMAPURESULTVALID;
input FCMAPUSLEEPNOTREADY;
input FCMAPUXERCA;
input FCMAPUXEROV;
input [0:7] ISARCVALUE;
input [0:7] ISCNTLVALUE;
input JTGC405BNDSCANTDO;
input JTGC405TCK;
input JTGC405TDI;
input JTGC405TMS;
input JTGC405TRSTNEG;
input MCBCPUCLKEN;
input MCBJTAGEN;
input MCBTIMEREN;
input MCPPCRST;
input PLBC405DCUADDRACK;
input PLBC405DCUBUSY;
input PLBC405DCUERR;
input PLBC405DCURDDACK;
input [0:63] PLBC405DCURDDBUS;
input [1:3] PLBC405DCURDWDADDR;
input PLBC405DCUSSIZE1;
input PLBC405DCUWRDACK;
input PLBC405ICUADDRACK;
input PLBC405ICUBUSY;
input PLBC405ICUERR;
input PLBC405ICURDDACK;
input [0:63] PLBC405ICURDDBUS;
input [1:3] PLBC405ICURDWDADDR;
input PLBC405ICUSSIZE1;
input PLBCLK;
input RSTC405RESETCHIP;
input RSTC405RESETCORE;
input RSTC405RESETSYS;
input [0:15] TIEAPUCONTROL;
input [0:23] TIEAPUUDI1;
input [0:23] TIEAPUUDI2;
input [0:23] TIEAPUUDI3;
input [0:23] TIEAPUUDI4;
input [0:23] TIEAPUUDI5;
input [0:23] TIEAPUUDI6;
input [0:23] TIEAPUUDI7;
input [0:23] TIEAPUUDI8;
input TIEC405DETERMINISTICMULT;
input TIEC405DISOPERANDFWD;
input TIEC405MMUEN;
input [0:5] TIEDCRADDR;
input TIEPVRBIT10;
input TIEPVRBIT11;
input TIEPVRBIT28;
input TIEPVRBIT29;
input TIEPVRBIT30;
input TIEPVRBIT31;
input TIEPVRBIT8;
input TIEPVRBIT9;
input TRCC405TRACEDISABLE;
input TRCC405TRIGGEREVENTIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PPC405 (C405CPMCORESLEEPREQ, C405CPMMSRCE, C405CPMMSREE, C405CPMTIMERIRQ, C405CPMTIMERRESETREQ, C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, C405DBGWBIAR, C405DCRABUS, C405DCRDBUSOUT, C405DCRREAD, C405DCRWRITE, C405JTGCAPTUREDR, C405JTGEXTEST, C405JTGPGMOUT, C405JTGSHIFTDR, C405JTGTDO, C405JTGTDOEN, C405JTGUPDATEDR, C405PLBDCUABORT, C405PLBDCUABUS, C405PLBDCUBE, C405PLBDCUCACHEABLE, C405PLBDCUGUARDED, C405PLBDCUPRIORITY, C405PLBDCUREQUEST, C405PLBDCURNW, C405PLBDCUSIZE2, C405PLBDCUU0ATTR, C405PLBDCUWRDBUS, C405PLBDCUWRITETHRU, C405PLBICUABORT, C405PLBICUABUS, C405PLBICUCACHEABLE, C405PLBICUPRIORITY, C405PLBICUREQUEST, C405PLBICUSIZE, C405PLBICUU0ATTR, C405RSTCHIPRESETREQ, C405RSTCORERESETREQ, C405RSTSYSRESETREQ, C405TRCCYCLE, C405TRCEVENEXECUTIONSTATUS, C405TRCODDEXECUTIONSTATUS, C405TRCTRACESTATUS, C405TRCTRIGGEREVENTOUT, C405TRCTRIGGEREVENTTYPE, C405XXXMACHINECHECK, DSOCMBRAMABUS, DSOCMBRAMBYTEWRITE, DSOCMBRAMEN, DSOCMBRAMWRDBUS, DSOCMBUSY, ISOCMBRAMEN, ISOCMBRAMEVENWRITEEN, ISOCMBRAMODDWRITEEN, ISOCMBRAMRDABUS, ISOCMBRAMWRABUS, ISOCMBRAMWRDBUS, BRAMDSOCMCLK, BRAMDSOCMRDDBUS, BRAMISOCMCLK, BRAMISOCMRDDBUS, CPMC405CLOCK, CPMC405CORECLKINACTIVE, CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405TIMERCLKEN, CPMC405TIMERTICK, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT, DCRC405ACK, DCRC405DBUSIN, DSARCVALUE, DSCNTLVALUE, EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ, ISARCVALUE, ISCNTLVALUE, JTGC405BNDSCANTDO, JTGC405TCK, JTGC405TDI, JTGC405TMS, JTGC405TRSTNEG, MCBCPUCLKEN, MCBJTAGEN, MCBTIMEREN, MCPPCRST, PLBC405DCUADDRACK, PLBC405DCUBUSY, PLBC405DCUERR, PLBC405DCURDDACK, PLBC405DCURDDBUS, PLBC405DCURDWDADDR, PLBC405DCUSSIZE1, PLBC405DCUWRDACK, PLBC405ICUADDRACK, PLBC405ICUBUSY, PLBC405ICUERR, PLBC405ICURDDACK, PLBC405ICURDDBUS, PLBC405ICURDWDADDR, PLBC405ICUSSIZE1, PLBCLK, RSTC405RESETCHIP, RSTC405RESETCORE, RSTC405RESETSYS, TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD, TIEC405MMUEN, TIEDSOCMDCRADDR, TIEISOCMDCRADDR, TRCC405TRACEDISABLE, TRCC405TRIGGEREVENTIN);
parameter PPCUSER = 4'b0000;
output C405CPMCORESLEEPREQ;
output C405CPMMSRCE;
output C405CPMMSREE;
output C405CPMTIMERIRQ;
output C405CPMTIMERRESETREQ;
output C405DBGMSRWE;
output C405DBGSTOPACK;
output C405DBGWBCOMPLETE;
output C405DBGWBFULL;
output [0:29] C405DBGWBIAR;
output [0:9] C405DCRABUS;
output [0:31] C405DCRDBUSOUT;
output C405DCRREAD;
output C405DCRWRITE;
output C405JTGCAPTUREDR;
output C405JTGEXTEST;
output C405JTGPGMOUT;
output C405JTGSHIFTDR;
output C405JTGTDO;
output C405JTGTDOEN;
output C405JTGUPDATEDR;
output C405PLBDCUABORT;
output [0:31] C405PLBDCUABUS;
output [0:7] C405PLBDCUBE;
output C405PLBDCUCACHEABLE;
output C405PLBDCUGUARDED;
output [0:1] C405PLBDCUPRIORITY;
output C405PLBDCUREQUEST;
output C405PLBDCURNW;
output C405PLBDCUSIZE2;
output C405PLBDCUU0ATTR;
output [0:63] C405PLBDCUWRDBUS;
output C405PLBDCUWRITETHRU;
output C405PLBICUABORT;
output [0:29] C405PLBICUABUS;
output C405PLBICUCACHEABLE;
output [0:1] C405PLBICUPRIORITY;
output C405PLBICUREQUEST;
output [2:3] C405PLBICUSIZE;
output C405PLBICUU0ATTR;
output C405RSTCHIPRESETREQ;
output C405RSTCORERESETREQ;
output C405RSTSYSRESETREQ;
output C405TRCCYCLE;
output [0:1] C405TRCEVENEXECUTIONSTATUS;
output [0:1] C405TRCODDEXECUTIONSTATUS;
output [0:3] C405TRCTRACESTATUS;
output C405TRCTRIGGEREVENTOUT;
output [0:10] C405TRCTRIGGEREVENTTYPE;
output C405XXXMACHINECHECK;
output [8:29] DSOCMBRAMABUS;
output [0:3] DSOCMBRAMBYTEWRITE;
output DSOCMBRAMEN;
output [0:31] DSOCMBRAMWRDBUS;
output DSOCMBUSY;
output ISOCMBRAMEN;
output ISOCMBRAMEVENWRITEEN;
output ISOCMBRAMODDWRITEEN;
output [8:28] ISOCMBRAMRDABUS;
output [8:28] ISOCMBRAMWRABUS;
output [0:31] ISOCMBRAMWRDBUS;
input BRAMDSOCMCLK;
input [0:31] BRAMDSOCMRDDBUS;
input BRAMISOCMCLK;
input [0:63] BRAMISOCMRDDBUS;
input CPMC405CLOCK;
input CPMC405CORECLKINACTIVE;
input CPMC405CPUCLKEN;
input CPMC405JTAGCLKEN;
input CPMC405TIMERCLKEN;
input CPMC405TIMERTICK;
input DBGC405DEBUGHALT;
input DBGC405EXTBUSHOLDACK;
input DBGC405UNCONDDEBUGEVENT;
input DCRC405ACK;
input [0:31] DCRC405DBUSIN;
input [0:7] DSARCVALUE;
input [0:7] DSCNTLVALUE;
input EICC405CRITINPUTIRQ;
input EICC405EXTINPUTIRQ;
input [0:7] ISARCVALUE;
input [0:7] ISCNTLVALUE;
input JTGC405BNDSCANTDO;
input JTGC405TCK;
input JTGC405TDI;
input JTGC405TMS;
input JTGC405TRSTNEG;
input MCBCPUCLKEN;
input MCBJTAGEN;
input MCBTIMEREN;
input MCPPCRST;
input PLBC405DCUADDRACK;
input PLBC405DCUBUSY;
input PLBC405DCUERR;
input PLBC405DCURDDACK;
input [0:63] PLBC405DCURDDBUS;
input [1:3] PLBC405DCURDWDADDR;
input PLBC405DCUSSIZE1;
input PLBC405DCUWRDACK;
input PLBC405ICUADDRACK;
input PLBC405ICUBUSY;
input PLBC405ICUERR;
input PLBC405ICURDDACK;
input [0:63] PLBC405ICURDDBUS;
input [1:3] PLBC405ICURDWDADDR;
input PLBC405ICUSSIZE1;
input PLBCLK;
input RSTC405RESETCHIP;
input RSTC405RESETCORE;
input RSTC405RESETSYS;
input TIEC405DETERMINISTICMULT;
input TIEC405DISOPERANDFWD;
input TIEC405MMUEN;
input [0:7] TIEDSOCMDCRADDR;
input [0:7] TIEISOCMDCRADDR;
input TRCC405TRACEDISABLE;
input TRCC405TRIGGEREVENTIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PPC440 (APUFCMDECFPUOP, APUFCMDECLDSTXFERSIZE, APUFCMDECLOAD, APUFCMDECNONAUTON, APUFCMDECSTORE, APUFCMDECUDI, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRUCTION, APUFCMINSTRVALID, APUFCMLOADBYTEADDR, APUFCMLOADDATA, APUFCMLOADDVALID, APUFCMMSRFE0, APUFCMMSRFE1, APUFCMNEXTINSTRREADY, APUFCMOPERANDVALID, APUFCMRADATA, APUFCMRBDATA, APUFCMWRITEBACKOK, C440CPMCORESLEEPREQ, C440CPMDECIRPTREQ, C440CPMFITIRPTREQ, C440CPMMSRCE, C440CPMMSREE, C440CPMTIMERRESETREQ, C440CPMWDIRPTREQ, C440DBGSYSTEMCONTROL, C440JTGTDO, C440JTGTDOEN, C440MACHINECHECK, C440RSTCHIPRESETREQ, C440RSTCORERESETREQ, C440RSTSYSTEMRESETREQ, C440TRCBRANCHSTATUS, C440TRCCYCLE, C440TRCEXECUTIONSTATUS, C440TRCTRACESTATUS, C440TRCTRIGGEREVENTOUT, C440TRCTRIGGEREVENTTYPE, DMA0LLRSTENGINEACK, DMA0LLRXDSTRDYN, DMA0LLTXD, DMA0LLTXEOFN, DMA0LLTXEOPN, DMA0LLTXREM, DMA0LLTXSOFN, DMA0LLTXSOPN, DMA0LLTXSRCRDYN, DMA0RXIRQ, DMA0TXIRQ, DMA1LLRSTENGINEACK, DMA1LLRXDSTRDYN, DMA1LLTXD, DMA1LLTXEOFN, DMA1LLTXEOPN, DMA1LLTXREM, DMA1LLTXSOFN, DMA1LLTXSOPN, DMA1LLTXSRCRDYN, DMA1RXIRQ, DMA1TXIRQ, DMA2LLRSTENGINEACK, DMA2LLRXDSTRDYN, DMA2LLTXD, DMA2LLTXEOFN, DMA2LLTXEOPN, DMA2LLTXREM, DMA2LLTXSOFN, DMA2LLTXSOPN, DMA2LLTXSRCRDYN, DMA2RXIRQ, DMA2TXIRQ, DMA3LLRSTENGINEACK, DMA3LLRXDSTRDYN, DMA3LLTXD, DMA3LLTXEOFN, DMA3LLTXEOPN, DMA3LLTXREM, DMA3LLTXSOFN, DMA3LLTXSOPN, DMA3LLTXSRCRDYN, DMA3RXIRQ, DMA3TXIRQ, MIMCADDRESS, MIMCADDRESSVALID, MIMCBANKCONFLICT, MIMCBYTEENABLE, MIMCREADNOTWRITE, MIMCROWCONFLICT, MIMCWRITEDATA, MIMCWRITEDATAVALID, PPCCPMINTERCONNECTBUSY, PPCDMDCRABUS, PPCDMDCRDBUSOUT, PPCDMDCRREAD, PPCDMDCRUABUS, PPCDMDCRWRITE, PPCDSDCRACK, PPCDSDCRDBUSIN, PPCDSDCRTIMEOUTWAIT, PPCEICINTERCONNECTIRQ, PPCMPLBABORT, PPCMPLBABUS, PPCMPLBBE, PPCMPLBBUSLOCK, PPCMPLBLOCKERR, PPCMPLBPRIORITY, PPCMPLBRDBURST, PPCMPLBREQUEST, PPCMPLBRNW, PPCMPLBSIZE, PPCMPLBTATTRIBUTE, PPCMPLBTYPE, PPCMPLBUABUS, PPCMPLBWRBURST, PPCMPLBWRDBUS, PPCS0PLBADDRACK, PPCS0PLBMBUSY, PPCS0PLBMIRQ, PPCS0PLBMRDERR, PPCS0PLBMWRERR, PPCS0PLBRDBTERM, PPCS0PLBRDCOMP, PPCS0PLBRDDACK, PPCS0PLBRDDBUS, PPCS0PLBRDWDADDR, PPCS0PLBREARBITRATE, PPCS0PLBSSIZE, PPCS0PLBWAIT, PPCS0PLBWRBTERM, PPCS0PLBWRCOMP, PPCS0PLBWRDACK, PPCS1PLBADDRACK, PPCS1PLBMBUSY, PPCS1PLBMIRQ, PPCS1PLBMRDERR, PPCS1PLBMWRERR, PPCS1PLBRDBTERM, PPCS1PLBRDCOMP, PPCS1PLBRDDACK, PPCS1PLBRDDBUS, PPCS1PLBRDWDADDR, PPCS1PLBREARBITRATE, PPCS1PLBSSIZE, PPCS1PLBWAIT, PPCS1PLBWRBTERM, PPCS1PLBWRCOMP, PPCS1PLBWRDACK, CPMC440CLK, CPMC440CLKEN, CPMC440CORECLOCKINACTIVE, CPMC440TIMERCLOCK, CPMDCRCLK, CPMDMA0LLCLK, CPMDMA1LLCLK, CPMDMA2LLCLK, CPMDMA3LLCLK, CPMFCMCLK, CPMINTERCONNECTCLK, CPMINTERCONNECTCLKEN, CPMINTERCONNECTCLKNTO1, CPMMCCLK, CPMPPCMPLBCLK, CPMPPCS0PLBCLK, CPMPPCS1PLBCLK, DBGC440DEBUGHALT, DBGC440SYSTEMSTATUS, DBGC440UNCONDDEBUGEVENT, DCRPPCDMACK, DCRPPCDMDBUSIN, DCRPPCDMTIMEOUTWAIT, DCRPPCDSABUS, DCRPPCDSDBUSOUT, DCRPPCDSREAD, DCRPPCDSWRITE, EICC440CRITIRQ, EICC440EXTIRQ, FCMAPUCONFIRMINSTR, FCMAPUCR, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUFPSCRFEX, FCMAPURESULT, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, FCMAPUSTOREDATA, JTGC440TCK, JTGC440TDI, JTGC440TMS, JTGC440TRSTNEG, LLDMA0RSTENGINEREQ, LLDMA0RXD, LLDMA0RXEOFN, LLDMA0RXEOPN, LLDMA0RXREM, LLDMA0RXSOFN, LLDMA0RXSOPN, LLDMA0RXSRCRDYN, LLDMA0TXDSTRDYN, LLDMA1RSTENGINEREQ, LLDMA1RXD, LLDMA1RXEOFN, LLDMA1RXEOPN, LLDMA1RXREM, LLDMA1RXSOFN, LLDMA1RXSOPN, LLDMA1RXSRCRDYN, LLDMA1TXDSTRDYN, LLDMA2RSTENGINEREQ, LLDMA2RXD, LLDMA2RXEOFN, LLDMA2RXEOPN, LLDMA2RXREM, LLDMA2RXSOFN, LLDMA2RXSOPN, LLDMA2RXSRCRDYN, LLDMA2TXDSTRDYN, LLDMA3RSTENGINEREQ, LLDMA3RXD, LLDMA3RXEOFN, LLDMA3RXEOPN, LLDMA3RXREM, LLDMA3RXSOFN, LLDMA3RXSOPN, LLDMA3RXSRCRDYN, LLDMA3TXDSTRDYN, MCMIADDRREADYTOACCEPT, MCMIREADDATA, MCMIREADDATAERR, MCMIREADDATAVALID, PLBPPCMADDRACK, PLBPPCMMBUSY, PLBPPCMMIRQ, PLBPPCMMRDERR, PLBPPCMMWRERR, PLBPPCMRDBTERM, PLBPPCMRDDACK, PLBPPCMRDDBUS, PLBPPCMRDPENDPRI, PLBPPCMRDPENDREQ, PLBPPCMRDWDADDR, PLBPPCMREARBITRATE, PLBPPCMREQPRI, PLBPPCMSSIZE, PLBPPCMTIMEOUT, PLBPPCMWRBTERM, PLBPPCMWRDACK, PLBPPCMWRPENDPRI, PLBPPCMWRPENDREQ, PLBPPCS0ABORT, PLBPPCS0ABUS, PLBPPCS0BE, PLBPPCS0BUSLOCK, PLBPPCS0LOCKERR, PLBPPCS0MASTERID, PLBPPCS0MSIZE, PLBPPCS0PAVALID, PLBPPCS0RDBURST, PLBPPCS0RDPENDPRI, PLBPPCS0RDPENDREQ, PLBPPCS0RDPRIM, PLBPPCS0REQPRI, PLBPPCS0RNW, PLBPPCS0SAVALID, PLBPPCS0SIZE, PLBPPCS0TATTRIBUTE, PLBPPCS0TYPE, PLBPPCS0UABUS, PLBPPCS0WRBURST, PLBPPCS0WRDBUS, PLBPPCS0WRPENDPRI, PLBPPCS0WRPENDREQ, PLBPPCS0WRPRIM, PLBPPCS1ABORT, PLBPPCS1ABUS, PLBPPCS1BE, PLBPPCS1BUSLOCK, PLBPPCS1LOCKERR, PLBPPCS1MASTERID, PLBPPCS1MSIZE, PLBPPCS1PAVALID, PLBPPCS1RDBURST, PLBPPCS1RDPENDPRI, PLBPPCS1RDPENDREQ, PLBPPCS1RDPRIM, PLBPPCS1REQPRI, PLBPPCS1RNW, PLBPPCS1SAVALID, PLBPPCS1SIZE, PLBPPCS1TATTRIBUTE, PLBPPCS1TYPE, PLBPPCS1UABUS, PLBPPCS1WRBURST, PLBPPCS1WRDBUS, PLBPPCS1WRPENDPRI, PLBPPCS1WRPENDREQ, PLBPPCS1WRPRIM, RSTC440RESETCHIP, RSTC440RESETCORE, RSTC440RESETSYSTEM, TIEC440DCURDLDCACHEPLBPRIO, TIEC440DCURDNONCACHEPLBPRIO, TIEC440DCURDTOUCHPLBPRIO, TIEC440DCURDURGENTPLBPRIO, TIEC440DCUWRFLUSHPLBPRIO, TIEC440DCUWRSTOREPLBPRIO, TIEC440DCUWRURGENTPLBPRIO, TIEC440ENDIANRESET, TIEC440ERPNRESET, TIEC440ICURDFETCHPLBPRIO, TIEC440ICURDSPECPLBPRIO, TIEC440ICURDTOUCHPLBPRIO, TIEC440PIR, TIEC440PVR, TIEC440USERRESET, TIEDCRBASEADDR, TRCC440TRACEDISABLE, TRCC440TRIGGEREVENTIN);
parameter CLOCK_DELAY = "FALSE";
parameter DCR_AUTOLOCK_ENABLE = "TRUE";
parameter PPCDM_ASYNCMODE = "FALSE";
parameter PPCDS_ASYNCMODE = "FALSE";
parameter PPCS0_WIDTH_128N64 = "TRUE";
parameter PPCS1_WIDTH_128N64 = "TRUE";
parameter [0:16] APU_CONTROL = 17'h02000;
parameter [0:23] APU_UDI0 = 24'h000000;
parameter [0:23] APU_UDI1 = 24'h000000;
parameter [0:23] APU_UDI10 = 24'h000000;
parameter [0:23] APU_UDI11 = 24'h000000;
parameter [0:23] APU_UDI12 = 24'h000000;
parameter [0:23] APU_UDI13 = 24'h000000;
parameter [0:23] APU_UDI14 = 24'h000000;
parameter [0:23] APU_UDI15 = 24'h000000;
parameter [0:23] APU_UDI2 = 24'h000000;
parameter [0:23] APU_UDI3 = 24'h000000;
parameter [0:23] APU_UDI4 = 24'h000000;
parameter [0:23] APU_UDI5 = 24'h000000;
parameter [0:23] APU_UDI6 = 24'h000000;
parameter [0:23] APU_UDI7 = 24'h000000;
parameter [0:23] APU_UDI8 = 24'h000000;
parameter [0:23] APU_UDI9 = 24'h000000;
parameter [0:31] DMA0_RXCHANNELCTRL = 32'h01010000;
parameter [0:31] DMA0_TXCHANNELCTRL = 32'h01010000;
parameter [0:31] DMA1_RXCHANNELCTRL = 32'h01010000;
parameter [0:31] DMA1_TXCHANNELCTRL = 32'h01010000;
parameter [0:31] DMA2_RXCHANNELCTRL = 32'h01010000;
parameter [0:31] DMA2_TXCHANNELCTRL = 32'h01010000;
parameter [0:31] DMA3_RXCHANNELCTRL = 32'h01010000;
parameter [0:31] DMA3_TXCHANNELCTRL = 32'h01010000;
parameter [0:31] INTERCONNECT_IMASK = 32'hFFFFFFFF;
parameter [0:31] INTERCONNECT_TMPL_SEL = 32'h3FFFFFFF;
parameter [0:31] MI_ARBCONFIG = 32'h00432010;
parameter [0:31] MI_BANKCONFLICT_MASK = 32'h00000000;
parameter [0:31] MI_CONTROL = 32'h0000008F;
parameter [0:31] MI_ROWCONFLICT_MASK = 32'h00000000;
parameter [0:31] PPCM_ARBCONFIG = 32'h00432010;
parameter [0:31] PPCM_CONTROL = 32'h8000009F;
parameter [0:31] PPCM_COUNTER = 32'h00000500;
parameter [0:31] PPCS0_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
parameter [0:31] PPCS0_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
parameter [0:31] PPCS0_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
parameter [0:31] PPCS0_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
parameter [0:31] PPCS0_CONTROL = 32'h8033336C;
parameter [0:31] PPCS1_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
parameter [0:31] PPCS1_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
parameter [0:31] PPCS1_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
parameter [0:31] PPCS1_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
parameter [0:31] PPCS1_CONTROL = 32'h8033336C;
parameter [0:31] XBAR_ADDRMAP_TMPL0 = 32'hFFFF0000;
parameter [0:31] XBAR_ADDRMAP_TMPL1 = 32'h00000000;
parameter [0:31] XBAR_ADDRMAP_TMPL2 = 32'h00000000;
parameter [0:31] XBAR_ADDRMAP_TMPL3 = 32'h00000000;
parameter [0:7] DMA0_CONTROL = 8'h00;
parameter [0:7] DMA1_CONTROL = 8'h00;
parameter [0:7] DMA2_CONTROL = 8'h00;
parameter [0:7] DMA3_CONTROL = 8'h00;
parameter [0:9] DMA0_RXIRQTIMER = 10'h3FF;
parameter [0:9] DMA0_TXIRQTIMER = 10'h3FF;
parameter [0:9] DMA1_RXIRQTIMER = 10'h3FF;
parameter [0:9] DMA1_TXIRQTIMER = 10'h3FF;
parameter [0:9] DMA2_RXIRQTIMER = 10'h3FF;
parameter [0:9] DMA2_TXIRQTIMER = 10'h3FF;
parameter [0:9] DMA3_RXIRQTIMER = 10'h3FF;
parameter [0:9] DMA3_TXIRQTIMER = 10'h3FF;
output APUFCMDECFPUOP;
output [0:2] APUFCMDECLDSTXFERSIZE;
output APUFCMDECLOAD;
output APUFCMDECNONAUTON;
output APUFCMDECSTORE;
output [0:3] APUFCMDECUDI;
output APUFCMDECUDIVALID;
output APUFCMENDIAN;
output APUFCMFLUSH;
output [0:31] APUFCMINSTRUCTION;
output APUFCMINSTRVALID;
output [0:3] APUFCMLOADBYTEADDR;
output [0:127] APUFCMLOADDATA;
output APUFCMLOADDVALID;
output APUFCMMSRFE0;
output APUFCMMSRFE1;
output APUFCMNEXTINSTRREADY;
output APUFCMOPERANDVALID;
output [0:31] APUFCMRADATA;
output [0:31] APUFCMRBDATA;
output APUFCMWRITEBACKOK;
output C440CPMCORESLEEPREQ;
output C440CPMDECIRPTREQ;
output C440CPMFITIRPTREQ;
output C440CPMMSRCE;
output C440CPMMSREE;
output C440CPMTIMERRESETREQ;
output C440CPMWDIRPTREQ;
output [0:7] C440DBGSYSTEMCONTROL;
output C440JTGTDO;
output C440JTGTDOEN;
output C440MACHINECHECK;
output C440RSTCHIPRESETREQ;
output C440RSTCORERESETREQ;
output C440RSTSYSTEMRESETREQ;
output [0:2] C440TRCBRANCHSTATUS;
output C440TRCCYCLE;
output [0:4] C440TRCEXECUTIONSTATUS;
output [0:6] C440TRCTRACESTATUS;
output C440TRCTRIGGEREVENTOUT;
output [0:13] C440TRCTRIGGEREVENTTYPE;
output DMA0LLRSTENGINEACK;
output DMA0LLRXDSTRDYN;
output [0:31] DMA0LLTXD;
output DMA0LLTXEOFN;
output DMA0LLTXEOPN;
output [0:3] DMA0LLTXREM;
output DMA0LLTXSOFN;
output DMA0LLTXSOPN;
output DMA0LLTXSRCRDYN;
output DMA0RXIRQ;
output DMA0TXIRQ;
output DMA1LLRSTENGINEACK;
output DMA1LLRXDSTRDYN;
output [0:31] DMA1LLTXD;
output DMA1LLTXEOFN;
output DMA1LLTXEOPN;
output [0:3] DMA1LLTXREM;
output DMA1LLTXSOFN;
output DMA1LLTXSOPN;
output DMA1LLTXSRCRDYN;
output DMA1RXIRQ;
output DMA1TXIRQ;
output DMA2LLRSTENGINEACK;
output DMA2LLRXDSTRDYN;
output [0:31] DMA2LLTXD;
output DMA2LLTXEOFN;
output DMA2LLTXEOPN;
output [0:3] DMA2LLTXREM;
output DMA2LLTXSOFN;
output DMA2LLTXSOPN;
output DMA2LLTXSRCRDYN;
output DMA2RXIRQ;
output DMA2TXIRQ;
output DMA3LLRSTENGINEACK;
output DMA3LLRXDSTRDYN;
output [0:31] DMA3LLTXD;
output DMA3LLTXEOFN;
output DMA3LLTXEOPN;
output [0:3] DMA3LLTXREM;
output DMA3LLTXSOFN;
output DMA3LLTXSOPN;
output DMA3LLTXSRCRDYN;
output DMA3RXIRQ;
output DMA3TXIRQ;
output [0:35] MIMCADDRESS;
output MIMCADDRESSVALID;
output MIMCBANKCONFLICT;
output [0:15] MIMCBYTEENABLE;
output MIMCREADNOTWRITE;
output MIMCROWCONFLICT;
output [0:127] MIMCWRITEDATA;
output MIMCWRITEDATAVALID;
output PPCCPMINTERCONNECTBUSY;
output [0:9] PPCDMDCRABUS;
output [0:31] PPCDMDCRDBUSOUT;
output PPCDMDCRREAD;
output [20:21] PPCDMDCRUABUS;
output PPCDMDCRWRITE;
output PPCDSDCRACK;
output [0:31] PPCDSDCRDBUSIN;
output PPCDSDCRTIMEOUTWAIT;
output PPCEICINTERCONNECTIRQ;
output PPCMPLBABORT;
output [0:31] PPCMPLBABUS;
output [0:15] PPCMPLBBE;
output PPCMPLBBUSLOCK;
output PPCMPLBLOCKERR;
output [0:1] PPCMPLBPRIORITY;
output PPCMPLBRDBURST;
output PPCMPLBREQUEST;
output PPCMPLBRNW;
output [0:3] PPCMPLBSIZE;
output [0:15] PPCMPLBTATTRIBUTE;
output [0:2] PPCMPLBTYPE;
output [28:31] PPCMPLBUABUS;
output PPCMPLBWRBURST;
output [0:127] PPCMPLBWRDBUS;
output PPCS0PLBADDRACK;
output [0:3] PPCS0PLBMBUSY;
output [0:3] PPCS0PLBMIRQ;
output [0:3] PPCS0PLBMRDERR;
output [0:3] PPCS0PLBMWRERR;
output PPCS0PLBRDBTERM;
output PPCS0PLBRDCOMP;
output PPCS0PLBRDDACK;
output [0:127] PPCS0PLBRDDBUS;
output [0:3] PPCS0PLBRDWDADDR;
output PPCS0PLBREARBITRATE;
output [0:1] PPCS0PLBSSIZE;
output PPCS0PLBWAIT;
output PPCS0PLBWRBTERM;
output PPCS0PLBWRCOMP;
output PPCS0PLBWRDACK;
output PPCS1PLBADDRACK;
output [0:3] PPCS1PLBMBUSY;
output [0:3] PPCS1PLBMIRQ;
output [0:3] PPCS1PLBMRDERR;
output [0:3] PPCS1PLBMWRERR;
output PPCS1PLBRDBTERM;
output PPCS1PLBRDCOMP;
output PPCS1PLBRDDACK;
output [0:127] PPCS1PLBRDDBUS;
output [0:3] PPCS1PLBRDWDADDR;
output PPCS1PLBREARBITRATE;
output [0:1] PPCS1PLBSSIZE;
output PPCS1PLBWAIT;
output PPCS1PLBWRBTERM;
output PPCS1PLBWRCOMP;
output PPCS1PLBWRDACK;
input CPMC440CLK;
input CPMC440CLKEN;
input CPMC440CORECLOCKINACTIVE;
input CPMC440TIMERCLOCK;
input CPMDCRCLK;
input CPMDMA0LLCLK;
input CPMDMA1LLCLK;
input CPMDMA2LLCLK;
input CPMDMA3LLCLK;
input CPMFCMCLK;
input CPMINTERCONNECTCLK;
input CPMINTERCONNECTCLKEN;
input CPMINTERCONNECTCLKNTO1;
input CPMMCCLK;
input CPMPPCMPLBCLK;
input CPMPPCS0PLBCLK;
input CPMPPCS1PLBCLK;
input DBGC440DEBUGHALT;
input [0:4] DBGC440SYSTEMSTATUS;
input DBGC440UNCONDDEBUGEVENT;
input DCRPPCDMACK;
input [0:31] DCRPPCDMDBUSIN;
input DCRPPCDMTIMEOUTWAIT;
input [0:9] DCRPPCDSABUS;
input [0:31] DCRPPCDSDBUSOUT;
input DCRPPCDSREAD;
input DCRPPCDSWRITE;
input EICC440CRITIRQ;
input EICC440EXTIRQ;
input FCMAPUCONFIRMINSTR;
input [0:3] FCMAPUCR;
input FCMAPUDONE;
input FCMAPUEXCEPTION;
input FCMAPUFPSCRFEX;
input [0:31] FCMAPURESULT;
input FCMAPURESULTVALID;
input FCMAPUSLEEPNOTREADY;
input [0:127] FCMAPUSTOREDATA;
input JTGC440TCK;
input JTGC440TDI;
input JTGC440TMS;
input JTGC440TRSTNEG;
input LLDMA0RSTENGINEREQ;
input [0:31] LLDMA0RXD;
input LLDMA0RXEOFN;
input LLDMA0RXEOPN;
input [0:3] LLDMA0RXREM;
input LLDMA0RXSOFN;
input LLDMA0RXSOPN;
input LLDMA0RXSRCRDYN;
input LLDMA0TXDSTRDYN;
input LLDMA1RSTENGINEREQ;
input [0:31] LLDMA1RXD;
input LLDMA1RXEOFN;
input LLDMA1RXEOPN;
input [0:3] LLDMA1RXREM;
input LLDMA1RXSOFN;
input LLDMA1RXSOPN;
input LLDMA1RXSRCRDYN;
input LLDMA1TXDSTRDYN;
input LLDMA2RSTENGINEREQ;
input [0:31] LLDMA2RXD;
input LLDMA2RXEOFN;
input LLDMA2RXEOPN;
input [0:3] LLDMA2RXREM;
input LLDMA2RXSOFN;
input LLDMA2RXSOPN;
input LLDMA2RXSRCRDYN;
input LLDMA2TXDSTRDYN;
input LLDMA3RSTENGINEREQ;
input [0:31] LLDMA3RXD;
input LLDMA3RXEOFN;
input LLDMA3RXEOPN;
input [0:3] LLDMA3RXREM;
input LLDMA3RXSOFN;
input LLDMA3RXSOPN;
input LLDMA3RXSRCRDYN;
input LLDMA3TXDSTRDYN;
input MCMIADDRREADYTOACCEPT;
input [0:127] MCMIREADDATA;
input MCMIREADDATAERR;
input MCMIREADDATAVALID;
input PLBPPCMADDRACK;
input PLBPPCMMBUSY;
input PLBPPCMMIRQ;
input PLBPPCMMRDERR;
input PLBPPCMMWRERR;
input PLBPPCMRDBTERM;
input PLBPPCMRDDACK;
input [0:127] PLBPPCMRDDBUS;
input [0:1] PLBPPCMRDPENDPRI;
input PLBPPCMRDPENDREQ;
input [0:3] PLBPPCMRDWDADDR;
input PLBPPCMREARBITRATE;
input [0:1] PLBPPCMREQPRI;
input [0:1] PLBPPCMSSIZE;
input PLBPPCMTIMEOUT;
input PLBPPCMWRBTERM;
input PLBPPCMWRDACK;
input [0:1] PLBPPCMWRPENDPRI;
input PLBPPCMWRPENDREQ;
input PLBPPCS0ABORT;
input [0:31] PLBPPCS0ABUS;
input [0:15] PLBPPCS0BE;
input PLBPPCS0BUSLOCK;
input PLBPPCS0LOCKERR;
input [0:1] PLBPPCS0MASTERID;
input [0:1] PLBPPCS0MSIZE;
input PLBPPCS0PAVALID;
input PLBPPCS0RDBURST;
input [0:1] PLBPPCS0RDPENDPRI;
input PLBPPCS0RDPENDREQ;
input PLBPPCS0RDPRIM;
input [0:1] PLBPPCS0REQPRI;
input PLBPPCS0RNW;
input PLBPPCS0SAVALID;
input [0:3] PLBPPCS0SIZE;
input [0:15] PLBPPCS0TATTRIBUTE;
input [0:2] PLBPPCS0TYPE;
input [28:31] PLBPPCS0UABUS;
input PLBPPCS0WRBURST;
input [0:127] PLBPPCS0WRDBUS;
input [0:1] PLBPPCS0WRPENDPRI;
input PLBPPCS0WRPENDREQ;
input PLBPPCS0WRPRIM;
input PLBPPCS1ABORT;
input [0:31] PLBPPCS1ABUS;
input [0:15] PLBPPCS1BE;
input PLBPPCS1BUSLOCK;
input PLBPPCS1LOCKERR;
input [0:1] PLBPPCS1MASTERID;
input [0:1] PLBPPCS1MSIZE;
input PLBPPCS1PAVALID;
input PLBPPCS1RDBURST;
input [0:1] PLBPPCS1RDPENDPRI;
input PLBPPCS1RDPENDREQ;
input PLBPPCS1RDPRIM;
input [0:1] PLBPPCS1REQPRI;
input PLBPPCS1RNW;
input PLBPPCS1SAVALID;
input [0:3] PLBPPCS1SIZE;
input [0:15] PLBPPCS1TATTRIBUTE;
input [0:2] PLBPPCS1TYPE;
input [28:31] PLBPPCS1UABUS;
input PLBPPCS1WRBURST;
input [0:127] PLBPPCS1WRDBUS;
input [0:1] PLBPPCS1WRPENDPRI;
input PLBPPCS1WRPENDREQ;
input PLBPPCS1WRPRIM;
input RSTC440RESETCHIP;
input RSTC440RESETCORE;
input RSTC440RESETSYSTEM;
input [0:1] TIEC440DCURDLDCACHEPLBPRIO;
input [0:1] TIEC440DCURDNONCACHEPLBPRIO;
input [0:1] TIEC440DCURDTOUCHPLBPRIO;
input [0:1] TIEC440DCURDURGENTPLBPRIO;
input [0:1] TIEC440DCUWRFLUSHPLBPRIO;
input [0:1] TIEC440DCUWRSTOREPLBPRIO;
input [0:1] TIEC440DCUWRURGENTPLBPRIO;
input TIEC440ENDIANRESET;
input [0:3] TIEC440ERPNRESET;
input [0:1] TIEC440ICURDFETCHPLBPRIO;
input [0:1] TIEC440ICURDSPECPLBPRIO;
input [0:1] TIEC440ICURDTOUCHPLBPRIO;
input [28:31] TIEC440PIR;
input [28:31] TIEC440PVR;
input [0:3] TIEC440USERRESET;
input [0:1] TIEDCRBASEADDR;
input TRCC440TRACEDISABLE;
input TRCC440TRIGGEREVENTIN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PULLDOWN (O);
output O;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module PULLUP (O);
output O;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM128X1D (DPO, SPO, A, D, DPRA, WCLK, WE);
parameter INIT = 128'h0;
output DPO;
output SPO;
input [6:0] A;
input D;
input [6:0] DPRA;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM128X1S_1 (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE);
parameter INIT = 128'h00000000000000000000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM128X1S (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE);
parameter INIT = 128'h00000000000000000000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM16X1D_1 (DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE);
parameter INIT = 16'h0000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input D;
input DPRA0;
input DPRA1;
input DPRA2;
input DPRA3;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM16X1D (DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE);
parameter INIT = 16'h0000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input D;
input DPRA0;
input DPRA1;
input DPRA2;
input DPRA3;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM16X1S_1 (O, A0, A1, A2, A3, D, WCLK, WE);
parameter INIT = 16'h0000;
output O;
input A0;
input A1;
input A2;
input A3;
input D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM16X1S (O, A0, A1, A2, A3, D, WCLK, WE);
parameter INIT = 16'h0000;
output O;
input A0;
input A1;
input A2;
input A3;
input D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM16X2S (O0, O1, A0, A1, A2, A3, D0, D1, WCLK, WE);
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
output O0;
output O1;
input A0;
input A1;
input A2;
input A3;
input D0;
input D1;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM16X4S (O0, O1, O2, O3, A0, A1, A2, A3, D0, D1, D2, D3, WCLK, WE);
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
parameter INIT_02 = 16'h0000;
parameter INIT_03 = 16'h0000;
output O0;
output O1;
output O2;
output O3;
input A0;
input A1;
input A2;
input A3;
input D0;
input D1;
input D2;
input D3;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM16X8S (O, A0, A1, A2, A3, D, WCLK, WE);
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
parameter INIT_02 = 16'h0000;
parameter INIT_03 = 16'h0000;
parameter INIT_04 = 16'h0000;
parameter INIT_05 = 16'h0000;
parameter INIT_06 = 16'h0000;
parameter INIT_07 = 16'h0000;
output [7:0] O;
input A0;
input A1;
input A2;
input A3;
input [7:0] D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM256X1S (O, A, D, WCLK, WE);
parameter INIT = 256'h0;
output O;
input [7:0] A;
input D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM32M (DOA, DOB, DOC, DOD, ADDRA, ADDRB, ADDRC, ADDRD, DIA, DIB, DIC, DID, WCLK, WE);
parameter INIT_A = 64'h0000000000000000;
parameter INIT_B = 64'h0000000000000000;
parameter INIT_C = 64'h0000000000000000;
parameter INIT_D = 64'h0000000000000000;
output [1:0] DOA;
output [1:0] DOB;
output [1:0] DOC;
output [1:0] DOD;
input [4:0] ADDRA;
input [4:0] ADDRB;
input [4:0] ADDRC;
input [4:0] ADDRD;
input [1:0] DIA;
input [1:0] DIB;
input [1:0] DIC;
input [1:0] DID;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM32X1D_1 (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE);
parameter INIT = 32'h00000000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input A4;
input D;
input DPRA0;
input DPRA1;
input DPRA2;
input DPRA3;
input DPRA4;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM32X1D (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE);
parameter INIT = 32'h00000000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input A4;
input D;
input DPRA0;
input DPRA1;
input DPRA2;
input DPRA3;
input DPRA4;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM32X1S_1 (O, A0, A1, A2, A3, A4, D, WCLK, WE);
parameter INIT = 32'h00000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM32X1S (O, A0, A1, A2, A3, A4, D, WCLK, WE);
parameter INIT = 32'h00000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM32X2S (O0, O1, A0, A1, A2, A3, A4, D0, D1, WCLK, WE);
parameter INIT_00 = 32'h00000000;
parameter INIT_01 = 32'h00000000;
output O0;
output O1;
input A0;
input A1;
input A2;
input A3;
input A4;
input D0;
input D1;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM32X4S (O0, O1, O2, O3, A0, A1, A2, A3, A4, D0, D1, D2, D3, WCLK, WE);
parameter INIT_00 = 32'h00000000;
parameter INIT_01 = 32'h00000000;
parameter INIT_02 = 32'h00000000;
parameter INIT_03 = 32'h00000000;
output O0;
output O1;
output O2;
output O3;
input A0;
input A1;
input A2;
input A3;
input A4;
input D0;
input D1;
input D2;
input D3;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM32X8S (O, A0, A1, A2, A3, A4, D, WCLK, WE);
parameter INIT_00 = 32'h00000000;
parameter INIT_01 = 32'h00000000;
parameter INIT_02 = 32'h00000000;
parameter INIT_03 = 32'h00000000;
parameter INIT_04 = 32'h00000000;
parameter INIT_05 = 32'h00000000;
parameter INIT_06 = 32'h00000000;
parameter INIT_07 = 32'h00000000;
output [7:0] O;
input A0;
input A1;
input A2;
input A3;
input A4;
input [7:0] D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM64M (DOA, DOB, DOC, DOD, ADDRA, ADDRB, ADDRC, ADDRD, DIA, DIB, DIC, DID, WCLK, WE);
parameter INIT_A = 64'h0000000000000000;
parameter INIT_B = 64'h0000000000000000;
parameter INIT_C = 64'h0000000000000000;
parameter INIT_D = 64'h0000000000000000;
output DOA;
output DOB;
output DOC;
output DOD;
input [5:0] ADDRA;
input [5:0] ADDRB;
input [5:0] ADDRC;
input [5:0] ADDRD;
input DIA;
input DIB;
input DIC;
input DID;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM64X1D_1 (DPO, SPO, A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE);
parameter INIT = 64'h0000000000000000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D;
input DPRA0;
input DPRA1;
input DPRA2;
input DPRA3;
input DPRA4;
input DPRA5;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM64X1D (DPO, SPO, A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE);
parameter INIT = 64'h0000000000000000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D;
input DPRA0;
input DPRA1;
input DPRA2;
input DPRA3;
input DPRA4;
input DPRA5;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM64X1S_1 (O, A0, A1, A2, A3, A4, A5, D, WCLK, WE);
parameter INIT = 64'h0000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM64X1S (O, A0, A1, A2, A3, A4, A5, D, WCLK, WE);
parameter INIT = 64'h0000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAM64X2S (O0, O1, A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE);
parameter INIT_00 = 64'h0000000000000000;
parameter INIT_01 = 64'h0000000000000000;
output O0;
output O1;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D0;
input D1;
input WCLK;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16BWER (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, RSTA, RSTB, WEA, WEB);
parameter integer DATA_WIDTH_A = 0;
parameter integer DATA_WIDTH_B = 0;
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter RSTTYPE = "SYNC";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [31:0] DOA;
output [31:0] DOB;
output [3:0] DOPA;
output [3:0] DOPB;
input [13:0] ADDRA;
input [13:0] ADDRB;
input CLKA;
input CLKB;
input [31:0] DIA;
input [31:0] DIB;
input [3:0] DIPA;
input [3:0] DIPB;
input ENA;
input ENB;
input REGCEA;
input REGCEB;
input RSTA;
input RSTB;
input [3:0] WEA;
input [3:0] WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16BWE_S18_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INITP_00 = 256'h0;
parameter INITP_01 = 256'h0;
parameter INITP_02 = 256'h0;
parameter INITP_03 = 256'h0;
parameter INITP_04 = 256'h0;
parameter INITP_05 = 256'h0;
parameter INITP_06 = 256'h0;
parameter INITP_07 = 256'h0;
parameter INIT_00 = 256'h0;
parameter INIT_01 = 256'h0;
parameter INIT_02 = 256'h0;
parameter INIT_03 = 256'h0;
parameter INIT_04 = 256'h0;
parameter INIT_05 = 256'h0;
parameter INIT_06 = 256'h0;
parameter INIT_07 = 256'h0;
parameter INIT_08 = 256'h0;
parameter INIT_09 = 256'h0;
parameter INIT_0A = 256'h0;
parameter INIT_0B = 256'h0;
parameter INIT_0C = 256'h0;
parameter INIT_0D = 256'h0;
parameter INIT_0E = 256'h0;
parameter INIT_0F = 256'h0;
parameter INIT_10 = 256'h0;
parameter INIT_11 = 256'h0;
parameter INIT_12 = 256'h0;
parameter INIT_13 = 256'h0;
parameter INIT_14 = 256'h0;
parameter INIT_15 = 256'h0;
parameter INIT_16 = 256'h0;
parameter INIT_17 = 256'h0;
parameter INIT_18 = 256'h0;
parameter INIT_19 = 256'h0;
parameter INIT_1A = 256'h0;
parameter INIT_1B = 256'h0;
parameter INIT_1C = 256'h0;
parameter INIT_1D = 256'h0;
parameter INIT_1E = 256'h0;
parameter INIT_1F = 256'h0;
parameter INIT_20 = 256'h0;
parameter INIT_21 = 256'h0;
parameter INIT_22 = 256'h0;
parameter INIT_23 = 256'h0;
parameter INIT_24 = 256'h0;
parameter INIT_25 = 256'h0;
parameter INIT_26 = 256'h0;
parameter INIT_27 = 256'h0;
parameter INIT_28 = 256'h0;
parameter INIT_29 = 256'h0;
parameter INIT_2A = 256'h0;
parameter INIT_2B = 256'h0;
parameter INIT_2C = 256'h0;
parameter INIT_2D = 256'h0;
parameter INIT_2E = 256'h0;
parameter INIT_2F = 256'h0;
parameter INIT_30 = 256'h0;
parameter INIT_31 = 256'h0;
parameter INIT_32 = 256'h0;
parameter INIT_33 = 256'h0;
parameter INIT_34 = 256'h0;
parameter INIT_35 = 256'h0;
parameter INIT_36 = 256'h0;
parameter INIT_37 = 256'h0;
parameter INIT_38 = 256'h0;
parameter INIT_39 = 256'h0;
parameter INIT_3A = 256'h0;
parameter INIT_3B = 256'h0;
parameter INIT_3C = 256'h0;
parameter INIT_3D = 256'h0;
parameter INIT_3E = 256'h0;
parameter INIT_3F = 256'h0;
parameter INIT_A = 18'h0;
parameter INIT_B = 18'h0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SRVAL_A = 18'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
output [15:0] DOA;
output [15:0] DOB;
output [1:0] DOPA;
output [1:0] DOPB;
input [9:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [15:0] DIA;
input [15:0] DIB;
input [1:0] DIPA;
input [1:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input [1:0] WEA;
input [1:0] WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16BWE_S18_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INITP_00 = 256'h0;
parameter INITP_01 = 256'h0;
parameter INITP_02 = 256'h0;
parameter INITP_03 = 256'h0;
parameter INITP_04 = 256'h0;
parameter INITP_05 = 256'h0;
parameter INITP_06 = 256'h0;
parameter INITP_07 = 256'h0;
parameter INIT_00 = 256'h0;
parameter INIT_01 = 256'h0;
parameter INIT_02 = 256'h0;
parameter INIT_03 = 256'h0;
parameter INIT_04 = 256'h0;
parameter INIT_05 = 256'h0;
parameter INIT_06 = 256'h0;
parameter INIT_07 = 256'h0;
parameter INIT_08 = 256'h0;
parameter INIT_09 = 256'h0;
parameter INIT_0A = 256'h0;
parameter INIT_0B = 256'h0;
parameter INIT_0C = 256'h0;
parameter INIT_0D = 256'h0;
parameter INIT_0E = 256'h0;
parameter INIT_0F = 256'h0;
parameter INIT_10 = 256'h0;
parameter INIT_11 = 256'h0;
parameter INIT_12 = 256'h0;
parameter INIT_13 = 256'h0;
parameter INIT_14 = 256'h0;
parameter INIT_15 = 256'h0;
parameter INIT_16 = 256'h0;
parameter INIT_17 = 256'h0;
parameter INIT_18 = 256'h0;
parameter INIT_19 = 256'h0;
parameter INIT_1A = 256'h0;
parameter INIT_1B = 256'h0;
parameter INIT_1C = 256'h0;
parameter INIT_1D = 256'h0;
parameter INIT_1E = 256'h0;
parameter INIT_1F = 256'h0;
parameter INIT_20 = 256'h0;
parameter INIT_21 = 256'h0;
parameter INIT_22 = 256'h0;
parameter INIT_23 = 256'h0;
parameter INIT_24 = 256'h0;
parameter INIT_25 = 256'h0;
parameter INIT_26 = 256'h0;
parameter INIT_27 = 256'h0;
parameter INIT_28 = 256'h0;
parameter INIT_29 = 256'h0;
parameter INIT_2A = 256'h0;
parameter INIT_2B = 256'h0;
parameter INIT_2C = 256'h0;
parameter INIT_2D = 256'h0;
parameter INIT_2E = 256'h0;
parameter INIT_2F = 256'h0;
parameter INIT_30 = 256'h0;
parameter INIT_31 = 256'h0;
parameter INIT_32 = 256'h0;
parameter INIT_33 = 256'h0;
parameter INIT_34 = 256'h0;
parameter INIT_35 = 256'h0;
parameter INIT_36 = 256'h0;
parameter INIT_37 = 256'h0;
parameter INIT_38 = 256'h0;
parameter INIT_39 = 256'h0;
parameter INIT_3A = 256'h0;
parameter INIT_3B = 256'h0;
parameter INIT_3C = 256'h0;
parameter INIT_3D = 256'h0;
parameter INIT_3E = 256'h0;
parameter INIT_3F = 256'h0;
parameter INIT_A = 18'h0;
parameter INIT_B = 9'h0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SRVAL_A = 18'h0;
parameter SRVAL_B = 9'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
output [15:0] DOA;
output [7:0] DOB;
output [1:0] DOPA;
output [0:0] DOPB;
input [9:0] ADDRA;
input [10:0] ADDRB;
input CLKA;
input CLKB;
input [15:0] DIA;
input [7:0] DIB;
input [1:0] DIPA;
input [0:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input [1:0] WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16BWE_S18 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
parameter INIT = 18'h0;
parameter INITP_00 = 256'h0;
parameter INITP_01 = 256'h0;
parameter INITP_02 = 256'h0;
parameter INITP_03 = 256'h0;
parameter INITP_04 = 256'h0;
parameter INITP_05 = 256'h0;
parameter INITP_06 = 256'h0;
parameter INITP_07 = 256'h0;
parameter INIT_00 = 256'h0;
parameter INIT_01 = 256'h0;
parameter INIT_02 = 256'h0;
parameter INIT_03 = 256'h0;
parameter INIT_04 = 256'h0;
parameter INIT_05 = 256'h0;
parameter INIT_06 = 256'h0;
parameter INIT_07 = 256'h0;
parameter INIT_08 = 256'h0;
parameter INIT_09 = 256'h0;
parameter INIT_0A = 256'h0;
parameter INIT_0B = 256'h0;
parameter INIT_0C = 256'h0;
parameter INIT_0D = 256'h0;
parameter INIT_0E = 256'h0;
parameter INIT_0F = 256'h0;
parameter INIT_10 = 256'h0;
parameter INIT_11 = 256'h0;
parameter INIT_12 = 256'h0;
parameter INIT_13 = 256'h0;
parameter INIT_14 = 256'h0;
parameter INIT_15 = 256'h0;
parameter INIT_16 = 256'h0;
parameter INIT_17 = 256'h0;
parameter INIT_18 = 256'h0;
parameter INIT_19 = 256'h0;
parameter INIT_1A = 256'h0;
parameter INIT_1B = 256'h0;
parameter INIT_1C = 256'h0;
parameter INIT_1D = 256'h0;
parameter INIT_1E = 256'h0;
parameter INIT_1F = 256'h0;
parameter INIT_20 = 256'h0;
parameter INIT_21 = 256'h0;
parameter INIT_22 = 256'h0;
parameter INIT_23 = 256'h0;
parameter INIT_24 = 256'h0;
parameter INIT_25 = 256'h0;
parameter INIT_26 = 256'h0;
parameter INIT_27 = 256'h0;
parameter INIT_28 = 256'h0;
parameter INIT_29 = 256'h0;
parameter INIT_2A = 256'h0;
parameter INIT_2B = 256'h0;
parameter INIT_2C = 256'h0;
parameter INIT_2D = 256'h0;
parameter INIT_2E = 256'h0;
parameter INIT_2F = 256'h0;
parameter INIT_30 = 256'h0;
parameter INIT_31 = 256'h0;
parameter INIT_32 = 256'h0;
parameter INIT_33 = 256'h0;
parameter INIT_34 = 256'h0;
parameter INIT_35 = 256'h0;
parameter INIT_36 = 256'h0;
parameter INIT_37 = 256'h0;
parameter INIT_38 = 256'h0;
parameter INIT_39 = 256'h0;
parameter INIT_3A = 256'h0;
parameter INIT_3B = 256'h0;
parameter INIT_3C = 256'h0;
parameter INIT_3D = 256'h0;
parameter INIT_3E = 256'h0;
parameter INIT_3F = 256'h0;
parameter SRVAL = 18'h0;
parameter WRITE_MODE = "WRITE_FIRST";
output [15:0] DO;
output [1:0] DOP;
input [9:0] ADDR;
input CLK;
input [15:0] DI;
input [1:0] DIP;
input EN;
input SSR;
input [1:0] WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16BWE_S36_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INITP_00 = 256'h0;
parameter INITP_01 = 256'h0;
parameter INITP_02 = 256'h0;
parameter INITP_03 = 256'h0;
parameter INITP_04 = 256'h0;
parameter INITP_05 = 256'h0;
parameter INITP_06 = 256'h0;
parameter INITP_07 = 256'h0;
parameter INIT_00 = 256'h0;
parameter INIT_01 = 256'h0;
parameter INIT_02 = 256'h0;
parameter INIT_03 = 256'h0;
parameter INIT_04 = 256'h0;
parameter INIT_05 = 256'h0;
parameter INIT_06 = 256'h0;
parameter INIT_07 = 256'h0;
parameter INIT_08 = 256'h0;
parameter INIT_09 = 256'h0;
parameter INIT_0A = 256'h0;
parameter INIT_0B = 256'h0;
parameter INIT_0C = 256'h0;
parameter INIT_0D = 256'h0;
parameter INIT_0E = 256'h0;
parameter INIT_0F = 256'h0;
parameter INIT_10 = 256'h0;
parameter INIT_11 = 256'h0;
parameter INIT_12 = 256'h0;
parameter INIT_13 = 256'h0;
parameter INIT_14 = 256'h0;
parameter INIT_15 = 256'h0;
parameter INIT_16 = 256'h0;
parameter INIT_17 = 256'h0;
parameter INIT_18 = 256'h0;
parameter INIT_19 = 256'h0;
parameter INIT_1A = 256'h0;
parameter INIT_1B = 256'h0;
parameter INIT_1C = 256'h0;
parameter INIT_1D = 256'h0;
parameter INIT_1E = 256'h0;
parameter INIT_1F = 256'h0;
parameter INIT_20 = 256'h0;
parameter INIT_21 = 256'h0;
parameter INIT_22 = 256'h0;
parameter INIT_23 = 256'h0;
parameter INIT_24 = 256'h0;
parameter INIT_25 = 256'h0;
parameter INIT_26 = 256'h0;
parameter INIT_27 = 256'h0;
parameter INIT_28 = 256'h0;
parameter INIT_29 = 256'h0;
parameter INIT_2A = 256'h0;
parameter INIT_2B = 256'h0;
parameter INIT_2C = 256'h0;
parameter INIT_2D = 256'h0;
parameter INIT_2E = 256'h0;
parameter INIT_2F = 256'h0;
parameter INIT_30 = 256'h0;
parameter INIT_31 = 256'h0;
parameter INIT_32 = 256'h0;
parameter INIT_33 = 256'h0;
parameter INIT_34 = 256'h0;
parameter INIT_35 = 256'h0;
parameter INIT_36 = 256'h0;
parameter INIT_37 = 256'h0;
parameter INIT_38 = 256'h0;
parameter INIT_39 = 256'h0;
parameter INIT_3A = 256'h0;
parameter INIT_3B = 256'h0;
parameter INIT_3C = 256'h0;
parameter INIT_3D = 256'h0;
parameter INIT_3E = 256'h0;
parameter INIT_3F = 256'h0;
parameter INIT_A = 36'h0;
parameter INIT_B = 18'h0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
output [31:0] DOA;
output [15:0] DOB;
output [3:0] DOPA;
output [1:0] DOPB;
input [8:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [31:0] DIA;
input [15:0] DIB;
input [3:0] DIPA;
input [1:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input [3:0] WEA;
input [1:0] WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16BWE_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INITP_00 = 256'h0;
parameter INITP_01 = 256'h0;
parameter INITP_02 = 256'h0;
parameter INITP_03 = 256'h0;
parameter INITP_04 = 256'h0;
parameter INITP_05 = 256'h0;
parameter INITP_06 = 256'h0;
parameter INITP_07 = 256'h0;
parameter INIT_00 = 256'h0;
parameter INIT_01 = 256'h0;
parameter INIT_02 = 256'h0;
parameter INIT_03 = 256'h0;
parameter INIT_04 = 256'h0;
parameter INIT_05 = 256'h0;
parameter INIT_06 = 256'h0;
parameter INIT_07 = 256'h0;
parameter INIT_08 = 256'h0;
parameter INIT_09 = 256'h0;
parameter INIT_0A = 256'h0;
parameter INIT_0B = 256'h0;
parameter INIT_0C = 256'h0;
parameter INIT_0D = 256'h0;
parameter INIT_0E = 256'h0;
parameter INIT_0F = 256'h0;
parameter INIT_10 = 256'h0;
parameter INIT_11 = 256'h0;
parameter INIT_12 = 256'h0;
parameter INIT_13 = 256'h0;
parameter INIT_14 = 256'h0;
parameter INIT_15 = 256'h0;
parameter INIT_16 = 256'h0;
parameter INIT_17 = 256'h0;
parameter INIT_18 = 256'h0;
parameter INIT_19 = 256'h0;
parameter INIT_1A = 256'h0;
parameter INIT_1B = 256'h0;
parameter INIT_1C = 256'h0;
parameter INIT_1D = 256'h0;
parameter INIT_1E = 256'h0;
parameter INIT_1F = 256'h0;
parameter INIT_20 = 256'h0;
parameter INIT_21 = 256'h0;
parameter INIT_22 = 256'h0;
parameter INIT_23 = 256'h0;
parameter INIT_24 = 256'h0;
parameter INIT_25 = 256'h0;
parameter INIT_26 = 256'h0;
parameter INIT_27 = 256'h0;
parameter INIT_28 = 256'h0;
parameter INIT_29 = 256'h0;
parameter INIT_2A = 256'h0;
parameter INIT_2B = 256'h0;
parameter INIT_2C = 256'h0;
parameter INIT_2D = 256'h0;
parameter INIT_2E = 256'h0;
parameter INIT_2F = 256'h0;
parameter INIT_30 = 256'h0;
parameter INIT_31 = 256'h0;
parameter INIT_32 = 256'h0;
parameter INIT_33 = 256'h0;
parameter INIT_34 = 256'h0;
parameter INIT_35 = 256'h0;
parameter INIT_36 = 256'h0;
parameter INIT_37 = 256'h0;
parameter INIT_38 = 256'h0;
parameter INIT_39 = 256'h0;
parameter INIT_3A = 256'h0;
parameter INIT_3B = 256'h0;
parameter INIT_3C = 256'h0;
parameter INIT_3D = 256'h0;
parameter INIT_3E = 256'h0;
parameter INIT_3F = 256'h0;
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
output [31:0] DOA;
output [31:0] DOB;
output [3:0] DOPA;
output [3:0] DOPB;
input [8:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [31:0] DIA;
input [31:0] DIB;
input [3:0] DIPA;
input [3:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input [3:0] WEA;
input [3:0] WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16BWE_S36_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INITP_00 = 256'h0;
parameter INITP_01 = 256'h0;
parameter INITP_02 = 256'h0;
parameter INITP_03 = 256'h0;
parameter INITP_04 = 256'h0;
parameter INITP_05 = 256'h0;
parameter INITP_06 = 256'h0;
parameter INITP_07 = 256'h0;
parameter INIT_00 = 256'h0;
parameter INIT_01 = 256'h0;
parameter INIT_02 = 256'h0;
parameter INIT_03 = 256'h0;
parameter INIT_04 = 256'h0;
parameter INIT_05 = 256'h0;
parameter INIT_06 = 256'h0;
parameter INIT_07 = 256'h0;
parameter INIT_08 = 256'h0;
parameter INIT_09 = 256'h0;
parameter INIT_0A = 256'h0;
parameter INIT_0B = 256'h0;
parameter INIT_0C = 256'h0;
parameter INIT_0D = 256'h0;
parameter INIT_0E = 256'h0;
parameter INIT_0F = 256'h0;
parameter INIT_10 = 256'h0;
parameter INIT_11 = 256'h0;
parameter INIT_12 = 256'h0;
parameter INIT_13 = 256'h0;
parameter INIT_14 = 256'h0;
parameter INIT_15 = 256'h0;
parameter INIT_16 = 256'h0;
parameter INIT_17 = 256'h0;
parameter INIT_18 = 256'h0;
parameter INIT_19 = 256'h0;
parameter INIT_1A = 256'h0;
parameter INIT_1B = 256'h0;
parameter INIT_1C = 256'h0;
parameter INIT_1D = 256'h0;
parameter INIT_1E = 256'h0;
parameter INIT_1F = 256'h0;
parameter INIT_20 = 256'h0;
parameter INIT_21 = 256'h0;
parameter INIT_22 = 256'h0;
parameter INIT_23 = 256'h0;
parameter INIT_24 = 256'h0;
parameter INIT_25 = 256'h0;
parameter INIT_26 = 256'h0;
parameter INIT_27 = 256'h0;
parameter INIT_28 = 256'h0;
parameter INIT_29 = 256'h0;
parameter INIT_2A = 256'h0;
parameter INIT_2B = 256'h0;
parameter INIT_2C = 256'h0;
parameter INIT_2D = 256'h0;
parameter INIT_2E = 256'h0;
parameter INIT_2F = 256'h0;
parameter INIT_30 = 256'h0;
parameter INIT_31 = 256'h0;
parameter INIT_32 = 256'h0;
parameter INIT_33 = 256'h0;
parameter INIT_34 = 256'h0;
parameter INIT_35 = 256'h0;
parameter INIT_36 = 256'h0;
parameter INIT_37 = 256'h0;
parameter INIT_38 = 256'h0;
parameter INIT_39 = 256'h0;
parameter INIT_3A = 256'h0;
parameter INIT_3B = 256'h0;
parameter INIT_3C = 256'h0;
parameter INIT_3D = 256'h0;
parameter INIT_3E = 256'h0;
parameter INIT_3F = 256'h0;
parameter INIT_A = 36'h0;
parameter INIT_B = 9'h0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 9'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
output [31:0] DOA;
output [7:0] DOB;
output [3:0] DOPA;
output [0:0] DOPB;
input [8:0] ADDRA;
input [10:0] ADDRB;
input CLKA;
input CLKB;
input [31:0] DIA;
input [7:0] DIB;
input [3:0] DIPA;
input [0:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input [3:0] WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16BWE_S36 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
parameter INIT = 36'h0;
parameter INITP_00 = 256'h0;
parameter INITP_01 = 256'h0;
parameter INITP_02 = 256'h0;
parameter INITP_03 = 256'h0;
parameter INITP_04 = 256'h0;
parameter INITP_05 = 256'h0;
parameter INITP_06 = 256'h0;
parameter INITP_07 = 256'h0;
parameter INIT_00 = 256'h0;
parameter INIT_01 = 256'h0;
parameter INIT_02 = 256'h0;
parameter INIT_03 = 256'h0;
parameter INIT_04 = 256'h0;
parameter INIT_05 = 256'h0;
parameter INIT_06 = 256'h0;
parameter INIT_07 = 256'h0;
parameter INIT_08 = 256'h0;
parameter INIT_09 = 256'h0;
parameter INIT_0A = 256'h0;
parameter INIT_0B = 256'h0;
parameter INIT_0C = 256'h0;
parameter INIT_0D = 256'h0;
parameter INIT_0E = 256'h0;
parameter INIT_0F = 256'h0;
parameter INIT_10 = 256'h0;
parameter INIT_11 = 256'h0;
parameter INIT_12 = 256'h0;
parameter INIT_13 = 256'h0;
parameter INIT_14 = 256'h0;
parameter INIT_15 = 256'h0;
parameter INIT_16 = 256'h0;
parameter INIT_17 = 256'h0;
parameter INIT_18 = 256'h0;
parameter INIT_19 = 256'h0;
parameter INIT_1A = 256'h0;
parameter INIT_1B = 256'h0;
parameter INIT_1C = 256'h0;
parameter INIT_1D = 256'h0;
parameter INIT_1E = 256'h0;
parameter INIT_1F = 256'h0;
parameter INIT_20 = 256'h0;
parameter INIT_21 = 256'h0;
parameter INIT_22 = 256'h0;
parameter INIT_23 = 256'h0;
parameter INIT_24 = 256'h0;
parameter INIT_25 = 256'h0;
parameter INIT_26 = 256'h0;
parameter INIT_27 = 256'h0;
parameter INIT_28 = 256'h0;
parameter INIT_29 = 256'h0;
parameter INIT_2A = 256'h0;
parameter INIT_2B = 256'h0;
parameter INIT_2C = 256'h0;
parameter INIT_2D = 256'h0;
parameter INIT_2E = 256'h0;
parameter INIT_2F = 256'h0;
parameter INIT_30 = 256'h0;
parameter INIT_31 = 256'h0;
parameter INIT_32 = 256'h0;
parameter INIT_33 = 256'h0;
parameter INIT_34 = 256'h0;
parameter INIT_35 = 256'h0;
parameter INIT_36 = 256'h0;
parameter INIT_37 = 256'h0;
parameter INIT_38 = 256'h0;
parameter INIT_39 = 256'h0;
parameter INIT_3A = 256'h0;
parameter INIT_3B = 256'h0;
parameter INIT_3C = 256'h0;
parameter INIT_3D = 256'h0;
parameter INIT_3E = 256'h0;
parameter INIT_3F = 256'h0;
parameter SRVAL = 36'h0;
parameter WRITE_MODE = "WRITE_FIRST";
output [31:0] DO;
output [3:0] DOP;
input [8:0] ADDR;
input CLK;
input [31:0] DI;
input [3:0] DIP;
input EN;
input SSR;
input [3:0] WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16BWE (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter integer DATA_WIDTH_A = 0;
parameter integer DATA_WIDTH_B = 0;
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [31:0] DOA;
output [31:0] DOB;
output [3:0] DOPA;
output [3:0] DOPB;
input [13:0] ADDRA;
input [13:0] ADDRB;
input CLKA;
input CLKB;
input [31:0] DIA;
input [31:0] DIB;
input [3:0] DIPA;
input [3:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input [3:0] WEA;
input [3:0] WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S18_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 18'h0;
parameter INIT_B = 18'h0;
parameter SRVAL_A = 18'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [15:0] DOA;
output [15:0] DOB;
output [1:0] DOPA;
output [1:0] DOPB;
input [9:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [15:0] DIA;
input [15:0] DIB;
input [1:0] DIPA;
input [1:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S18_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 18'h0;
parameter INIT_B = 36'h0;
parameter SRVAL_A = 18'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [15:0] DOA;
output [31:0] DOB;
output [1:0] DOPA;
output [3:0] DOPB;
input [9:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [15:0] DIA;
input [31:0] DIB;
input [1:0] DIPA;
input [3:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S18 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
parameter INIT = 18'h0;
parameter SRVAL = 18'h0;
parameter WRITE_MODE = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [15:0] DO;
output [1:0] DOP;
input [9:0] ADDR;
input CLK;
input [15:0] DI;
input [1:0] DIP;
input EN;
input SSR;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S1_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 1'h0;
parameter INIT_B = 18'h0;
parameter SRVAL_A = 1'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [15:0] DOB;
output [1:0] DOPB;
input [13:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [15:0] DIB;
input [1:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S1_S1 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 1'h0;
parameter INIT_B = 1'h0;
parameter SRVAL_A = 1'h0;
parameter SRVAL_B = 1'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [0:0] DOB;
input [13:0] ADDRA;
input [13:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [0:0] DIB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 1'h0;
parameter INIT_B = 2'h0;
parameter SRVAL_A = 1'h0;
parameter SRVAL_B = 2'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [1:0] DOB;
input [13:0] ADDRA;
input [12:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [1:0] DIB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S1_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 1'h0;
parameter INIT_B = 36'h0;
parameter SRVAL_A = 1'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [31:0] DOB;
output [3:0] DOPB;
input [13:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [31:0] DIB;
input [3:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S1_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 1'h0;
parameter INIT_B = 4'h0;
parameter SRVAL_A = 1'h0;
parameter SRVAL_B = 4'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [3:0] DOB;
input [13:0] ADDRA;
input [11:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [3:0] DIB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S1_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 1'h0;
parameter INIT_B = 9'h0;
parameter SRVAL_A = 1'h0;
parameter SRVAL_B = 9'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [7:0] DOB;
output [0:0] DOPB;
input [13:0] ADDRA;
input [10:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [7:0] DIB;
input [0:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S1 (DO, ADDR, CLK, DI, EN, SSR, WE);
parameter INIT = 1'h0;
parameter SRVAL = 1'h0;
parameter WRITE_MODE = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DO;
input [13:0] ADDR;
input CLK;
input [0:0] DI;
input EN;
input SSR;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S2_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 2'h0;
parameter INIT_B = 18'h0;
parameter SRVAL_A = 2'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DOA;
output [15:0] DOB;
output [1:0] DOPB;
input [12:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [1:0] DIA;
input [15:0] DIB;
input [1:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 2'h0;
parameter INIT_B = 2'h0;
parameter SRVAL_A = 2'h0;
parameter SRVAL_B = 2'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DOA;
output [1:0] DOB;
input [12:0] ADDRA;
input [12:0] ADDRB;
input CLKA;
input CLKB;
input [1:0] DIA;
input [1:0] DIB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S2_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 2'h0;
parameter INIT_B = 36'h0;
parameter SRVAL_A = 2'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DOA;
output [31:0] DOB;
output [3:0] DOPB;
input [12:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [1:0] DIA;
input [31:0] DIB;
input [3:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 2'h0;
parameter INIT_B = 4'h0;
parameter SRVAL_A = 2'h0;
parameter SRVAL_B = 4'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DOA;
output [3:0] DOB;
input [12:0] ADDRA;
input [11:0] ADDRB;
input CLKA;
input CLKB;
input [1:0] DIA;
input [3:0] DIB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S2_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 2'h0;
parameter INIT_B = 9'h0;
parameter SRVAL_A = 2'h0;
parameter SRVAL_B = 9'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DOA;
output [7:0] DOB;
output [0:0] DOPB;
input [12:0] ADDRA;
input [10:0] ADDRB;
input CLKA;
input CLKB;
input [1:0] DIA;
input [7:0] DIB;
input [0:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
parameter INIT = 2'h0;
parameter SRVAL = 2'h0;
parameter WRITE_MODE = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DO;
input [12:0] ADDR;
input CLK;
input [1:0] DI;
input EN;
input SSR;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [31:0] DOA;
output [31:0] DOB;
output [3:0] DOPA;
output [3:0] DOPB;
input [8:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [31:0] DIA;
input [31:0] DIB;
input [3:0] DIPA;
input [3:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S36 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
parameter INIT = 36'h0;
parameter SRVAL = 36'h0;
parameter WRITE_MODE = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [31:0] DO;
output [3:0] DOP;
input [8:0] ADDR;
input CLK;
input [31:0] DI;
input [3:0] DIP;
input EN;
input SSR;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S4_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 4'h0;
parameter INIT_B = 18'h0;
parameter SRVAL_A = 4'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [3:0] DOA;
output [15:0] DOB;
output [1:0] DOPB;
input [11:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [3:0] DIA;
input [15:0] DIB;
input [1:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S4_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 4'h0;
parameter INIT_B = 36'h0;
parameter SRVAL_A = 4'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [3:0] DOA;
output [31:0] DOB;
output [3:0] DOPB;
input [11:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [3:0] DIA;
input [31:0] DIB;
input [3:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S4_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 4'h0;
parameter INIT_B = 4'h0;
parameter SRVAL_A = 4'h0;
parameter SRVAL_B = 4'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [3:0] DOA;
output [3:0] DOB;
input [11:0] ADDRA;
input [11:0] ADDRB;
input CLKA;
input CLKB;
input [3:0] DIA;
input [3:0] DIB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S4_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 4'h0;
parameter INIT_B = 9'h0;
parameter SRVAL_A = 4'h0;
parameter SRVAL_B = 9'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [3:0] DOA;
output [7:0] DOB;
output [0:0] DOPB;
input [11:0] ADDRA;
input [10:0] ADDRB;
input CLKA;
input CLKB;
input [3:0] DIA;
input [7:0] DIB;
input [0:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S4 (DO, ADDR, CLK, DI, EN, SSR, WE);
parameter INIT = 4'h0;
parameter SRVAL = 4'h0;
parameter WRITE_MODE = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [3:0] DO;
input [11:0] ADDR;
input CLK;
input [3:0] DI;
input EN;
input SSR;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S9_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 9'h0;
parameter INIT_B = 18'h0;
parameter SRVAL_A = 9'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [7:0] DOA;
output [15:0] DOB;
output [0:0] DOPA;
output [1:0] DOPB;
input [10:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [7:0] DIA;
input [15:0] DIB;
input [0:0] DIPA;
input [1:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S9_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 9'h0;
parameter INIT_B = 36'h0;
parameter SRVAL_A = 9'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [7:0] DOA;
output [31:0] DOB;
output [0:0] DOPA;
output [3:0] DOPB;
input [10:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [7:0] DIA;
input [31:0] DIB;
input [0:0] DIPA;
input [3:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S9_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
parameter INIT_A = 9'h0;
parameter INIT_B = 9'h0;
parameter SRVAL_A = 9'h0;
parameter SRVAL_B = 9'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [7:0] DOA;
output [7:0] DOB;
output [0:0] DOPA;
output [0:0] DOPB;
input [10:0] ADDRA;
input [10:0] ADDRB;
input CLKA;
input CLKB;
input [7:0] DIA;
input [7:0] DIB;
input [0:0] DIPA;
input [0:0] DIPB;
input ENA;
input ENB;
input SSRA;
input SSRB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16_S9 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE);
parameter INIT = 9'h0;
parameter SRVAL = 9'h0;
parameter WRITE_MODE = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [7:0] DO;
output [0:0] DOP;
input [10:0] ADDR;
input CLK;
input [7:0] DI;
input [0:0] DIP;
input EN;
input SSR;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB16 (CASCADEOUTA, CASCADEOUTB, DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter INIT_FILE = "NONE";
parameter INVERT_CLK_DOA_REG = "FALSE";
parameter INVERT_CLK_DOB_REG = "FALSE";
parameter RAM_EXTENSION_A = "NONE";
parameter RAM_EXTENSION_B = "NONE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
output CASCADEOUTA;
output CASCADEOUTB;
output [31:0] DOA;
output [31:0] DOB;
output [3:0] DOPA;
output [3:0] DOPB;
input [14:0] ADDRA;
input [14:0] ADDRB;
input CASCADEINA;
input CASCADEINB;
input CLKA;
input CLKB;
input [31:0] DIA;
input [31:0] DIB;
input [3:0] DIPA;
input [3:0] DIPB;
input ENA;
input ENB;
input REGCEA;
input REGCEB;
input SSRA;
input SSRB;
input [3:0] WEA;
input [3:0] WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB18SDP (DO, DOP, DI, DIP, RDADDR, RDCLK, RDEN, REGCE, SSR, WE, WRADDR, WRCLK, WREN);
parameter integer DO_REG = 0;
parameter INIT = 36'h0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_FILE = "NONE";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_MODE = "SAFE";
parameter SRVAL = 36'h0;
output [31:0] DO;
output [3:0] DOP;
input [31:0] DI;
input [3:0] DIP;
input [8:0] RDADDR;
input RDCLK;
input RDEN;
input REGCE;
input SSR;
input [3:0] WE;
input [8:0] WRADDR;
input WRCLK;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 18'h0;
parameter INIT_B = 18'h0;
parameter INIT_FILE = "NONE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_MODE = "SAFE";
parameter SRVAL_A = 18'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
output [15:0] DOA;
output [15:0] DOB;
output [1:0] DOPA;
output [1:0] DOPB;
input [13:0] ADDRA;
input [13:0] ADDRB;
input CLKA;
input CLKB;
input [15:0] DIA;
input [15:0] DIB;
input [1:0] DIPA;
input [1:0] DIPB;
input ENA;
input ENB;
input REGCEA;
input REGCEB;
input SSRA;
input SSRB;
input [1:0] WEA;
input [1:0] WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB32_S64_ECC (DO, STATUS, DI, RDADDR, RDCLK, RDEN, SSR, WRADDR, WRCLK, WREN);
parameter integer DO_REG = 0;
parameter SIM_COLLISION_CHECK = "ALL";
output [63:0] DO;
output [1:0] STATUS;
input [63:0] DI;
input [8:0] RDADDR;
input RDCLK;
input RDEN;
input SSR;
input [8:0] WRADDR;
input WRCLK;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB36_EXP (CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, ADDRAL, ADDRAU, ADDRBL, ADDRBU, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, CLKAL, CLKAU, CLKBL, CLKBU, DIA, DIB, DIPA, DIPB, ENAL, ENAU, ENBL, ENBU, REGCEAL, REGCEAU, REGCEBL, REGCEBU, REGCLKAL, REGCLKAU, REGCLKBL, REGCLKBU, SSRAL, SSRAU, SSRBL, SSRBU, WEAL, WEAU, WEBL, WEBU);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter INIT_FILE = "NONE";
parameter RAM_EXTENSION_A = "NONE";
parameter RAM_EXTENSION_B = "NONE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_MODE = "SAFE";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
output CASCADEOUTLATA;
output CASCADEOUTLATB;
output CASCADEOUTREGA;
output CASCADEOUTREGB;
output [31:0] DOA;
output [31:0] DOB;
output [3:0] DOPA;
output [3:0] DOPB;
input [15:0] ADDRAL;
input [14:0] ADDRAU;
input [15:0] ADDRBL;
input [14:0] ADDRBU;
input CASCADEINLATA;
input CASCADEINLATB;
input CASCADEINREGA;
input CASCADEINREGB;
input CLKAL;
input CLKAU;
input CLKBL;
input CLKBU;
input [31:0] DIA;
input [31:0] DIB;
input [3:0] DIPA;
input [3:0] DIPB;
input ENAL;
input ENAU;
input ENBL;
input ENBU;
input REGCEAL;
input REGCEAU;
input REGCEBL;
input REGCEBU;
input REGCLKAL;
input REGCLKAU;
input REGCLKBL;
input REGCLKBU;
input SSRAL;
input SSRAU;
input SSRBL;
input SSRBU;
input [3:0] WEAL;
input [3:0] WEAU;
input [7:0] WEBL;
input [7:0] WEBU;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB36SDP_EXP (DBITERR, DO, DOP, ECCPARITY, SBITERR, DI, DIP, RDADDRL, RDADDRU, RDCLKL, RDCLKU, RDENL, RDENU, RDRCLKL, RDRCLKU, REGCEL, REGCEU, SSRL, SSRU, WEL, WEU, WRADDRL, WRADDRU, WRCLKL, WRCLKU, WRENL, WRENU);
parameter integer DO_REG = 0;
parameter EN_ECC_READ = "FALSE";
parameter EN_ECC_SCRUB = "FALSE";
parameter EN_ECC_WRITE = "FALSE";
parameter INIT = 72'h0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_FILE = "NONE";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_MODE = "SAFE";
parameter SRVAL = 72'h0;
output DBITERR;
output [63:0] DO;
output [7:0] DOP;
output [7:0] ECCPARITY;
output SBITERR;
input [63:0] DI;
input [7:0] DIP;
input [15:0] RDADDRL;
input [14:0] RDADDRU;
input RDCLKL;
input RDCLKU;
input RDENL;
input RDENU;
input RDRCLKL;
input RDRCLKU;
input REGCEL;
input REGCEU;
input SSRL;
input SSRU;
input [7:0] WEL;
input [7:0] WEU;
input [15:0] WRADDRL;
input [14:0] WRADDRU;
input WRCLKL;
input WRCLKU;
input WRENL;
input WRENU;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB36SDP (DBITERR, DO, DOP, ECCPARITY, SBITERR, DI, DIP, RDADDR, RDCLK, RDEN, REGCE, SSR, WE, WRADDR, WRCLK, WREN);
parameter integer DO_REG = 0;
parameter EN_ECC_READ = "FALSE";
parameter EN_ECC_SCRUB = "FALSE";
parameter EN_ECC_WRITE = "FALSE";
parameter INIT = 72'h0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_FILE = "NONE";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_MODE = "SAFE";
parameter SRVAL = 72'h0;
output DBITERR;
output [63:0] DO;
output [7:0] DOP;
output [7:0] ECCPARITY;
output SBITERR;
input [63:0] DI;
input [7:0] DIP;
input [8:0] RDADDR;
input RDCLK;
input RDEN;
input REGCE;
input SSR;
input [7:0] WE;
input [8:0] WRADDR;
input WRCLK;
input WREN;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB36 (CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter INIT_FILE = "NONE";
parameter RAM_EXTENSION_A = "NONE";
parameter RAM_EXTENSION_B = "NONE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_MODE = "SAFE";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
output CASCADEOUTLATA;
output CASCADEOUTLATB;
output CASCADEOUTREGA;
output CASCADEOUTREGB;
output [31:0] DOA;
output [31:0] DOB;
output [3:0] DOPA;
output [3:0] DOPB;
input [15:0] ADDRA;
input [15:0] ADDRB;
input CASCADEINLATA;
input CASCADEINLATB;
input CASCADEINREGA;
input CASCADEINREGB;
input CLKA;
input CLKB;
input [31:0] DIA;
input [31:0] DIB;
input [3:0] DIPA;
input [3:0] DIPB;
input ENA;
input ENB;
input REGCEA;
input REGCEB;
input SSRA;
input SSRB;
input [3:0] WEA;
input [3:0] WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S16_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [15:0] DOA;
output [15:0] DOB;
input [7:0] ADDRA;
input [7:0] ADDRB;
input CLKA;
input CLKB;
input [15:0] DIA;
input [15:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S16 (DO, ADDR, CLK, DI, EN, RST, WE);
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [15:0] DO;
input [7:0] ADDR;
input CLK;
input [15:0] DI;
input EN;
input RST;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S1_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [15:0] DOB;
input [11:0] ADDRA;
input [7:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [15:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S1_S1 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [0:0] DOB;
input [11:0] ADDRA;
input [11:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [0:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [1:0] DOB;
input [11:0] ADDRA;
input [10:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [1:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S1_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [3:0] DOB;
input [11:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [3:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S1_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DOA;
output [7:0] DOB;
input [11:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [0:0] DIA;
input [7:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S1 (DO, ADDR, CLK, DI, EN, RST, WE);
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [0:0] DO;
input [11:0] ADDR;
input CLK;
input [0:0] DI;
input EN;
input RST;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S2_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DOA;
output [15:0] DOB;
input [10:0] ADDRA;
input [7:0] ADDRB;
input CLKA;
input CLKB;
input [1:0] DIA;
input [15:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DOA;
output [1:0] DOB;
input [10:0] ADDRA;
input [10:0] ADDRB;
input CLKA;
input CLKB;
input [1:0] DIA;
input [1:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DOA;
output [3:0] DOB;
input [10:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [1:0] DIA;
input [3:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S2_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DOA;
output [7:0] DOB;
input [10:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [1:0] DIA;
input [7:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S2 (DO, ADDR, CLK, DI, EN, RST, WE);
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DO;
input [10:0] ADDR;
input CLK;
input [1:0] DI;
input EN;
input RST;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S4_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [3:0] DOA;
output [15:0] DOB;
input [9:0] ADDRA;
input [7:0] ADDRB;
input CLKA;
input CLKB;
input [3:0] DIA;
input [15:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S4_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [3:0] DOA;
output [3:0] DOB;
input [9:0] ADDRA;
input [9:0] ADDRB;
input CLKA;
input CLKB;
input [3:0] DIA;
input [3:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S4_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [3:0] DOA;
output [7:0] DOB;
input [9:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [3:0] DIA;
input [7:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S4 (DO, ADDR, CLK, DI, EN, RST, WE);
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [3:0] DO;
input [9:0] ADDR;
input CLK;
input [3:0] DI;
input EN;
input RST;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S8_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [7:0] DOA;
output [15:0] DOB;
input [8:0] ADDRA;
input [7:0] ADDRB;
input CLKA;
input CLKB;
input [7:0] DIA;
input [15:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S8_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB);
parameter SIM_COLLISION_CHECK = "ALL";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [7:0] DOA;
output [7:0] DOB;
input [8:0] ADDRA;
input [8:0] ADDRB;
input CLKA;
input CLKB;
input [7:0] DIA;
input [7:0] DIB;
input ENA;
input ENB;
input RSTA;
input RSTB;
input WEA;
input WEB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module RAMB4_S8 (DO, ADDR, CLK, DI, EN, RST, WE);
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [7:0] DO;
input [8:0] ADDR;
input CLK;
input [7:0] DI;
input EN;
input RST;
input WE;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ROM128X1 (O, A0, A1, A2, A3, A4, A5, A6);
parameter INIT = 128'h00000000000000000000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ROM16X1 (O, A0, A1, A2, A3);
parameter INIT = 16'h0000;
output O;
input A0;
input A1;
input A2;
input A3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ROM256X1 (O, A0, A1, A2, A3, A4, A5, A6, A7);
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ROM32X1 (O, A0, A1, A2, A3, A4);
parameter INIT = 32'h00000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module ROM64X1 (O, A0, A1, A2, A3, A4, A5);
parameter INIT = 64'h0000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SIM_CONFIG_S3A (CSOB, DONE, CCLK, D, DCMLOCK, CSIB, INITB, M, PROGB, RDWRB);
parameter DEVICE_ID = 32'h0;
output CSOB;
inout DONE;
inout [7:0] D;
inout INITB;
input CCLK;
input DCMLOCK;
input CSIB;
input [2:0] M;
input PROGB;
input RDWRB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SIM_CONFIG_V5 (BUSY, CSOB, DONE, CCLK, CSB, D, DCMLOCK, INITB, M, PROGB, RDWRB);
parameter DEVICE_ID = 32'h0;
output BUSY;
output CSOB;
inout DONE;
inout [31:0] D;
inout INITB;
input CCLK;
input CSB;
input DCMLOCK;
input [2:0] M;
input PROGB;
input RDWRB;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SPI_ACCESS (MISO, CLK, CSB, MOSI);
parameter SIM_DELAY_TYPE = "SCALED";
parameter SIM_DEVICE = "3S1400AN";
parameter SIM_FACTORY_ID = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter SIM_USER_ID = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
parameter SIM_MEM_FILE = "NONE";
output MISO;
input CLK;
input CSB;
input MOSI;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SRL16_1 (Q, A0, A1, A2, A3, CLK, D);
parameter INIT = 16'h0000;
output Q;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SRL16E_1 (Q, A0, A1, A2, A3, CE, CLK, D);
parameter INIT = 16'h0000;
output Q;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D);
parameter INIT = 16'h0000;
output Q;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SRL16 (Q, A0, A1, A2, A3, CLK, D);
parameter INIT = 16'h0000;
output Q;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SRLC16_1 (Q, Q15, A0, A1, A2, A3, CLK, D);
parameter INIT = 16'h0000;
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SRLC16E_1 (Q, Q15, A0, A1, A2, A3, CE, CLK, D);
parameter INIT = 16'h0000;
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SRLC16E (Q, Q15, A0, A1, A2, A3, CE, CLK, D);
parameter INIT = 16'h0000;
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SRLC16 (Q, Q15, A0, A1, A2, A3, CLK, D);
parameter INIT = 16'h0000;
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SRLC32E (Q, Q31, A, CE, CLK, D);
parameter INIT = 32'h00000000;
output Q;
output Q31;
input [4:0] A;
input CE;
input CLK;
input D;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module STARTUP_FPGACORE (CLK, GSR);
input CLK;
input GSR;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module STARTUP_SPARTAN2 (CLK, GSR, GTS);
input CLK;
input GSR;
input GTS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module STARTUP_SPARTAN3A (CLK, GSR, GTS);
input CLK;
input GSR;
input GTS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module STARTUP_SPARTAN3E (CLK, GSR, GTS, MBT);
input CLK;
input GSR;
input GTS;
input MBT;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module STARTUP_SPARTAN3 (CLK, GSR, GTS);
input CLK;
input GSR;
input GTS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module STARTUP_VIRTEX2 (CLK, GSR, GTS);
input CLK;
input GSR;
input GTS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module STARTUP_VIRTEX4 (EOS, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS);
output EOS;
input CLK;
input GSR;
input GTS;
input USRCCLKO;
input USRCCLKTS;
input USRDONEO;
input USRDONETS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module STARTUP_VIRTEX5 (CFGCLK, CFGMCLK, DINSPI, EOS, TCKSPI, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS);
output CFGCLK;
output CFGMCLK;
output DINSPI;
output EOS;
output TCKSPI;
input CLK;
input GSR;
input GTS;
input USRCCLKO;
input USRCCLKTS;
input USRDONEO;
input USRDONETS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module STARTUP_VIRTEX (CLK, GSR, GTS);
input CLK;
input GSR;
input GTS;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module SYSMON (ALM, BUSY, CHANNEL, DO, DRDY, EOC, EOS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, OT, CONVST, CONVSTCLK, DADDR, DCLK, DEN, DI, DWE, RESET, VAUXN, VAUXP, VN, VP);
parameter INIT_40 = 16'h0;
parameter INIT_41 = 16'h0;
parameter INIT_42 = 16'h0800;
parameter INIT_43 = 16'h0;
parameter INIT_44 = 16'h0;
parameter INIT_45 = 16'h0;
parameter INIT_46 = 16'h0;
parameter INIT_47 = 16'h0;
parameter INIT_48 = 16'h0;
parameter INIT_49 = 16'h0;
parameter INIT_4A = 16'h0;
parameter INIT_4B = 16'h0;
parameter INIT_4C = 16'h0;
parameter INIT_4D = 16'h0;
parameter INIT_4E = 16'h0;
parameter INIT_4F = 16'h0;
parameter INIT_50 = 16'h0;
parameter INIT_51 = 16'h0;
parameter INIT_52 = 16'h0;
parameter INIT_53 = 16'h0;
parameter INIT_54 = 16'h0;
parameter INIT_55 = 16'h0;
parameter INIT_56 = 16'h0;
parameter INIT_57 = 16'h0;
parameter SIM_MONITOR_FILE = "design.txt";
output [2:0] ALM;
output BUSY;
output [4:0] CHANNEL;
output [15:0] DO;
output DRDY;
output EOC;
output EOS;
output JTAGBUSY;
output JTAGLOCKED;
output JTAGMODIFIED;
output OT;
input CONVST;
input CONVSTCLK;
input [6:0] DADDR;
input DCLK;
input DEN;
input [15:0] DI;
input DWE;
input RESET;
input [15:0] VAUXN;
input [15:0] VAUXP;
input VN;
input VP;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module TBLOCK ();
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module TEMAC (DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXD, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATS, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXD, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC0PHYTXGMIIMIICLKOUT, EMAC0SPEEDIS10100, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXD, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME, EMAC1CLIENTRXSTATS, EMAC1CLIENTRXSTATSBYTEVLD, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK, EMAC1PHYTXD, EMAC1PHYTXEN, EMAC1PHYTXER, EMAC1PHYTXGMIIMIICLKOUT, EMAC1SPEEDIS10100, EMACDCRACK, EMACDCRDBUS, HOSTMIIMRDY, HOSTRDDATA, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXD, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1PAUSEVAL, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXD, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXIFGDELAY, CLIENTEMAC1TXUNDERRUN, DCREMACABUS, DCREMACCLK, DCREMACDBUS, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTADDR, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTOPCODE, HOSTREQ, HOSTWRDATA, PHYEMAC0COL, PHYEMAC0CRS, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0PHYAD, PHYEMAC0RXBUFERR, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCLKCORCNT, PHYEMAC0RXCOMMADET, PHYEMAC0RXD, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXLOSSOFSYNC, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC0TXGMIIMIICLKIN, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN, PHYEMAC1MDIN, PHYEMAC1MIITXCLK, PHYEMAC1PHYAD, PHYEMAC1RXBUFERR, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCLKCORCNT, PHYEMAC1RXCOMMADET, PHYEMAC1RXD, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXLOSSOFSYNC, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, PHYEMAC1TXGMIIMIICLKIN, RESET);
parameter EMAC0_1000BASEX_ENABLE = "FALSE";
parameter EMAC0_ADDRFILTER_ENABLE = "FALSE";
parameter EMAC0_BYTEPHY = "FALSE";
parameter EMAC0_CONFIGVEC_79 = "FALSE";
parameter EMAC0_GTLOOPBACK = "FALSE";
parameter EMAC0_HOST_ENABLE = "FALSE";
parameter EMAC0_LTCHECK_DISABLE = "FALSE";
parameter EMAC0_MDIO_ENABLE = "FALSE";
parameter EMAC0_PHYINITAUTONEG_ENABLE = "FALSE";
parameter EMAC0_PHYISOLATE = "FALSE";
parameter EMAC0_PHYLOOPBACKMSB = "FALSE";
parameter EMAC0_PHYPOWERDOWN = "FALSE";
parameter EMAC0_PHYRESET = "FALSE";
parameter EMAC0_RGMII_ENABLE = "FALSE";
parameter EMAC0_RX16BITCLIENT_ENABLE = "FALSE";
parameter EMAC0_RXFLOWCTRL_ENABLE = "FALSE";
parameter EMAC0_RXHALFDUPLEX = "FALSE";
parameter EMAC0_RXINBANDFCS_ENABLE = "FALSE";
parameter EMAC0_RXJUMBOFRAME_ENABLE = "FALSE";
parameter EMAC0_RXRESET = "FALSE";
parameter EMAC0_RXVLAN_ENABLE = "FALSE";
parameter EMAC0_RX_ENABLE = "FALSE";
parameter EMAC0_SGMII_ENABLE = "FALSE";
parameter EMAC0_SPEED_LSB = "FALSE";
parameter EMAC0_SPEED_MSB = "FALSE";
parameter EMAC0_TX16BITCLIENT_ENABLE = "FALSE";
parameter EMAC0_TXFLOWCTRL_ENABLE = "FALSE";
parameter EMAC0_TXHALFDUPLEX = "FALSE";
parameter EMAC0_TXIFGADJUST_ENABLE = "FALSE";
parameter EMAC0_TXINBANDFCS_ENABLE = "FALSE";
parameter EMAC0_TXJUMBOFRAME_ENABLE = "FALSE";
parameter EMAC0_TXRESET = "FALSE";
parameter EMAC0_TXVLAN_ENABLE = "FALSE";
parameter EMAC0_TX_ENABLE = "FALSE";
parameter EMAC0_UNIDIRECTION_ENABLE = "FALSE";
parameter EMAC0_USECLKEN = "FALSE";
parameter EMAC1_1000BASEX_ENABLE = "FALSE";
parameter EMAC1_ADDRFILTER_ENABLE = "FALSE";
parameter EMAC1_BYTEPHY = "FALSE";
parameter EMAC1_CONFIGVEC_79 = "FALSE";
parameter EMAC1_GTLOOPBACK = "FALSE";
parameter EMAC1_HOST_ENABLE = "FALSE";
parameter EMAC1_LTCHECK_DISABLE = "FALSE";
parameter EMAC1_MDIO_ENABLE = "FALSE";
parameter EMAC1_PHYINITAUTONEG_ENABLE = "FALSE";
parameter EMAC1_PHYISOLATE = "FALSE";
parameter EMAC1_PHYLOOPBACKMSB = "FALSE";
parameter EMAC1_PHYPOWERDOWN = "FALSE";
parameter EMAC1_PHYRESET = "FALSE";
parameter EMAC1_RGMII_ENABLE = "FALSE";
parameter EMAC1_RX16BITCLIENT_ENABLE = "FALSE";
parameter EMAC1_RXFLOWCTRL_ENABLE = "FALSE";
parameter EMAC1_RXHALFDUPLEX = "FALSE";
parameter EMAC1_RXINBANDFCS_ENABLE = "FALSE";
parameter EMAC1_RXJUMBOFRAME_ENABLE = "FALSE";
parameter EMAC1_RXRESET = "FALSE";
parameter EMAC1_RXVLAN_ENABLE = "FALSE";
parameter EMAC1_RX_ENABLE = "FALSE";
parameter EMAC1_SGMII_ENABLE = "FALSE";
parameter EMAC1_SPEED_LSB = "FALSE";
parameter EMAC1_SPEED_MSB = "FALSE";
parameter EMAC1_TX16BITCLIENT_ENABLE = "FALSE";
parameter EMAC1_TXFLOWCTRL_ENABLE = "FALSE";
parameter EMAC1_TXHALFDUPLEX = "FALSE";
parameter EMAC1_TXIFGADJUST_ENABLE = "FALSE";
parameter EMAC1_TXINBANDFCS_ENABLE = "FALSE";
parameter EMAC1_TXJUMBOFRAME_ENABLE = "FALSE";
parameter EMAC1_TXRESET = "FALSE";
parameter EMAC1_TXVLAN_ENABLE = "FALSE";
parameter EMAC1_TX_ENABLE = "FALSE";
parameter EMAC1_UNIDIRECTION_ENABLE = "FALSE";
parameter EMAC1_USECLKEN = "FALSE";
parameter [0:7] EMAC0_DCRBASEADDR = 8'h00;
parameter [0:7] EMAC1_DCRBASEADDR = 8'h00;
parameter [47:0] EMAC0_PAUSEADDR = 48'h000000000000;
parameter [47:0] EMAC0_UNICASTADDR = 48'h000000000000;
parameter [47:0] EMAC1_PAUSEADDR = 48'h000000000000;
parameter [47:0] EMAC1_UNICASTADDR = 48'h000000000000;
parameter [8:0] EMAC0_LINKTIMERVAL = 9'h000;
parameter [8:0] EMAC1_LINKTIMERVAL = 9'h000;
output DCRHOSTDONEIR;
output EMAC0CLIENTANINTERRUPT;
output EMAC0CLIENTRXBADFRAME;
output EMAC0CLIENTRXCLIENTCLKOUT;
output [15:0] EMAC0CLIENTRXD;
output EMAC0CLIENTRXDVLD;
output EMAC0CLIENTRXDVLDMSW;
output EMAC0CLIENTRXFRAMEDROP;
output EMAC0CLIENTRXGOODFRAME;
output [6:0] EMAC0CLIENTRXSTATS;
output EMAC0CLIENTRXSTATSBYTEVLD;
output EMAC0CLIENTRXSTATSVLD;
output EMAC0CLIENTTXACK;
output EMAC0CLIENTTXCLIENTCLKOUT;
output EMAC0CLIENTTXCOLLISION;
output EMAC0CLIENTTXRETRANSMIT;
output EMAC0CLIENTTXSTATS;
output EMAC0CLIENTTXSTATSBYTEVLD;
output EMAC0CLIENTTXSTATSVLD;
output EMAC0PHYENCOMMAALIGN;
output EMAC0PHYLOOPBACKMSB;
output EMAC0PHYMCLKOUT;
output EMAC0PHYMDOUT;
output EMAC0PHYMDTRI;
output EMAC0PHYMGTRXRESET;
output EMAC0PHYMGTTXRESET;
output EMAC0PHYPOWERDOWN;
output EMAC0PHYSYNCACQSTATUS;
output EMAC0PHYTXCHARDISPMODE;
output EMAC0PHYTXCHARDISPVAL;
output EMAC0PHYTXCHARISK;
output EMAC0PHYTXCLK;
output [7:0] EMAC0PHYTXD;
output EMAC0PHYTXEN;
output EMAC0PHYTXER;
output EMAC0PHYTXGMIIMIICLKOUT;
output EMAC0SPEEDIS10100;
output EMAC1CLIENTANINTERRUPT;
output EMAC1CLIENTRXBADFRAME;
output EMAC1CLIENTRXCLIENTCLKOUT;
output [15:0] EMAC1CLIENTRXD;
output EMAC1CLIENTRXDVLD;
output EMAC1CLIENTRXDVLDMSW;
output EMAC1CLIENTRXFRAMEDROP;
output EMAC1CLIENTRXGOODFRAME;
output [6:0] EMAC1CLIENTRXSTATS;
output EMAC1CLIENTRXSTATSBYTEVLD;
output EMAC1CLIENTRXSTATSVLD;
output EMAC1CLIENTTXACK;
output EMAC1CLIENTTXCLIENTCLKOUT;
output EMAC1CLIENTTXCOLLISION;
output EMAC1CLIENTTXRETRANSMIT;
output EMAC1CLIENTTXSTATS;
output EMAC1CLIENTTXSTATSBYTEVLD;
output EMAC1CLIENTTXSTATSVLD;
output EMAC1PHYENCOMMAALIGN;
output EMAC1PHYLOOPBACKMSB;
output EMAC1PHYMCLKOUT;
output EMAC1PHYMDOUT;
output EMAC1PHYMDTRI;
output EMAC1PHYMGTRXRESET;
output EMAC1PHYMGTTXRESET;
output EMAC1PHYPOWERDOWN;
output EMAC1PHYSYNCACQSTATUS;
output EMAC1PHYTXCHARDISPMODE;
output EMAC1PHYTXCHARDISPVAL;
output EMAC1PHYTXCHARISK;
output EMAC1PHYTXCLK;
output [7:0] EMAC1PHYTXD;
output EMAC1PHYTXEN;
output EMAC1PHYTXER;
output EMAC1PHYTXGMIIMIICLKOUT;
output EMAC1SPEEDIS10100;
output EMACDCRACK;
output [0:31] EMACDCRDBUS;
output HOSTMIIMRDY;
output [31:0] HOSTRDDATA;
input CLIENTEMAC0DCMLOCKED;
input CLIENTEMAC0PAUSEREQ;
input [15:0] CLIENTEMAC0PAUSEVAL;
input CLIENTEMAC0RXCLIENTCLKIN;
input CLIENTEMAC0TXCLIENTCLKIN;
input [15:0] CLIENTEMAC0TXD;
input CLIENTEMAC0TXDVLD;
input CLIENTEMAC0TXDVLDMSW;
input CLIENTEMAC0TXFIRSTBYTE;
input [7:0] CLIENTEMAC0TXIFGDELAY;
input CLIENTEMAC0TXUNDERRUN;
input CLIENTEMAC1DCMLOCKED;
input CLIENTEMAC1PAUSEREQ;
input [15:0] CLIENTEMAC1PAUSEVAL;
input CLIENTEMAC1RXCLIENTCLKIN;
input CLIENTEMAC1TXCLIENTCLKIN;
input [15:0] CLIENTEMAC1TXD;
input CLIENTEMAC1TXDVLD;
input CLIENTEMAC1TXDVLDMSW;
input CLIENTEMAC1TXFIRSTBYTE;
input [7:0] CLIENTEMAC1TXIFGDELAY;
input CLIENTEMAC1TXUNDERRUN;
input [0:9] DCREMACABUS;
input DCREMACCLK;
input [0:31] DCREMACDBUS;
input DCREMACENABLE;
input DCREMACREAD;
input DCREMACWRITE;
input [9:0] HOSTADDR;
input HOSTCLK;
input HOSTEMAC1SEL;
input HOSTMIIMSEL;
input [1:0] HOSTOPCODE;
input HOSTREQ;
input [31:0] HOSTWRDATA;
input PHYEMAC0COL;
input PHYEMAC0CRS;
input PHYEMAC0GTXCLK;
input PHYEMAC0MCLKIN;
input PHYEMAC0MDIN;
input PHYEMAC0MIITXCLK;
input [4:0] PHYEMAC0PHYAD;
input PHYEMAC0RXBUFERR;
input [1:0] PHYEMAC0RXBUFSTATUS;
input PHYEMAC0RXCHARISCOMMA;
input PHYEMAC0RXCHARISK;
input PHYEMAC0RXCHECKINGCRC;
input PHYEMAC0RXCLK;
input [2:0] PHYEMAC0RXCLKCORCNT;
input PHYEMAC0RXCOMMADET;
input [7:0] PHYEMAC0RXD;
input PHYEMAC0RXDISPERR;
input PHYEMAC0RXDV;
input PHYEMAC0RXER;
input [1:0] PHYEMAC0RXLOSSOFSYNC;
input PHYEMAC0RXNOTINTABLE;
input PHYEMAC0RXRUNDISP;
input PHYEMAC0SIGNALDET;
input PHYEMAC0TXBUFERR;
input PHYEMAC0TXGMIIMIICLKIN;
input PHYEMAC1COL;
input PHYEMAC1CRS;
input PHYEMAC1GTXCLK;
input PHYEMAC1MCLKIN;
input PHYEMAC1MDIN;
input PHYEMAC1MIITXCLK;
input [4:0] PHYEMAC1PHYAD;
input PHYEMAC1RXBUFERR;
input [1:0] PHYEMAC1RXBUFSTATUS;
input PHYEMAC1RXCHARISCOMMA;
input PHYEMAC1RXCHARISK;
input PHYEMAC1RXCHECKINGCRC;
input PHYEMAC1RXCLK;
input [2:0] PHYEMAC1RXCLKCORCNT;
input PHYEMAC1RXCOMMADET;
input [7:0] PHYEMAC1RXD;
input PHYEMAC1RXDISPERR;
input PHYEMAC1RXDV;
input PHYEMAC1RXER;
input [1:0] PHYEMAC1RXLOSSOFSYNC;
input PHYEMAC1RXNOTINTABLE;
input PHYEMAC1RXRUNDISP;
input PHYEMAC1SIGNALDET;
input PHYEMAC1TXBUFERR;
input PHYEMAC1TXGMIIMIICLKIN;
input RESET;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module TIMEGRP ();
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module TIMESPEC ();
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module USR_ACCESS_VIRTEX4 (DATA, DATAVALID);
output [31:0] DATA;
output DATAVALID;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module USR_ACCESS_VIRTEX5 (CFGCLK, DATA, DATAVALID);
output CFGCLK;
output [31:0] DATA;
output DATAVALID;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module VCC (P);
output P;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module WIREAND (I);
input I;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XNOR2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XNOR3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XNOR4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XNOR5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XOR2 (O, I0, I1);
output O;
input I0;
input I1;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XOR3 (O, I0, I1, I2);
output O;
input I0;
input I1;
input I2;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XOR4 (O, I0, I1, I2, I3);
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XOR5 (O, I0, I1, I2, I3, I4);
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XORCY_D (LO, O, CI, LI);
output LO;
output O;
input CI;
input LI;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XORCY_L (LO, CI, LI);
output LO;
input CI;
input LI;
endmodule
(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001
module XORCY (O, CI, LI);
output O;
input CI;
input LI;
endmodule