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# clock pin for Basys Board
NET "A_CLK"    LOC = "p53"                           ; # oscillator 48 Mhz
NET "B_CLK"    LOC = "p54"                           ; # resonator 100/50/25


NET "A_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
PIN "core/clock_sys/DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; 



# Pin assignment for DispCtl
# Connected to Basys onBoard 7seg display

NET "SEG<0>" LOC = "p25"                             ; # Signal name = CA
NET "SEG<1>" LOC = "p16"                             ; # Signal name = CB
NET "SEG<2>" LOC = "p23"                             ; # Signal name = CC
NET "SEG<3>" LOC = "p21"                             ; # Signal name = CD
NET "SEG<4>" LOC = "p20"                             ; # Signal name = CE
NET "SEG<5>" LOC = "p17"                             ; # Signal name = CF
NET "SEG<6>" LOC = "p83"                             ; # Signal name = CG
NET "DP"     LOC = "p22"                             ; # Signal name = DP

NET "AN<3>"  LOC = "p26"                             ; # Signal name = AN3
NET "AN<2>"  LOC = "p32"                             ; # Signal name = AN2
NET "AN<1>"  LOC = "p33"                             ; # Signal name = AN1
NET "AN<0>"  LOC = "p34"                             ; # Signal name = AN0

# Pin assignment for LEDs
NET "LED<7>"      LOC = "p2"                         ; # Bank = 3, Signal name = LD7
NET "LED<6>"      LOC = "p3"                         ; # Bank = 3, Signal name = LD6
NET "LED<5>"      LOC = "p4"                         ; # Bank = 3, Signal name = LD5
NET "LED<4>"      LOC = "p5"                         ; # Bank = 3, Signal name = LD4
NET "LED<3>"      LOC = "p7"                         ; # Bank = 3, Signal name = LD3
NET "LED<2>"      LOC = "p8"                         ; # Bank = 3, Signal name = LD2
NET "LED<1>"      LOC = "p14"                        ; # Bank = 3, Signal name = LD1
NET "LED<0>"      LOC = "p15"                        ; # Bank = 3, Signal name = LD0

# Pin assignment for SWs
NET "SW<7>"       LOC = "p6"                         ; # Bank = 3, Signal name = SW7
NET "SW<6>"       LOC = "p10"                        ; # Bank = 3, Signal name = SW6
NET "SW<5>"       LOC = "p12"                        ; # Bank = 3, Signal name = SW5
NET "SW<4>"       LOC = "p18"                        ; # Bank = 3, Signal name = SW4
NET "SW<3>"       LOC = "p24"                        ; # Bank = 3, Signal name = SW3
NET "SW<2>"       LOC = "p29"                        ; # Bank = 3, Signal name = SW2
NET "SW<1>"       LOC = "p36"                        ; # Bank = 3, Signal name = SW1
NET "SW<0>"       LOC = "p38"                        ; # Bank = 2, Signal name = SW0

# Pin assignment for BTNs
NET "BTN<3>"      LOC = "p41"                        ; # Bank = 2, Signal name = BTN3
NET "BTN<2>"      LOC = "p47"                        ; # Bank = 2, Signal name = BTN2
NET "BTN<1>"      LOC = "p48"                        ; # Bank = 2, Signal name = BTN1
NET "BTN<0>"      LOC = "p69"                        ; # Bank = 2, Signal name = BTN0

# Loop back/demo signals
# Pin assignment for PS2
NET "PS2C"        LOC = "p96"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = PS2C
NET "PS2D"        LOC = "p97"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = PS2D

# Pin assignment for VGA
NET "HSYNC_N"       LOC = "p39"  | DRIVE = 2           ; # Bank = 2, Signal name = HSYNC
NET "VSYNC_N"       LOC = "p35"  | DRIVE = 2           ; # Bank = 3, Signal name = VSYNC
NET "VGARED<2>"   LOC = "p67"  | DRIVE = 2           ; # Bank = 2, Signal name = RED2
NET "VGARED<1>"   LOC = "p68"  | DRIVE = 2           ; # Bank = 2, Signal name = RED1
NET "VGARED<0>"   LOC = "p70"  | DRIVE = 2           ; # Bank = 2, Signal name = RED0
NET "VGAGREEN<2>" LOC = "p50"  | DRIVE = 2           ; # Bank = 2, Signal name = GRN2
NET "VGAGREEN<1>" LOC = "p51"  | DRIVE = 2           ; # Bank = 2, Signal name = GRN1 
NET "VGAGREEN<0>" LOC = "p52"  | DRIVE = 2           ; # Bank = 2, Signal name = GRN0 
NET "VGABLUE<1>"  LOC = "p43"  | DRIVE = 2           ; # Bank = 2, Signal name = BLU2 
NET "VGABLUE<0>"  LOC = "p44"  | DRIVE = 2           ; # Bank = 2, Signal name = BLU1 

# Pin assignment for Expansion Ports

NET "JA_1"       LOC = "p81" | DRIVE = 6 ; 
NET "JA_2"       LOC = "p91" | DRIVE = 6 ; 
NET "JA_3"       LOC = "p82" | DRIVE = 6 ; 
NET "JA_4"       LOC = "p92" | DRIVE = 6 ; 

NET "JB_1"       LOC = "p87"  ; 
NET "JB_2"       LOC = "p93"  ; 
NET "JB_3"       LOC = "p88"  ; 
NET "JB_4"       LOC = "p94"  ; 

NET "JC_1"       LOC = "p77"  ; 
NET "JC_2"       LOC = "p86"  ; 
NET "JC_3"       LOC = "p76"  ; 
NET "JC_4"       LOC = "p85"  ; 

NET "RTS"        LOC = "p75"  ; 
NET "CTS"        LOC = "p59"  ; 
NET "RXD"        LOC = "p74"  ; 
NET "TXD"        LOC = "p58"  ;