Subversion Repositories socgen

# clock pin for Phoenix Board
NET "A_CLK" LOC = "A8"; # Bank = 0, Pin name = IO_L32P_0/GCLK6, Type = GCLK, Signal name = GCLK
NET "B_CLK" LOC = "R9"; #

NET "SEG<0>" LOC = "F13"; # Bank = 2, Pin name = IO_L21P_2, Type = I/O, Signal name = R-CA
NET "SEG<1>" LOC = "E13"; # Bank = 2, Pin name = IO_L19N_2, Type = I/O, Signal name = R-CB
NET "SEG<2>" LOC = "G15"; # Bank = 2, Pin name = IO_L24P_2, Type = I/O, Signal name = R-CC
NET "SEG<3>" LOC = "H13"; # Bank = 2, Pin name = IO_L39N_2, Type = I/O, Signal name = R-CD
NET "SEG<4>" LOC = "J14"; # Bank = 3, Pin name = IO_L39N_3, Type = I/O, Signal name = R-CE
NET "SEG<5>" LOC = "E14"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Signal name = R-CF
NET "SEG<6>" LOC = "G16"; # Bank = 2, Pin name = IO, Type = I/O, Signal name = R-CG
NET "DP"     LOC = "H14"; # Bank = 2, Pin name = IO_L39P_2, Type = I/O, Signal name = R-CDP

NET "AN<3>"  LOC = "F12"; # Bank = 2, Pin name = IO_L21N_2, Type = I/O, Signal name = R-AN1
NET "AN<2>"  LOC = "G13"; # Bank = 2, Pin name = IO_L23P_2, Type = I/O, Signal name = R-AN2
NET "AN<1>"  LOC = "G12"; # Bank = 2, Pin name = IO_L23N_2/VREF_2, Type = VREF, Signal name = R-AN3
NET "AN<0>"  LOC = "G14"; # Bank = 2, Pin name = IO_L24N_2, Type = I/O, Signal name = R-AN4

NET "LED<7>" LOC = "R16" ; # Bank = 3, Pin name = IO_L01P_3/VRN_3, Type = DCI, Signal name = LD7
NET "LED<6>" LOC = "P14" ; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Signal name = LD6
NET "LED<5>" LOC = "M13" ; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Signal name = LD5
NET "LED<4>" LOC = "N14" ; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Signal name = LD4
NET "LED<3>" LOC = "L12" ; # Bank = 3, Pin name = IO_L23P_3/VREF_3, Type = VREF, Signal name = LD3
NET "LED<2>" LOC = "M14" ; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Signal name = LD2
NET "LED<1>" LOC = "L13" ; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Signal name = LD1
NET "LED<0>" LOC = "L14" ; # Bank = 3, Pin name = IO_L22P_3, Type = I/O, Signal name = LD0

NET "SW<7>"  LOC = "N16"; # Bank = 3, Pin name = IO_L17N_3, Type = I/O, Signal name = SW7/XD7
NET "SW<6>"  LOC = "M15"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Signal name = SW6/XD6
NET "SW<5>"  LOC = "M16"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Signal name = SW5/XD5
NET "SW<4>"  LOC = "L15"; # Bank = 3, Pin name = IO_L22N_3, Type = I/O, Signal name = SW4/XD4
NET "SW<3>"  LOC = "K15"; # Bank = 3, Pin name = IO, Type = I/O, Signal name = SW3/XD3
NET "SW<2>"  LOC = "K16"; # Bank = 3, Pin name = IO_L40P_3, Type = I/O, Signal name = SW2/XD2
NET "SW<1>"  LOC = "J16"; # Bank = 3, Pin name = IO_L40N_3/VREF_3, Type = VREF, Signal name = SW1/XD1
NET "SW<0>"  LOC = "N15"; # Bank = 3, Pin name = IO_L17P_3/VREF_3, Type = VREF, Signal name = SW0/XD0


NET "BTN<3>" LOC = "K12"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Signal name = BTN3
NET "BTN<2>" LOC = "K13"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Signal name = BTN2
NET "BTN<1>" LOC = "K14"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Signal name = BTN1
NET "BTN<0>" LOC = "J13"; # Bank = 3, Pin name = IO_L39P_3, Type = I/O, Signal name = BTN0


NET "JA_1" LOC = "T14"  | DRIVE = 8  ; # Bank = 4, Pin name = IO, Type = I/O, Signal name = R-JA1
NET "JA_2" LOC = "R13"  | DRIVE = 8  ; # Bank = 4, Pin name = IO_L01N_4/VRP_4, Type = DCI, Signal name = R-JA2
NET "JA_3" LOC = "T13"  | DRIVE = 8  ; # Bank = 4, Pin name = IO_L01P_4/VRN_4, Type = DCI, Signal name = R-JA3
NET "JA_4" LOC = "R12"  | DRIVE = 8  ; # Bank = 4, Pin name = IO_L25P_4, Type = I/O, Signal name = R-JA4


NET "JB_1" LOC = "T12"  | DRIVE = 2  ; # Bank = 4, Pin name = IO, Type = I/O, Signal name = R-JB1
NET "JB_2" LOC = "R11"  | DRIVE = 2  ; # Bank = 4, Pin name = IO_L28P_4, Type = I/O, Signal name = R-JB2
NET "JB_3" LOC = "P8"   | DRIVE = 2  ; # Bank = 5, Pin name = IO_L32N_5/GCLK3, Type = GCLK, Signal name = R-JB3
NET "JB_4" LOC = "T10"  | DRIVE = 2  ; # Bank = 4, Pin name = IO/VREF_4, Type = VREF, Signal name = R-JB4


NET "JC_1" LOC = "D5"   | DRIVE = 2  ; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Signal name = R-JC1
NET "JC_2" LOC = "P9"   | DRIVE = 2  ; # Bank = 4, Pin name = IO_L31P_4/DOUT/BUSY, Type = DUAL, Signal name = R-JC2
NET "JC_3" LOC = "A5"   | DRIVE = 2  ; # Bank = 0, Pin name = IO, Type = I/O, Signal name = R-JC3
NET "JC_4" LOC = "A7"   | DRIVE = 2  ; # Bank = 0, Pin name = IO, Type = I/O, Signal name = R-JC4

NET "RTS" LOC = "A9"   | DRIVE = 2   ; # Bank = 1, Pin name = IO, Type = I/O, Signal name = R-JD1
NET "CTS" LOC = "A12"  | DRIVE = 2   ; # Bank = 1, Pin name = IO, Type = I/O, Signal name = R-JD2
NET "RXD" LOC = "C10"  | DRIVE = 2   ; # Bank = 1, Pin name = IO, Type = I/O, Signal name = R-JD3
NET "TXD" LOC = "D12"  | DRIVE = 2   ; # Bank = 1, Pin name = IO/VREF_1, Type = VREF, Signal name = R-JD4 



# Pin assignment for OnBoardMemCtrl
# Connected to Phoenix onBoard Cellular RAM and StrataFlash


NET "MEMOE" LOC = "K2"; # Bank = 6, Pin name = IO_L24P_6, Type = I/O, Signal name = OE
NET "MEMWR" LOC = "T3"; # Bank = 5, Pin name = IO_L01N_5/RDWR_B, Type = DUAL, Signal name = WE
NET "RAMADV" LOC = "B1"; # Bank = 7, Pin name = IO_L01P_7/VRN_7, Type = DCI, Signal name = MT-ADV
NET "RAMCS" LOC = "K1"; # Bank = 6, Pin name = IO, Type = I/O, Signal name = MT-CE
NET "RAMCLK" LOC = "C2"; # Bank = 7, Pin name = IO_L16N_7, Type = I/O, Signal name = MT-CLK
NET "RAMCRE" LOC = "L2"; # Bank = 6, Pin name = IO_L22P_6, Type = I/O, Signal name = MT-CRE
NET "RAMLB" LOC = "J1"; # Bank = 6, Pin name = IO_L40P_6/VREF_6, Type = VREF, Signal name = MT-LB
NET "RAMUB" LOC = "J2"; # Bank = 6, Pin name = IO_L40N_6, Type = I/O, Signal name = MT-UB
NET "RAMWAIT" LOC = "C1"; # Bank = 7, Pin name = IO_L01N_7/VRP_7, Type = DCI, Signal name = MT-WAIT
NET "FLASHRP" LOC = "T4"; # Bank = 5, Pin name = IO_L10N_5/VRP_5, Type = DCI, Signal name = RP#
NET "FLASHCS" LOC = "E4"; # Bank = 7, Pin name = IO_L21P_7, Type = I/O, Signal name = ST-CE
NET "FLASHSTSTS" LOC = "R4"; # Bank = 5, Pin name = IO_L10P_5/VRN_5, Type = DCI, Signal name = ST-STS


NET "MEMADR<1>" LOC = "J3";             # ADDR1
NET "MEMADR<2>" LOC = "K5";             # ADDR2
NET "MEMADR<3>" LOC = "L3";             # ADDR3
NET "MEMADR<4>" LOC = "J4";             # ADDR4
NET "MEMADR<5>" LOC = "K3";             # ADDR5
NET "MEMADR<6>" LOC = "H4";             # ADDR6
NET "MEMADR<7>" LOC = "K4";             # ADDR7
NET "MEMADR<8>" LOC = "G3";             # ADDR8
NET "MEMADR<9>" LOC = "E3";             # ADDR9
NET "MEMADR<10>" LOC = "F4";            # ADDR10
NET "MEMADR<11>" LOC = "F5";            # ADDR11
NET "MEMADR<12>" LOC = "N3";            # ADDR12
NET "MEMADR<13>" LOC = "L5";            # ADDR13
NET "MEMADR<14>" LOC = "M3";            # ADDR14
NET "MEMADR<15>" LOC = "F3";            # ADDR15
NET "MEMADR<16>" LOC = "L4";            # ADDR16
NET "MEMADR<17>" LOC = "G4";            # ADDR17
NET "MEMADR<18>" LOC = "H3";            # ADDR18
NET "MEMADR<19>" LOC = "G5";            # ADDR19
NET "MEMADR<20>" LOC = "D3";            # ADDR20
NET "MEMADR<21>" LOC = "M4";            # ADDR21
NET "MEMADR<22>" LOC = "A3";            # ADDR22
NET "MEMADR<23>" LOC = "C3";            # ADDR23

NET "MEMDB<0>" LOC = "M2" | PULLUP ; # Bank = 6, Pin name = IO_L20N_6, Type = I/O, Signal name = DB0
NET "MEMDB<1>" LOC = "M1" | PULLUP ; # Bank = 6, Pin name = IO_L20P_6, Type = I/O, Signal name = DB1
NET "MEMDB<2>" LOC = "N2" | PULLUP ; # Bank = 6, Pin name = IO_L17N_6, Type = I/O, Signal name = DB2
NET "MEMDB<3>" LOC = "N1" | PULLUP ; # Bank = 6, Pin name = IO_L17P_6/VREF_6, Type = VREF, Signal name = DB3
NET "MEMDB<4>" LOC = "P2" | PULLUP ; # Bank = 6, Pin name = IO_L16N_6, Type = I/O, Signal name = DB4
NET "MEMDB<5>" LOC = "P1" | PULLUP ; # Bank = 6, Pin name = IO_L01P_6/VRN_6, Type = DCI, Signal name = DB5
NET "MEMDB<6>" LOC = "R1" | PULLUP ; # Bank = 6, Pin name = IO_L01N_6/VRP_6, Type = DCI, Signal name = DB6
NET "MEMDB<7>" LOC = "R3" | PULLUP ; # Bank = 5, Pin name = IO_L01P_5/CS_B, Type = DUAL, Signal name = DB7
NET "MEMDB<8>" LOC = "H1" | PULLUP ; # Bank = 7, Pin name = IO_L40N_7/VREF_7, Type = VREF, Signal name = DB8
NET "MEMDB<9>" LOC = "G1" | PULLUP ; # Bank = 7, Pin name = IO_L40P_7, Type = I/O, Signal name = DB9
NET "MEMDB<10>" LOC = "G2" | PULLUP ; # Bank = 7, Pin name = IO, Type = I/O, Signal name = DB10
NET "MEMDB<11>" LOC = "F2" | PULLUP ; # Bank = 7, Pin name = IO_L22N_7, Type = I/O, Signal name = DB11
NET "MEMDB<12>" LOC = "E1" | PULLUP ; # Bank = 7, Pin name = IO_L20N_7, Type = I/O, Signal name = DB12
NET "MEMDB<13>" LOC = "D1" | PULLUP ; # Bank = 7, Pin name = IO_L17N_7, Type = I/O, Signal name = DB13
NET "MEMDB<14>" LOC = "E2" | PULLUP ; # Bank = 7, Pin name = IO_L20P_7, Type = I/O, Signal name = DB14
NET "MEMDB<15>" LOC = "D2" | PULLUP ; # Bank = 7, Pin name = IO_L17P_7, Type = I/O, Signal name = DB15




NET "EPPWait" LOC = "N5"; # Bank = , Pin name = IO, Type = I/O, Signal name = U-SLRD

NET "EPPASTB" LOC = "N8"; # Bank = 5, Pin name = IO_L32P_5/GCLK2, Type = GCLK, Signal name = U-FLAGA
NET "EPPDSTB" LOC = "P7"; # Bank = 5, Pin name = IO, Type = I/O, Signal name = U-FLAGB
NET "EPPWR" LOC = "N7"; # Bank = 5, Pin name = IO_L30N_5, Type = I/O, Signal name = U-FLAGC
NET "EPPDB<0>" LOC = "N12"; # Bank = 4, Pin name = IO/VREF_4, Type = VREF, Signal name = U-FD0
NET "EPPDB<1>" LOC = "P12"; # Bank = 4, Pin name = IO_L25N_4, Type = I/O, Signal name = U-FD1
NET "EPPDB<2>" LOC = "N11"; # Bank = 4, Pin name = IO_L27P_4/D1, Type = DUAL, Signal name = U-FD2
NET "EPPDB<3>" LOC = "P11"; # Bank = 4, Pin name = IO_L28N_4, Type = I/O, Signal name = U-FD3
NET "EPPDB<4>" LOC = "N10"; # Bank = 4, Pin name = IO_L29P_4, Type = I/O, Signal name = U-FD4
NET "EPPDB<5>" LOC = "P10"; # Bank = 4, Pin name = IO_L30N_4/D2, Type = DUAL, Signal name = U-FD5
NET "EPPDB<6>" LOC = "M10"; # Bank = 4, Pin name = IO_L29N_4, Type = I/O, Signal name = U-FD6
NET "EPPDB<7>" LOC = "R10"; # Bank = 4, Pin name = IO_L30P_4/D3, Type = DUAL, Signal name = U-FD7





# Loop Back tested signals
NET "PIO<0>" LOC = "B4"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L01N_0/VRP_0, Type = DCI, Signal name = R-IO1
NET "PIO<1>" LOC = "C5"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L25N_0, Type = I/O, Signal name = R-IO3
NET "PIO<2>" LOC = "E6"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L27N_0, Type = I/O, Signal name = R-IO5
NET "PIO<3>" LOC = "C6"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L28N_0, Type = I/O, Signal name = R-IO7
NET "PIO<4>" LOC = "E7"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L29N_0, Type = I/O, Signal name = R-IO9
NET "PIO<5>" LOC = "C7"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L30N_0, Type = I/O, Signal name = R-IO11
NET "PIO<6>" LOC = "D8"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L31N_0, Type = I/O, Signal name = R-IO13
NET "PIO<7>" LOC = "A10"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L31N_1/VREF_1, Type = VREF, Signal name = R-IO15
NET "PIO<8>" LOC = "A4"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L01P_0/VRN_0, Type = DCI, Signal name = R-IO2
NET "PIO<9>" LOC = "B5"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Signal name = R-IO4
NET "PIO<10>" LOC = "D6"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L27P_0, Type = I/O, Signal name = R-IO6
NET "PIO<11>" LOC = "B6"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L28P_0, Type = I/O, Signal name = R-IO8
NET "PIO<12>" LOC = "D7"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L29P_0, Type = I/O, Signal name = R-IO10
NET "PIO<13>" LOC = "B7"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L30P_0, Type = I/O, Signal name = R-IO12
NET "PIO<14>" LOC = "C8"   | DRIVE = 2  | PULLUP ; # Bank = 0, Pin name = IO_L31P_0/VREF_0, Type = VREF, Signal name = R-IO14
NET "PIO<15>" LOC = "B10"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L31P_1, Type = I/O, Signal name = R-IO16
NET "PIO<16>" LOC = "D10"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L30N_1, Type = I/O, Signal name = R-IO17
NET "PIO<17>" LOC = "B11"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L29N_1, Type = I/O, Signal name = R-IO19
NET "PIO<18>" LOC = "D11"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L28N_1, Type = I/O, Signal name = R-IO21
NET "PIO<19>" LOC = "B12"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L27N_1, Type = I/O, Signal name = R-IO23
NET "PIO<20>" LOC = "A13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Signal name = R-IO25
NET "PIO<21>" LOC = "A14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L01N_1/VRP_1, Type = DCI, Signal name = R-IO27
NET "PIO<22>" LOC = "B16"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L01N_2/VRP_2, Type = DCI, Signal name = R-IO29
NET "PIO<23>" LOC = "C15"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L16N_2, Type = I/O, Signal name = R-IO31
NET "PIO<24>" LOC = "E10"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L30P_1, Type = I/O, Signal name = R-IO18
NET "PIO<25>" LOC = "C11"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L29P_1, Type = I/O, Signal name = R-IO20
NET "PIO<26>" LOC = "E11"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L28P_1, Type = I/O, Signal name = R-IO22
NET "PIO<27>" LOC = "C12"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L27P_1, Type = I/O, Signal name = R-IO24
NET "PIO<28>" LOC = "B13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Signal name = R-IO26
NET "PIO<28>" LOC = "B14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Pin name = IO_L01P_1/VRN_1, Type = DCI, Signal name = R-IO28
NET "PIO<30>" LOC = "C16"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L01P_2/VRN_2, Type = DCI, Signal name = R-IO30
NET "PIO<31>" LOC = "D14"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L16P_2, Type = I/O, Signal name = R-IO32
NET "PIO<32>" LOC = "D15"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L17N_2, Type = I/O, Signal name = R-IO33
NET "PIO<33>" LOC = "E15"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Signal name = R-IO35
NET "PIO<34>" LOC = "F14"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L22N_2, Type = I/O, Signal name = R-IO37
NET "PIO<35>" LOC = "H16"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L40P_2/VREF_2, Type = VREF, Signal name = R-IO39
NET "PIO<36>" LOC = "D16"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L17P_2/VREF_2, Type = VREF, Signal name = R-IO34
NET "PIO<37>" LOC = "E16"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Signal name = R-IO36
NET "PIO<38>" LOC = "F15"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L22P_2, Type = I/O, Signal name = R-IO38
NET "PIO<39>" LOC = "H15"  | DRIVE = 2  | PULLUP ; # Bank = 2, Pin name = IO_L40N_2, Type = I/O, Signal name = R-IO40
NET "PIO<40>" LOC = "P16"  | DRIVE = 2  | PULLUP ; # Bank = 3, Pin name = IO_L01N_3/VRP_3, Type = DCI, Signal name = LCD-D/I = XIO1
NET "PIO<41>" LOC = "P15"  | DRIVE = 2  | PULLUP ; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Signal name = LCD-R/W = XIO2
NET "PIO<42>" LOC = "T7"   | DRIVE = 2  | PULLUP ; # Bank = 5, Pin name = IO_L31N_5/D4, Type = DUAL, Signal name = LCD-E = XIO3
NET "PIO<43>" LOC = "R7"   | DRIVE = 2  | PULLUP ; # Bank = 5, Pin name = IO_L31P_5/D5, Type = DUAL, Signal name = LCD-CS1 = XIO6
NET "PIO<44>" LOC = "R6"   | DRIVE = 2  | PULLUP ; # Bank = 5, Pin name = IO_L29N_5, Type = I/O, Signal name = LCD-CS2 = XIO5
NET "PIO<45>" LOC = "R5"   | DRIVE = 2  | PULLUP ; # Bank = 5, Pin name = IO_L27N_5/VREF_5, Type = VREF, Signal name = LCD-/RET = XIO4
NET "PIO<46>" LOC = "P5"   | DRIVE = 2  | PULLUP ; # Bank = 5, Pin name = IO_L27P_5, Type = I/O, Signal name = U-FIFOAD0 
NET "PIO<47>" LOC = "M7"   | DRIVE = 2  | PULLUP ; # Bank = 5, Pin name = IO_L30P_5, Type = I/O, Signal name = U-FIFOAD1