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https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilogLib] - Rev 119
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eval 'exec `which perl` -S $0 ${1+"$@"}'if 0;#/**********************************************************************/#/* */#/* ------- */#/* / SOC \ */#/* / GEN \ */#/* / TOOL \ */#/* ============== */#/* | | */#/* |____________| */#/* */#/* */#/* */#/* Author(s): */#/* - John Eaton, jt_eaton@opencores.org */#/* */#/**********************************************************************/#/* */#/* Copyright (C) <2010-2012> <Ouabache Design Works> */#/* */#/* This source file may be used and distributed without */#/* restriction provided that this copyright statement is not */#/* removed from the file and that any derivative work contains */#/* the original copyright notice and the associated disclaimer. */#/* */#/* This source file is free software; you can redistribute it */#/* and/or modify it under the terms of the GNU Lesser General */#/* Public License as published by the Free Software Foundation; */#/* either version 2.1 of the License, or (at your option) any */#/* later version. */#/* */#/* This source is distributed in the hope that it will be */#/* useful, but WITHOUT ANY WARRANTY; without even the implied */#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */#/* PURPOSE. See the GNU Lesser General Public License for more */#/* details. */#/* */#/* You should have received a copy of the GNU Lesser General */#/* Public License along with this source; if not, download it */#/* from http://www.opencores.org/lgpl.shtml */#/* */#/**********************************************************************/############################################################################# General PERL config############################################################################use Getopt::Long;use English;use File::Basename;use Cwd;use XML::LibXML;use lib './tools';use sys::lib;use yp::lib;$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.############################################################################### Process the options############################################################################Getopt::Long::config("require_order", "prefix=-");GetOptions("h","help","view=s" => \$view,"prefix=s" => \$prefix,"vendor=s" => \$vendor,"project=s" => \$project,"component=s" => \$component,"version=s" => \$version,"dest_dir=s" => \$dest_dir) || die "(use '$program_name -h' for help)";################################################################################ Help option##############################################################################if ( $opt_h or ($opt_help) ){print "\n gen_verilogLib -view {sim|syn} -prefix /work -vendor vendor_name -project project_name -component component_name -version version_name -dest_dir dest_dir";print "\n";exit 1;}##############################################################################################################################################################$home = cwd();my $variant;if($version) {$variant = "${component}_${version}";}else {$variant = "${component}";}my $lib_comp_sep = yp::lib::find_lib_comp_sep($vendor,$project);my $comp_xml_sep = yp::lib::find_ipxact_component_path("spirit:component",$vendor,$project,$component,$version);##############################################################################################################################################################print "\n Building $view Verilog Lib RTL for $prefix $project $component $verison $variant $dest_dir \n" ;my $path = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}";mkdir $path,0755 unless( -e $path );my $path = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/${view}";mkdir $path,0755 unless( -e $path );my $parser = XML::LibXML->new();my $spirit_component_file = $parser->parse_file(yp::lib::find_ipxact("spirit:component",$vendor,$project,$component,$version));foreach my $comp_view ($spirit_component_file->findnodes("//spirit:component/spirit:model/spirit:views/spirit:view/spirit:name[./text() = '$view']")){my($view_fileset) = $comp_view->findnodes('../spirit:fileSetRef/spirit:localName/text()')->to_literal ;#/**********************************************************************/#/* */#/* build a `define file for module names */#/* */#/* */#/* */#/* */#/**********************************************************************/my $outfile ="${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/deflist";open DEFLIST,">$outfile" or die "unable to open $outfile";print DEFLIST " \n";foreach my $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:logicalName")){my($def_logic) = $i_name ->findnodes('./text()')->to_literal ;my($def_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;if($def_logic ) {print DEFLIST sprintf( "\`define %s _%s\n", uc($def_logic) , $def_logic );}}#/**********************************************************************/#/* */#/* build a fileset in the following order */#/* */#/* deflist for module names */#/* all include files */#/* verilogSource files */#/* */#/* */#/**********************************************************************/my $outfile ="${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/filelist";open FILELIST,">$outfile" or die "unable to open $outfile";print FILELIST "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/deflist\n";foreach my $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name")){my($file_name) = $i_name ->findnodes('./text()')->to_literal ;my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;my($view_file) = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;if(($file_type eq "verilogInclude")&& (($view_file eq $view_fileset))){ print FILELIST "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${file_name}\n"};}foreach my $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name")){my($file_name) = $i_name ->findnodes('./text()')->to_literal ;my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;my($view_file) = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;if(($file_type eq "verilogSource")&& (($view_file eq $view_fileset))){ print FILELIST "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${file_name}\n"};}#/**********************************************************************/#/* */#/* Every leaf cell is processed through a the verilog preprocessor */#/* to customize the module names,remove all verilog tic(`) statements */#/* and to create seperate versions for simulation and synthesys */#/* */#/* */#/**********************************************************************/my $file_out = "${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/${view}/${variant}.v";if( -e $file_out ){$cmd ="rm $file_out \n";if (system($cmd)) {}};$cmd ="vppreproc --noline --noblank -DVARIANT=${variant} -I${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/../verilog -f ${home}${prefix}/${vendor}__${project}${lib_comp_sep}/${component}${comp_xml_sep}/${dest_dir}/filelist >> $file_out \n";if (system($cmd)) {}}1
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