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Subversion Repositories socgen
[/] [socgen/] [trunk/] [tools/] [verilog/] [gen_verilogLib] - Rev 131
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eval 'exec `which perl` -S $0 ${1+"$@"}'if 0;#/**********************************************************************/#/* */#/* ------- */#/* / SOC \ */#/* / GEN \ */#/* / TOOL \ */#/* ============== */#/* | | */#/* |____________| */#/* */#/* */#/* */#/* Author(s): */#/* - John Eaton, jt_eaton@opencores.org */#/* */#/**********************************************************************/#/* */#/* Copyright (C) <2010-2012> <Ouabache Design Works> */#/* */#/* This source file may be used and distributed without */#/* restriction provided that this copyright statement is not */#/* removed from the file and that any derivative work contains */#/* the original copyright notice and the associated disclaimer. */#/* */#/* This source file is free software; you can redistribute it */#/* and/or modify it under the terms of the GNU Lesser General */#/* Public License as published by the Free Software Foundation; */#/* either version 2.1 of the License, or (at your option) any */#/* later version. */#/* */#/* This source is distributed in the hope that it will be */#/* useful, but WITHOUT ANY WARRANTY; without even the implied */#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */#/* PURPOSE. See the GNU Lesser General Public License for more */#/* details. */#/* */#/* You should have received a copy of the GNU Lesser General */#/* Public License along with this source; if not, download it */#/* from http://www.opencores.org/lgpl.shtml */#/* */#/**********************************************************************/############################################################################# General PERL config############################################################################use Getopt::Long;use English;use File::Basename;use Cwd;use XML::LibXML;use lib './tools';use sys::lib;use yp::lib;$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.############################################################################### Process the options############################################################################Getopt::Long::config("require_order", "prefix=-");GetOptions("h","help","envidentifier=s" => \$envidentifier,"prefix=s" => \$prefix,"vendor=s" => \$vendor,"library=s" => \$library,"component=s" => \$component,"version=s" => \$version,"dest_dir=s" => \$dest_dir,"view=s" => \$view) || die "(use '$program_name -h' for help)";################################################################################ Help option##############################################################################if ( $opt_h or ($opt_help) ){print "\n gen_verilogLib -envidentifier *simulation* -prefix /work -vendor vendor_name -library library_name -component component_name -version version_name -dest_dir dest_dir";print "\n";exit 1;}##############################################################################################################################################################my $parser = XML::LibXML->new();my $socgen_file = $parser->parse_file(yp::lib::find_componentConfiguration($vendor,$library,$component));my $ip_name_base_macro = $socgen_file->findnodes("//socgen:componentConfiguration/socgen:ip_name_base_macro/text()")->to_literal;$home = cwd();my @search_paths = ();my $variant;if($version) {$variant = "${component}_${version}";}else {$variant = "${component}";}my $lib_comp_sep = yp::lib::find_lib_comp_sep($vendor,$library,$component);my $comp_xml_sep = yp::lib::find_comp_xml_sep($vendor,$library,$component,$version);my $module_name = yp::lib::get_module_name($vendor,$library,$component,$version);my $parser = XML::LibXML->new();my $spirit_component_file = $parser->parse_file(yp::lib::find_ipxact_component($vendor,$library,$component,$version));print "\n Building $view Verilog Lib RTL for $prefix $library $component $verison $variant $dest_dir \n" ;my $path = "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}";mkdir $path,0755 unless( -e $path );my $path = "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/../defines";mkdir $path,0755 unless( -e $path );my $path = "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/../filelists";mkdir $path,0755 unless( -e $path );my $path = "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/${view}";mkdir $path,0755 unless( -e $path );#/**********************************************************************/#/* */#/* build a `define file for module names */#/* */#/* */#/* */#/* */#/**********************************************************************/my $outfile ="${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/../defines/${variant}.v";open DEFLIST,">$outfile" or die "unable to open $outfile";print DEFLIST " \`define $ip_name_base_macro ${module_name} \n";my $outfile ="${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/../filelists/${variant}.MOD";open FILELIST,">$outfile" or die "unable to open $outfile";my $outfile ="${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/../filelists/${variant}.INC";open INCLIST,">$outfile" or die "unable to open $outfile";print INCLIST "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/../defines/${variant}.v\n";#print " FFFFFFFFFFFFFFFF $envidentifier $view \n" ;my @filelist = yp::lib::parse_component_brothers("$vendor","$library","$component","$version");foreach $line (@filelist){$_ = $line;if(/::(\S+)::(\S+)::(\S+)::(\S+)::/){$new_library = $2;$new_component = $3;$new_vendor = $1;$new_version = $4;# print " FFFFFFFFFFFFFFFF Brother $new_vendor $new_library $new_component $new_version \n" ;my $spirit_component_file = $parser->parse_file(yp::lib::find_ipxact_component($new_vendor,$new_library,$new_component,$new_version));foreach my $comp_view ($spirit_component_file->findnodes("//spirit:component/spirit:model/spirit:views/spirit:view/spirit:envIdentifier[./text() = '$envidentifier']")){my($view_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal ;my($view_fileset) = $comp_view->findnodes('../spirit:fileSetRef/spirit:localName/text()')->to_literal ;# print " FFFFFFFFFFFFFFFF Found $view_name $view_fileset \n" ;#/**********************************************************************/#/* */#/* build a fileset in the following order */#/* */#/* deflist for module names */#/* all include files */#/* all module files */#/* */#/* */#/**********************************************************************/foreach my $i_name ($spirit_component_file->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name")){my($file_name) = $i_name ->findnodes('./text()')->to_literal ;my($file_logicalname) = $i_name ->findnodes('../spirit:logicalName/text()')->to_literal ;my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;my($file_usertype) = $i_name ->findnodes('../spirit:userFileType/text()')->to_literal ;my($view_file) = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;# print " FFFFFFFFFFFFFFFX $file_name $file_logicalname $file_type $file_usertype $view_file \n" ;if(($file_usertype eq "include")&& ($view_file eq $view_fileset) && ($file_type eq "verilogSource") ){print INCLIST "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${file_name}\n";};if(($file_usertype eq "libraryDir")&& ($view_file eq $view_fileset) && ($file_type eq "verilogSource") ){push @search_paths, "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${file_name}";};if(($file_usertype eq "module") && ($view_file eq $view_fileset) && ($file_type eq "verilogSource") ){print FILELIST "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${file_name}\n";if($file_logicalname ){print DEFLIST sprintf( "\`define %s _%s\n", uc($file_logicalname) , $file_logicalname );}};}}}}#/**********************************************************************/#/* */#/* Every leaf cell is processed through a the verilog preprocessor */#/* to customize the module names,remove all verilog tic(`) statements */#/* and to create seperate versions for simulation and synthesys */#/* */#/* */#/**********************************************************************/my $file_out = "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/${view}/${variant}.v";if( -e $file_out ){$cmd ="rm $file_out \n";if (system($cmd)) {}};my $cmd_path;foreach $search_path (@search_paths){$cmd_path = " $cmd_path -I${search_path} " ;}$cmd ="vppreproc --noline --noblank $cmd_path -f ${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/../filelists/${variant}.INC -f ${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}${comp_xml_sep}/${dest_dir}/../filelists/${variant}.MOD >> $file_out \n";if (system($cmd)) {}1
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