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# Constraints for Digilent XC3S200 board.

# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns
NET "clk50" TNM_NET = "clk50" ;
TIMESPEC "TS_clk" = PERIOD "clk50" 18.0 ns ;

# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns = 4 ns delay + 1 ns margin
NET "sysclk" TNM_NET = "sysclk" ;
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sync" = FROM FFS("*/syncdff_ff1") TO FFS("*/syncdff_ff2") 2 ns ;

NET "clk50"      LOC = "T9" ;
NET "led(0)"     LOC = "K12" | DRIVE = 6 ;
NET "led(1)"     LOC = "P14" | DRIVE = 6 ;
NET "led(2)"     LOC = "L12" | DRIVE = 6 ;
NET "led(3)"     LOC = "N14" | DRIVE = 6 ;
NET "led(4)"     LOC = "P13" | DRIVE = 6 ;
NET "led(5)"     LOC = "N12" | DRIVE = 6 ;
NET "led(6)"     LOC = "P12" | DRIVE = 6 ;
NET "led(7)"     LOC = "P11" | DRIVE = 6 ;
NET "button(0)"  LOC = "M13" ;
NET "button(1)"  LOC = "M14" ;
NET "button(2)"  LOC = "L13" ;
NET "button(3)"  LOC = "L14" ;
NET "switch(0)"  LOC = "F12" ;
NET "switch(1)"  LOC = "G12" ;
NET "switch(2)"  LOC = "H14" ;
NET "switch(3)"  LOC = "H13" ;
NET "switch(4)"  LOC = "J14" ;
NET "switch(5)"  LOC = "J13" ;
NET "switch(6)"  LOC = "K14" ;
NET "switch(7)"  LOC = "K13" ;
NET "spw_di_p"   LOC = "B5" ; # | IOSTANDARD = LVDS_25;
NET "spw_di_n"   LOC = "C5" ; # | IOSTANDARD = LVDS_25;
NET "spw_si_p"   LOC = "D6" ; # | IOSTANDARD = LVDS_25;
NET "spw_si_n"   LOC = "E6" ; # | IOSTANDARD = LVDS_25;
NET "spw_do_p"   LOC = "B6" ; # | IOSTANDARD = LVDS_25;
NET "spw_do_n"   LOC = "C6" ; # | IOSTANDARD = LVDS_25;
NET "spw_so_p"   LOC = "D7" ; # | IOSTANDARD = LVDS_25;
NET "spw_so_n"   LOC = "E7" ; # | IOSTANDARD = LVDS_25;