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# Constraints for Pender GR-XC3S-1500 board (either revision).

# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns
NET "clk" TNM_NET = "clk" ;
TIMESPEC "TS_clk" = PERIOD "clk" 18.0 ns ;

# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns nominal = 4 ns data path + 1 ns margin
NET "sysclk" TNM_NET = "sysclk" ;
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sync" = FROM FFS("*/syncdff_ff1") TO FFS("*/syncdff_ff2") 2 ns ;

# Board clock
NET "clk"        LOC = "aa12" | IOSTANDARD = LVTTL; 

# Note: LEDs use inverted logic
NET "led(0)" LOC = "f11" | IOSTANDARD = LVTTL;
NET "led(1)" LOC = "e11" | IOSTANDARD = LVTTL;
NET "led(2)" LOC = "d11" | IOSTANDARD = LVTTL;
NET "led(3)" LOC = "c11" | IOSTANDARD = LVTTL;

NET "btn_reset" LOC = "D19" | IOSTANDARD = LVTTL;
NET "btn_clear" LOC = "D21" | IOSTANDARD = LVTTL;

NET "switch(0)"  LOC = "f16" | IOSTANDARD = LVTTL;
NET "switch(1)"  LOC = "f13" | IOSTANDARD = LVTTL;
NET "switch(2)"  LOC = "f12" | IOSTANDARD = LVTTL;
NET "switch(3)"  LOC = "e16" | IOSTANDARD = LVTTL;
NET "switch(4)"  LOC = "c22" | IOSTANDARD = LVTTL;
NET "switch(5)"  LOC = "c20" | IOSTANDARD = LVTTL;
NET "switch(6)"  LOC = "c21" | IOSTANDARD = LVTTL;
NET "switch(7)"  LOC = "d20" | IOSTANDARD = LVTTL;

NET "spw_rxdp" LOC = "m1";# | IOSTANDARD = LVDS_25;
NET "spw_rxdn" LOC = "m2";# | IOSTANDARD = LVDS_25;
NET "spw_rxsp" LOC = "m3";# | IOSTANDARD = LVDS_25;
NET "spw_rxsn" LOC = "m4";#  | IOSTANDARD = LVDS_25;
NET "spw_txdp" LOC = "n1";# | IOSTANDARD = LVDS_25;
NET "spw_txdn" LOC = "n2";# | IOSTANDARD = LVDS_25;
NET "spw_txsp" LOC = "n3";# | IOSTANDARD = LVDS_25;
NET "spw_txsn" LOC = "n4";# | IOSTANDARD = LVDS_25;

CONFIG PROHIBIT  = "aa14"; #"fpgadata" 
CONFIG PROHIBIT  = "w12"; #"fpgainit"