URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.fit.rpt] - Rev 40
Compare with Previous | Blame | View Log
Fitter report for spw_fifo_ulightMon Feb 5 00:57:17 2018Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. Parallel Compilation5. Fitter Netlist Optimizations6. Ignored Assignments7. Incremental Compilation Preservation Summary8. Incremental Compilation Partition Settings9. Incremental Compilation Placement Preservation10. Pin-Out File11. Fitter Resource Usage Summary12. Fitter Partition Statistics13. Input Pins14. Output Pins15. I/O Bank Usage16. All Package Pins17. I/O Assignment Warnings18. PLL Usage Summary19. Fitter Resource Utilization by Entity20. Delay Chain Summary21. Pad To Core Delay Chain Fanout22. Control Signals23. Global & Other Fast Signals24. Non-Global High Fan-Out Signals25. Routing Usage Summary26. I/O Rules Summary27. I/O Rules Details28. I/O Rules Matrix29. Fitter Device Options30. Operating Settings and Conditions31. Estimated Delay Added for Hold Timing Summary32. Estimated Delay Added for Hold Timing Details33. Fitter Messages34. Fitter Suppressed Messages----------------; Legal Notice ;----------------Copyright (C) 2017 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel FPGA IP License Agreement, or other applicable licenseagreement, including, without limitation, that your use is forthe sole purpose of programming logic devices manufactured byIntel and sold by Intel or its authorized distributors. Pleaserefer to the applicable agreement for further details.+----------------------------------------------------------------------------------------+; Fitter Summary ;+---------------------------------+------------------------------------------------------+; Fitter Status ; Successful - Mon Feb 5 00:57:17 2018 ;; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ;; Revision Name ; spw_fifo_ulight ;; Top-level Entity Name ; SPW_ULIGHT_FIFO ;; Family ; Cyclone V ;; Device ; 5CSEMA4U23C6 ;; Timing Models ; Final ;; Logic utilization (in ALMs) ; 3,362 / 15,880 ( 21 % ) ;; Total registers ; 4633 ;; Total pins ; 19 / 314 ( 6 % ) ;; Total virtual pins ; 0 ;; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;; Total RAM Blocks ; 0 / 270 ( 0 % ) ;; Total DSP Blocks ; 0 / 84 ( 0 % ) ;; Total HSSI RX PCSs ; 0 ;; Total HSSI PMA RX Deserializers ; 0 ;; Total HSSI TX PCSs ; 0 ;; Total HSSI PMA TX Serializers ; 0 ;; Total PLLs ; 1 / 5 ( 20 % ) ;; Total DLLs ; 0 / 4 ( 0 % ) ;+---------------------------------+------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+; Device ; 5CSEMA4U23C6 ; ;; Minimum Core Junction Temperature ; 0 ; ;; Maximum Core Junction Temperature ; 85 ; ;; Router Timing Optimization Level ; MAXIMUM ; Normal ;; Placement Effort Multiplier ; 4.0 ; 1.0 ;; Auto RAM to MLAB Conversion ; Off ; On ;; Power Optimization During Fitting ; Extra effort ; Normal compilation ;; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ;; Auto Delay Chains for High Fanout Input Pins ; On ; Off ;; Perform Physical Synthesis for Combinational Logic for Fitting ; On ; Off ;; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ;; Perform Asynchronous Signal Pipelining ; On ; Off ;; Physical Synthesis Effort Level ; Extra ; Normal ;; Logic Cell Insertion - Logic Duplication ; Off ; Auto ;; Auto Register Duplication ; Off ; Auto ;; Optimize Design for Metastability ; Off ; On ;; Use smart compilation ; Off ; Off ;; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Perform Clocking Topology Analysis During Routing ; Off ; Off ;; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;; Optimize Hold Timing ; All Paths ; All Paths ;; Optimize Multi-Corner Timing ; On ; On ;; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;; SSN Optimization ; Off ; Off ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize Timing for ECOs ; Off ; Off ;; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; Periphery to Core Placement and Routing Optimization ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Packed Registers ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Treat Bidirectional Pin as Output Pin ; Off ; Off ;; Perform Register Duplication for Performance ; Off ; Off ;; Perform Register Retiming for Performance ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;; Synchronizer Identification ; Auto ; Auto ;; Enable Beneficial Skew Optimization ; On ; On ;; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;; Clamping Diode ; Off ; Off ;; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;; Advanced Physical Optimization ; On ; On ;+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------++------------------------------------------+; Parallel Compilation ;+----------------------------+-------------+; Processors ; Number ;+----------------------------+-------------+; Number detected on machine ; 4 ;; Maximum allowed ; 2 ;; ; ;; Average used ; 1.09 ;; Maximum used ; 2 ;; ; ;; Usage by Processor ; % Time Used ;; Processor 1 ; 100.0% ;; Processor 2 ; 9.1% ;+----------------------------+-------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Netlist Optimizations ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;; FPGA_CLK1_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~41 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add1~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1_RESYN160_BDD161 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_RESYN126_BDD127 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_RESYN148_BDD149 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_RESYN150_BDD151 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_RESYN152_BDD153 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN138_BDD139 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN140_BDD141 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~53 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~55 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~56 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~66 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97_RESYN164_BDD165 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98_RESYN166_BDD167 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~99 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100_RESYN168_BDD169 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; debounce_db:db_system_spwulight_b|Add0~62 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; debounce_db:db_system_spwulight_b|counter~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|always5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|always5~1_RESYN162_BDD163 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|always5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0_RESYN26_BDD27 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1_RESYN170_BDD171 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add5~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add7~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Selector18~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|rd_ptr~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add1~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add2~26 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1_RESYN48_BDD49 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2_RESYN50_BDD51 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3_RESYN52_BDD53 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4_RESYN54_BDD55 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5_RESYN56_BDD57 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6_RESYN58_BDD59 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7_RESYN60_BDD61 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8_RESYN62_BDD63 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9_RESYN64_BDD65 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10_RESYN66_BDD67 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11_RESYN68_BDD69 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12_RESYN70_BDD71 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after850ns~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|always2~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13_RESYN72_BDD73 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0_RESYN24_BDD25 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1_RESYN104_BDD105 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1_RESYN154_BDD155 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1_RESYN156_BDD157 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0_RESYN158_BDD159 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Equal4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1_RESYN128_BDD129 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ShiftRight1~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4_RESYN146_BDD147 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1_RESYN10_BDD11 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~14 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~15 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN4_BDD5 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN6_BDD7 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~7 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~8 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN0_BDD1 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN2_BDD3 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18_RESYN130_BDD131 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21_RESYN40_BDD41 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN132_BDD133 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN134_BDD135 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25_RESYN136_BDD137 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~28 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1_RESYN12_BDD13 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1_RESYN120_BDD121 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3_RESYN122_BDD123 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4_RESYN124_BDD125 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1_RESYN142_BDD143 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0_RESYN144_BDD145 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3_RESYN76_BDD77 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5_RESYN78_BDD79 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10_RESYN80_BDD81 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.000~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9_RESYN98_BDD99 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10_RESYN100_BDD101 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN108_BDD109 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN110_BDD111 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13_RESYN112_BDD113 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14_RESYN114_BDD115 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0_RESYN14_BDD15 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0_RESYN16_BDD17 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2_RESYN18_BDD19 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3_RESYN84_BDD85 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~4 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5_RESYN20_BDD21 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[0]~output ; I ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[1]~output ; I ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[2]~output ; I ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[3]~output ; I ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[4]~output ; I ; ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------++---------------------------------------------------------------------------------------------+; Ignored Assignments ;+--------------+-----------------+--------------+------------+---------------+----------------+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;+--------------+-----------------+--------------+------------+---------------+----------------+; I/O Standard ; SPW_ULIGHT_FIFO ; ; KEY ; 3.3-V LVTTL ; QSF Assignment ;; I/O Standard ; SPW_ULIGHT_FIFO ; ; LED ; 3.3-V LVTTL ; QSF Assignment ;+--------------+-----------------+--------------+------------+---------------+----------------++----------------------------------------------------------------------------------------------------+; Incremental Compilation Preservation Summary ;+---------------------+----------------------+----------------------------+--------------------------+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;+---------------------+----------------------+----------------------------+--------------------------+; Placement (by node) ; ; ; ;; -- Requested ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ;; -- Achieved ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ;; ; ; ; ;; Routing (by net) ; ; ; ;; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;+---------------------+----------------------+----------------------------+--------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Incremental Compilation Partition Settings ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------++------------------------------------------------------------------------------------------------------------------------------------+; Incremental Compilation Placement Preservation ;+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+; Top ; 0.00 % ( 0 / 10065 ) ; N/A ; Source File ; N/A ; ;; hard_block:auto_generated_inst ; 0.00 % ( 0 / 18 ) ; N/A ; Source File ; N/A ; ;+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------++--------------+; Pin-Out File ;+--------------+The pin-out file can be found in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.pin.+---------------------------------------------------------------------------------------------+; Fitter Resource Usage Summary ;+-------------------------------------------------------------+-----------------------+-------+; Resource ; Usage ; % ;+-------------------------------------------------------------+-----------------------+-------+; Logic utilization (ALMs needed / total ALMs on device) ; 3,362 / 15,880 ; 21 % ;; ALMs needed [=A-B+C] ; 3,362 ; ;; [A] ALMs used in final placement [=a+b+c+d] ; 3,835 / 15,880 ; 24 % ;; [a] ALMs used for LUT logic and registers ; 1,626 ; ;; [b] ALMs used for LUT logic ; 1,539 ; ;; [c] ALMs used for registers ; 670 ; ;; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15,880 ; 3 % ;; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15,880 ; < 1 % ;; [a] Due to location constrained logic ; 0 ; ;; [b] Due to LAB-wide signal conflicts ; 10 ; ;; [c] Due to LAB input limits ; 6 ; ;; [d] Due to virtual I/Os ; 0 ; ;; ; ; ;; Difficulty packing design ; Low ; ;; ; ; ;; Total LABs: partially or completely used ; 464 / 1,588 ; 29 % ;; -- Logic LABs ; 464 ; ;; -- Memory LABs (up to half of total LABs) ; 0 ; ;; ; ; ;; Combinational ALUT usage for logic ; 5,522 ; ;; -- 7 input functions ; 72 ; ;; -- 6 input functions ; 1,329 ; ;; -- 5 input functions ; 874 ; ;; -- 4 input functions ; 1,532 ; ;; -- <=3 input functions ; 1,715 ; ;; Combinational ALUT usage for route-throughs ; 415 ; ;; ; ; ;; Dedicated logic registers ; 4,628 ; ;; -- By type: ; ; ;; -- Primary logic registers ; 4,592 / 31,760 ; 14 % ;; -- Secondary logic registers ; 36 / 31,760 ; < 1 % ;; -- By function: ; ; ;; -- Design implementation registers ; 4,628 ; ;; -- Routing optimization registers ; 0 ; ;; ; ; ;; Virtual pins ; 0 ; ;; I/O pins ; 19 / 314 ; 6 % ;; -- Clock pins ; 2 / 6 ; 33 % ;; -- Dedicated input pins ; 0 / 21 ; 0 % ;; I/O registers ; 5 ; ;; ; ; ;; Hard processor system peripheral utilization ; ; ;; -- Boot from FPGA ; 1 / 1 ( 100 % ) ; ;; -- Clock resets ; 1 / 1 ( 100 % ) ; ;; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;; -- S2F AXI ; 1 / 1 ( 100 % ) ; ;; -- F2S AXI ; 1 / 1 ( 100 % ) ; ;; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;; -- SDRAM ; 1 / 1 ( 100 % ) ; ;; -- Interrupts ; 0 / 1 ( 0 % ) ; ;; -- JTAG ; 0 / 1 ( 0 % ) ; ;; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;; -- STM event ; 0 / 1 ( 0 % ) ; ;; -- TPIU trace ; 1 / 1 ( 100 % ) ; ;; -- DMA ; 0 / 1 ( 0 % ) ; ;; -- CAN ; 0 / 2 ( 0 % ) ; ;; -- EMAC ; 0 / 2 ( 0 % ) ; ;; -- I2C ; 0 / 4 ( 0 % ) ; ;; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;; -- QSPI ; 0 / 1 ( 0 % ) ; ;; -- SDMMC ; 0 / 1 ( 0 % ) ; ;; -- SPI Master ; 0 / 2 ( 0 % ) ; ;; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;; -- UART ; 0 / 2 ( 0 % ) ; ;; -- USB ; 0 / 2 ( 0 % ) ; ;; ; ; ;; M10K blocks ; 0 / 270 ; 0 % ;; Total MLAB memory bits ; 0 ; ;; Total block memory bits ; 0 / 2,764,800 ; 0 % ;; Total block memory implementation bits ; 0 / 2,764,800 ; 0 % ;; ; ; ;; Total DSP Blocks ; 0 / 84 ; 0 % ;; ; ; ;; Fractional PLLs ; 1 / 5 ; 20 % ;; Global signals ; 4 ; ;; -- Global clocks ; 3 / 16 ; 19 % ;; -- Quadrant clocks ; 0 / 72 ; 0 % ;; -- Horizontal periphery clocks ; 0 / 12 ; 0 % ;; SERDES Transmitters ; 0 / 76 ; 0 % ;; SERDES Receivers ; 0 / 76 ; 0 % ;; JTAGs ; 0 / 1 ; 0 % ;; ASMI blocks ; 0 / 1 ; 0 % ;; CRC blocks ; 0 / 1 ; 0 % ;; Remote update blocks ; 0 / 1 ; 0 % ;; Oscillator blocks ; 0 / 1 ; 0 % ;; Impedance control blocks ; 0 / 3 ; 0 % ;; Hard Memory Controllers ; 0 / 2 ; 0 % ;; Average interconnect usage (total/H/V) ; 6.0% / 6.2% / 5.2% ; ;; Peak interconnect usage (total/H/V) ; 26.6% / 28.9% / 23.3% ; ;; Maximum fan-out ; 3073 ; ;; Highest non-global fan-out ; 2974 ; ;; Total fan-out ; 40291 ; ;; Average fan-out ; 3.79 ; ;+-------------------------------------------------------------+-----------------------+-------++---------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Partition Statistics ;+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+; Statistic ; Top ; ulight_fifo_hps_0_hps_io_border:border ; hard_block:auto_generated_inst ;+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+; Logic utilization (ALMs needed / total ALMs on device) ; 3362 / 15880 ( 21 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;; ALMs needed [=A-B+C] ; 3362 ; 0 ; 0 ;; [A] ALMs used in final placement [=a+b+c+d] ; 3835 / 15880 ( 24 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;; [a] ALMs used for LUT logic and registers ; 1626 ; 0 ; 0 ;; [b] ALMs used for LUT logic ; 1539 ; 0 ; 0 ;; [c] ALMs used for registers ; 670 ; 0 ; 0 ;; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; 0 ;; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15880 ( 3 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15880 ( < 1 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;; [a] Due to location constrained logic ; 0 ; 0 ; 0 ;; [b] Due to LAB-wide signal conflicts ; 10 ; 0 ; 0 ;; [c] Due to LAB input limits ; 6 ; 0 ; 0 ;; [d] Due to virtual I/Os ; 0 ; 0 ; 0 ;; ; ; ; ;; Difficulty packing design ; Low ; Low ; Low ;; ; ; ; ;; Total LABs: partially or completely used ; 464 / 1588 ( 29 % ) ; 0 / 1588 ( 0 % ) ; 0 / 1588 ( 0 % ) ;; -- Logic LABs ; 464 ; 0 ; 0 ;; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; 0 ;; ; ; ; ;; Combinational ALUT usage for logic ; 5522 ; 0 ; 0 ;; -- 7 input functions ; 72 ; 0 ; 0 ;; -- 6 input functions ; 1329 ; 0 ; 0 ;; -- 5 input functions ; 874 ; 0 ; 0 ;; -- 4 input functions ; 1532 ; 0 ; 0 ;; -- <=3 input functions ; 1715 ; 0 ; 0 ;; Combinational ALUT usage for route-throughs ; 415 ; 0 ; 0 ;; Memory ALUT usage ; 0 ; 0 ; 0 ;; -- 64-address deep ; 0 ; 0 ; 0 ;; -- 32-address deep ; 0 ; 0 ; 0 ;; ; ; ; ;; Dedicated logic registers ; 0 ; 0 ; 0 ;; -- By type: ; ; ; ;; -- Primary logic registers ; 4592 / 31760 ( 14 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;; -- Secondary logic registers ; 36 / 31760 ( < 1 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;; -- By function: ; ; ; ;; -- Design implementation registers ; 4628 ; 0 ; 0 ;; -- Routing optimization registers ; 0 ; 0 ; 0 ;; ; ; ; ;; ; ; ; ;; Virtual pins ; 0 ; 0 ; 0 ;; I/O pins ; 17 ; 0 ; 2 ;; I/O registers ; 5 ; 0 ; 0 ;; Total block memory bits ; 0 ; 0 ; 0 ;; Total block memory implementation bits ; 0 ; 0 ; 0 ;; Clock enable block ; 0 / 110 ( 0 % ) ; 0 / 110 ( 0 % ) ; 3 / 110 ( 2 % ) ;; Double data rate I/O output circuitry ; 5 / 304 ( 1 % ) ; 0 / 304 ( 0 % ) ; 0 / 304 ( 0 % ) ;; HPS DBG APB interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; Fractional PLL ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;; HPS boot from FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; HPS clock resets interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; FPGA-to-HPS interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; HPS FPGA-to-SDRAM interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; HPS-to-FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; HPS TPIU trace interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; PLL Output Counter ; 0 / 45 ( 0 % ) ; 0 / 45 ( 0 % ) ; 1 / 45 ( 2 % ) ;; PLL Reconfiguration Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;; PLL Reference Clock Select Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;; ; ; ; ;; Connections ; ; ; ;; -- Input Connections ; 4377 ; 0 ; 40 ;; -- Registered Input Connections ; 3099 ; 0 ; 0 ;; -- Output Connections ; 40 ; 0 ; 4377 ;; -- Registered Output Connections ; 1 ; 0 ; 0 ;; ; ; ; ;; Internal Connections ; ; ; ;; -- Total Connections ; 40728 ; 0 ; 4454 ;; -- Registered Connections ; 23593 ; 0 ; 0 ;; ; ; ; ;; External Connections ; ; ; ;; -- Top ; 0 ; 0 ; 4417 ;; -- ulight_fifo_hps_0_hps_io_border:border ; 0 ; 0 ; 0 ;; -- hard_block:auto_generated_inst ; 4417 ; 0 ; 0 ;; ; ; ; ;; Partition Interface ; ; ; ;; -- Input Ports ; 5 ; 0 ; 41 ;; -- Output Ports ; 10 ; 0 ; 106 ;; -- Bidir Ports ; 0 ; 0 ; 0 ;; ; ; ; ;; Registered Ports ; ; ; ;; -- Registered Input Ports ; 0 ; 0 ; 0 ;; -- Registered Output Ports ; 0 ; 0 ; 0 ;; ; ; ; ;; Port Connectivity ; ; ; ;; -- Input Ports driven by GND ; 0 ; 0 ; 0 ;; -- Output Ports driven by GND ; 0 ; 0 ; 0 ;; -- Input Ports driven by VCC ; 0 ; 0 ; 0 ;; -- Output Ports driven by VCC ; 0 ; 0 ; 0 ;; -- Input Ports with no Source ; 0 ; 0 ; 0 ;; -- Output Ports with no Source ; 0 ; 0 ; 0 ;; -- Input Ports with no Fanout ; 0 ; 0 ; 0 ;; -- Output Ports with no Fanout ; 0 ; 0 ; 0 ;+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+; FPGA_CLK1_50 ; Y13 ; 4A ; 38 ; 0 ; 0 ; 3074 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;; KEY[0] ; AH17 ; 4A ; 46 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;; KEY[1] ; AH16 ; 4A ; 46 ; 0 ; 51 ; 18 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;; din_a ; Y15 ; 4A ; 46 ; 0 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;; din_a(n) ; AA15 ; 4A ; 46 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;; sin_a ; AE20 ; 4A ; 51 ; 0 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;; sin_a(n) ; AD20 ; 4A ; 51 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+; LED[0] ; W15 ; 5A ; 68 ; 12 ; 20 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;; LED[1] ; AA24 ; 5A ; 68 ; 13 ; 37 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;; LED[2] ; V16 ; 5A ; 68 ; 13 ; 3 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;; LED[3] ; V15 ; 5A ; 68 ; 13 ; 20 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;; LED[4] ; AF26 ; 5A ; 68 ; 10 ; 77 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;; LED[5] ; AE26 ; 5A ; 68 ; 10 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;; LED[6] ; Y16 ; 5A ; 68 ; 12 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;; LED[7] ; AA23 ; 5A ; 68 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;; dout_a ; AG28 ; 4A ; 65 ; 0 ; 34 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;; dout_a(n) ; AH27 ; 4A ; 65 ; 0 ; 51 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;; sout_a ; AF20 ; 4A ; 53 ; 0 ; 34 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;; sout_a(n) ; AG20 ; 4A ; 53 ; 0 ; 51 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------++----------------------------------------------------------------------------+; I/O Bank Usage ;+----------+------------------+---------------+--------------+---------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;+----------+------------------+---------------+--------------+---------------+; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;; 3B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;; 4A ; 11 / 68 ( 16 % ) ; 2.5V ; -- ; 2.5V ;; 5A ; 8 / 16 ( 50 % ) ; 3.3V ; -- ; 3.3V ;; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;; 8A ; 0 / 13 ( 0 % ) ; 2.5V ; -- ; 2.5V ;+----------+------------------+---------------+--------------+---------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+; A2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; A3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A4 ; 357 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A5 ; 353 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A6 ; 347 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A7 ; 345 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A8 ; 343 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A9 ; 341 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A11 ; 339 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A12 ; 337 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A13 ; 335 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A14 ; 333 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A15 ; 331 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A16 ; 329 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A17 ; 321 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A18 ; 317 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A19 ; 315 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A20 ; 313 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A21 ; 311 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A22 ; 309 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; A23 ; 296 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;; A24 ; 283 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; A25 ; 281 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; A26 ; 279 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; A27 ; 275 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA4 ; 45 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AA5 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AA6 ; 29 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;; AA8 ; 36 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AA11 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AA12 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AA13 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AA14 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AA15 ; 114 ; 4A ; din_a(n) ; input ; LVDS ; ; Column I/O ; Y ; no ; Off ;; AA16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AA17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA18 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AA19 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AA20 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AA21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AA23 ; 180 ; 5A ; LED[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; AA24 ; 178 ; 5A ; LED[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; AA25 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; AA26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA27 ; 201 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AA28 ; 211 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB4 ; 43 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AB5 ; 32 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;; AB6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;; AB23 ; 176 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AB24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB28 ; 199 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AC4 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AC5 ; 33 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;; AC6 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;; AC7 ; 30 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;; AC8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AC21 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AC22 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AC23 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AC24 ; 174 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AC25 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AC26 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;; AC27 ; 197 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AC28 ; 195 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AD1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; AD2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AD4 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AD5 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AD6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AD7 ; 37 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;; AD8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AD9 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AD10 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AD11 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AD12 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AD13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AD15 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AD17 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AD18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AD19 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AD20 ; 127 ; 4A ; sin_a(n) ; input ; LVDS ; ; Column I/O ; Y ; no ; Off ;; AD21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AD22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AD23 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AD24 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;; AD25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AD26 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AD27 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AD28 ; 185 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AE4 ; 56 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE5 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;; AE6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE7 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE8 ; 64 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE9 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AE11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE12 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AE14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; AE15 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AE17 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AE19 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE20 ; 129 ; 4A ; sin_a ; input ; LVDS ; ; Column I/O ; Y ; no ; Off ;; AE21 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AE22 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE23 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE24 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AE25 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AE26 ; 168 ; 5A ; LED[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; AE27 ; 187 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AE28 ; 183 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AF4 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF5 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF6 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF7 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF8 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF9 ; 62 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF10 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF11 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;; AF13 ; 87 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AF15 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF16 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;; AF17 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AF20 ; 133 ; 4A ; sout_a ; output ; LVDS ; ; Column I/O ; Y ; no ; Off ;; AF21 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF22 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF23 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AF25 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF26 ; 166 ; 5A ; LED[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; AF27 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AF28 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AG3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AG4 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AG5 ; 80 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG6 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AG8 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG9 ; 93 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG11 ; 101 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AG13 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG14 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG15 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG16 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AG18 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG19 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG20 ; 131 ; 4A ; sout_a(n) ; output ; LVDS ; ; Column I/O ; Y ; no ; Off ;; AG21 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AG23 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG25 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG26 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AG28 ; 160 ; 4A ; dout_a ; output ; LVDS ; ; Column I/O ; Y ; no ; Off ;; AH2 ; 75 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH3 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH4 ; 78 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH5 ; 83 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH6 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH7 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH8 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH9 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AH11 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH12 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AH16 ; 115 ; 4A ; KEY[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AH17 ; 117 ; 4A ; KEY[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; AH18 ; 123 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH19 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AH21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH22 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH23 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH24 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH25 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; AH26 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; AH27 ; 158 ; 4A ; dout_a(n) ; output ; LVDS ; ; Column I/O ; Y ; no ; Off ;; B1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ;; B2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; B3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B4 ; 359 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B6 ; 355 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B8 ; 361 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B9 ; 363 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B10 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; B11 ; 362 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B12 ; 360 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B13 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; B14 ; 349 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B16 ; 324 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B18 ; 319 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B19 ; 325 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B21 ; 310 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; B22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B23 ; 298 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;; B24 ; 285 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; B25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B26 ; 273 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B28 ; 265 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C4 ; 368 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C5 ; 375 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C6 ; 373 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C7 ; 371 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C8 ; 369 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C9 ; 367 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C10 ; 365 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C12 ; 382 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C13 ; 354 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C14 ; 348 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C15 ; 340 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C16 ; 326 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C17 ; 318 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C18 ; 316 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C19 ; 323 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C20 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; C21 ; 308 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; C22 ; 302 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;; C23 ; 300 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;; C24 ; 289 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; C25 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; C26 ; 271 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; C27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; C28 ; 263 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; D1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; D2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D4 ; 370 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; D5 ; 377 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; D6 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; D7 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; D8 ; 387 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; D9 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D11 ; 398 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; D12 ; 380 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D14 ; 352 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; D15 ; 342 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D17 ; 332 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; D18 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; D19 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;; D20 ; 307 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;; D21 ; 304 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;; D22 ; 303 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;; D23 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; D24 ; 287 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; D25 ; 293 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;; D26 ; 269 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; D27 ; 257 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; D28 ; 255 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; E1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; E3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; E4 ; 364 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; E5 ; 376 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; E6 ; 432 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;; E7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; E8 ; 385 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; E9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; E10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; E11 ; 396 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; E12 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; E13 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; E14 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; E15 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;; E16 ; 334 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; E17 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; E18 ; 305 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;; E19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; E20 ; 306 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;; E21 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; E22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; E23 ; 295 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;; E24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; E25 ; 291 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; E26 ; 267 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; E27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; E28 ; 259 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; F1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; F4 ; 372 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; F5 ; 366 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; F6 ; 437 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;; F7 ; 435 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;; F8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;; F21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;; F22 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;; F23 ; 294 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;; F24 ; 292 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; F25 ; 284 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; F26 ; 282 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; F27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; F28 ; 249 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; G1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; G2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; G4 ; 374 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; G5 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; G6 ; 433 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;; G23 ; 290 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; G24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; G25 ; 276 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; G26 ; 253 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; G27 ; 251 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; G28 ; 247 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; H1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; H2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H4 ; 427 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; H5 ; 423 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; H6 ; 421 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; H8 ; 431 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;; H9 ; 430 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;; H10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H12 ; 358 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; H13 ; 356 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; H14 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H16 ; 344 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; H17 ; 322 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; H18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H19 ; 297 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; H23 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; H24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H25 ; 274 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H28 ; 261 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;; J5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J8 ; 429 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J10 ; 428 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;; J11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; J12 ; 338 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; J13 ; 336 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; J14 ; 330 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; J15 ; 328 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; J16 ; 346 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; J17 ; 320 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; J18 ; 314 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; J19 ; 299 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;; J20 ; 268 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; J21 ; 266 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; J24 ; 258 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; J25 ; 260 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; J26 ; 252 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; J27 ; 243 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; J28 ; 241 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K5 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;; K8 ; 426 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; K9 ; 436 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;; K10 ; 434 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; K18 ; 312 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; K19 ; 301 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; K24 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; K25 ; 244 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; K26 ; 250 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; K27 ; 245 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; K28 ; 239 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L4 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L8 ; 424 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; L9 ; 422 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; L10 ; 420 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; L11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; L12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L20 ; 288 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; L21 ; 286 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; L24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L25 ; 242 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; L26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; L27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L28 ; 237 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; M1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; M2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; M3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;; M5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; M18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; M19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; M24 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; M25 ; 246 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; M26 ; 234 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; M27 ; 236 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; M28 ; 235 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; N11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N20 ; 272 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; N21 ; 270 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; N24 ; 228 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; N25 ; 226 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; N26 ; 220 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; N27 ; 218 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; N28 ; 233 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; P14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; P15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; P24 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; P25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P26 ; 221 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; P27 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; P28 ; 231 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R16 ; 256 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R17 ; 254 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R18 ; 240 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R19 ; 238 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R20 ; 232 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R21 ; 230 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R24 ; 204 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R25 ; 210 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R26 ; 212 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R27 ; 219 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; R28 ; 229 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; T1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; T2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; T3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; T4 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; T5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; T8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; T9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; T11 ; 60 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; T12 ; 74 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; T13 ; 76 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; T15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; T16 ; 214 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; T17 ; 216 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; T18 ; 224 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; T19 ; 222 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; T20 ; 208 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; T21 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; T24 ; 202 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; T25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; T26 ; 196 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; T27 ; 205 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;; T28 ; 227 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; U4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;; U5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; U8 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; U9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; U10 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; U11 ; 58 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; U12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; U13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; U14 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; U15 ; 200 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; U16 ; 198 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; U18 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; U19 ; 206 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; U20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; U21 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; U25 ; 194 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; U26 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;; U27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; U28 ; 225 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; V11 ; 68 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; V12 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; V13 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V15 ; 181 ; 5A ; LED[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; V16 ; 179 ; 5A ; LED[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; V17 ; 192 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; V18 ; 190 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; V19 ; 188 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; V20 ; 186 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V24 ; 191 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; V25 ; 193 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; V26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V27 ; 217 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; V28 ; 223 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W5 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;; W8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; W9 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; W10 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;; W11 ; 66 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; W12 ; 82 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; W13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;; W14 ; 108 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; W15 ; 177 ; 5A ; LED[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; W16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W17 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; W20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W25 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; W26 ; 209 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; W27 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;; W28 ; 215 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; Y1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; Y2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;; Y3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y4 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; Y5 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; Y8 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; Y9 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;; Y10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;; Y11 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y13 ; 100 ; 4A ; FPGA_CLK1_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y15 ; 116 ; 4A ; din_a ; input ; LVDS ; ; Column I/O ; Y ; no ; Off ;; Y16 ; 175 ; 5A ; LED[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;; Y17 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; Y18 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; Y19 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y21 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;; Y24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y26 ; 207 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; Y27 ; 203 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;; Y28 ; 213 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+Note: Pin directions (input, output or bidir) are based on device operating in user mode.+-------------------------------------------------+; I/O Assignment Warnings ;+----------+--------------------------------------+; Pin Name ; Reason ;+----------+--------------------------------------+; LED[5] ; Missing drive strength and slew rate ;; LED[7] ; Missing drive strength and slew rate ;; LED[0] ; Missing drive strength and slew rate ;; LED[1] ; Missing drive strength and slew rate ;; LED[2] ; Missing drive strength and slew rate ;; LED[3] ; Missing drive strength and slew rate ;; LED[4] ; Missing drive strength and slew rate ;; LED[6] ; Missing drive strength and slew rate ;+----------+--------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+; PLL Usage Summary ;+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------+; ; ;+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------+; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll ; ;; -- PLL Type ; Integer PLL ;; -- PLL Location ; FRACTIONALPLL_X68_Y1_N0 ;; -- PLL Feedback clock type ; Global Clock ;; -- PLL Bandwidth ; Auto ;; -- PLL Bandwidth Range ; 1200000 to 600000 Hz ;; -- Reference Clock Frequency ; 50.0 MHz ;; -- Reference Clock Sourced by ; Dedicated Pin ;; -- PLL VCO Frequency ; 400.0 MHz ;; -- PLL Operation Mode ; Normal ;; -- PLL Freq Min Lock ; 37.500000 MHz ;; -- PLL Freq Max Lock ; 100.000000 MHz ;; -- PLL Enable ; On ;; -- PLL Fractional Division ; N/A ;; -- M Counter ; 16 ;; -- N Counter ; 2 ;; -- PLL Refclk Select ; ;; -- PLL Refclk Select Location ; PLLREFCLKSELECT_X68_Y7_N0 ;; -- PLL Reference Clock Input 0 source ; clk_0 ;; -- PLL Reference Clock Input 1 source ; clk_1 ;; -- ADJPLLIN source ; N/A ;; -- CORECLKIN source ; N/A ;; -- IQTXRXCLKIN source ; N/A ;; -- PLLIQCLKIN source ; N/A ;; -- RXIQCLKIN source ; N/A ;; -- CLKIN(0) source ; FPGA_CLK1_50~input ;; -- CLKIN(1) source ; N/A ;; -- CLKIN(2) source ; N/A ;; -- CLKIN(3) source ; N/A ;; -- PLL Output Counter ; ;; -- ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter ; ;; -- Output Clock Frequency ; 400.0 MHz ;; -- Output Clock Location ; PLLOUTPUTCOUNTER_X68_Y3_N1 ;; -- C Counter Odd Divider Even Duty Enable ; Off ;; -- Duty Cycle ; 50.0000 ;; -- Phase Shift ; 0.000000 degrees ;; -- C Counter ; 1 ;; -- C Counter PH Mux PRST ; 0 ;; -- C Counter PRST ; 1 ;; ; ;+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+; |SPW_ULIGHT_FIFO ; 3361.5 (0.5) ; 3835.0 (0.5) ; 488.5 (0.0) ; 15.0 (0.0) ; 0.0 (0.0) ; 5522 (1) ; 4628 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 19 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ;; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 109.5 (109.5) ; 117.7 (117.7) ; 9.2 (9.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 184 (184) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ;; |debounce_db:db_system_spwulight_b| ; 18.5 (18.5) ; 19.5 (19.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (37) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ;; |detector_tokens:m_x| ; 18.8 (9.2) ; 22.5 (10.3) ; 3.7 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (18) ; 38 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ;; |bit_capture_control:capture_c| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_control:capture_c ; bit_capture_control ; work ;; |bit_capture_data:capture_d| ; 1.7 (1.7) ; 2.8 (2.8) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_data:capture_d ; bit_capture_data ; work ;; |counter_neg:cnt_neg| ; 7.3 (7.3) ; 8.3 (8.3) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg ; counter_neg ; work ;; |spw_ulight_con_top_x:A_SPW_TOP| ; 839.8 (0.2) ; 1146.0 (0.5) ; 315.8 (0.2) ; 9.5 (0.0) ; 0.0 (0.0) ; 1060 (1) ; 1499 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ;; |fifo_rx:rx_data| ; 291.7 (50.6) ; 440.5 (58.3) ; 150.3 (7.7) ; 1.5 (0.0) ; 0.0 (0.0) ; 340 (87) ; 633 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ;; |mem_data:mem_dta_fifo_tx| ; 241.1 (241.1) ; 382.2 (382.2) ; 142.6 (142.6) ; 1.5 (1.5) ; 0.0 (0.0) ; 253 (253) ; 585 (585) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ;; |fifo_tx:tx_data| ; 287.5 (31.0) ; 418.8 (32.3) ; 139.3 (1.3) ; 8.0 (0.0) ; 0.0 (0.0) ; 299 (46) ; 627 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ;; |mem_data:mem_dta_fifo_tx| ; 256.5 (256.5) ; 386.6 (386.6) ; 138.1 (138.1) ; 8.0 (8.0) ; 0.0 (0.0) ; 253 (253) ; 585 (585) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ;; |top_spw_ultra_light:SPW| ; 260.3 (0.0) ; 286.2 (0.0) ; 25.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 420 (0) ; 239 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ;; |FSM_SPW:FSM| ; 75.6 (75.6) ; 78.3 (78.3) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 130 (130) ; 59 (59) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ;; |RX_SPW:RX| ; 41.0 (0.3) ; 50.5 (1.5) ; 9.5 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 66 (3) ; 75 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ;; |bit_capture_control:capture_c| ; 0.9 (0.9) ; 1.1 (1.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c ; bit_capture_control ; work ;; |bit_capture_data:capture_d| ; 2.6 (2.6) ; 3.2 (3.2) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d ; bit_capture_data ; work ;; |counter_neg:cnt_neg| ; 7.5 (7.5) ; 8.1 (8.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg ; counter_neg ; work ;; |rx_buffer_fsm:buffer_fsm| ; 1.3 (1.3) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm ; rx_buffer_fsm ; work ;; |rx_control_data_rdy:control_data_rdy| ; 3.0 (3.0) ; 3.7 (3.7) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy ; rx_control_data_rdy ; work ;; |rx_data_buffer_data_w:buffer_data_flag| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag ; rx_data_buffer_data_w ; work ;; |rx_data_control_p:data_control| ; 10.6 (10.6) ; 10.7 (10.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control ; rx_data_control_p ; work ;; |rx_data_receive:rx_dtarcv| ; 13.7 (13.7) ; 19.8 (19.8) ; 6.1 (6.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (28) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv ; rx_data_receive ; work ;; |TX_SPW:TX| ; 143.8 (0.0) ; 157.3 (0.0) ; 13.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 224 (0) ; 105 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ;; |tx_data_send:tx_data_snd| ; 23.3 (23.3) ; 23.3 (23.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (30) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd ; tx_data_send ; work ;; |tx_fsm_m:tx_fsm| ; 120.1 (81.2) ; 134.0 (91.8) ; 13.9 (10.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 194 (132) ; 76 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm ; tx_fsm_m ; work ;; |tx_fct_counter:tx_fct_cnt| ; 25.1 (25.1) ; 26.7 (26.7) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (42) ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt ; tx_fct_counter ; work ;; |tx_fct_send:tx_fct_snd| ; 13.8 (13.8) ; 15.5 (15.5) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 20 (20) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd ; tx_fct_send ; work ;; |ulight_fifo:u0| ; 2374.4 (0.0) ; 2528.8 (0.0) ; 158.9 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 4210 (0) ; 3049 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ;; |altera_reset_controller:rst_controller| ; 0.0 (0.0) ; 1.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; ulight_fifo ;; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;; |altera_reset_controller:rst_controller_001| ; 0.7 (0.0) ; 1.5 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ;; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.7 (0.7) ; 1.5 (1.5) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;; |ulight_fifo_auto_start:auto_start| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:data_read_en_rx| ; 0.8 (0.8) ; 1.3 (1.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:link_disable| ; 1.2 (1.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:link_start| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:timecode_tx_enable| ; 1.2 (1.2) ; 1.4 (1.4) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_auto_start:write_en_tx| ; 1.3 (1.3) ; 1.4 (1.4) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo_auto_start ; ulight_fifo ;; |ulight_fifo_clock_sel:clock_sel| ; 2.1 (2.1) ; 2.2 (2.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo_clock_sel ; ulight_fifo ;; |ulight_fifo_counter_rx_fifo:counter_rx_fifo| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 2.6 (2.6) ; 3.0 (3.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;; |ulight_fifo_counter_rx_fifo:fsm_info| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;; |ulight_fifo_data_flag_rx:data_flag_rx| ; 4.1 (4.1) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ;; |ulight_fifo_data_info:data_info| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:timecode_ready_rx| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_fifo_empty_rx_status:timecode_tx_ready| ; 0.5 (0.5) ; 0.7 (0.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;; |ulight_fifo_hps_0:hps_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo_hps_0 ; ulight_fifo ;; |ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces ; ulight_fifo_hps_0_fpga_interfaces ; ulight_fifo ;; |ulight_fifo_led_pio_test:led_pio_test| ; 2.9 (2.9) ; 4.2 (4.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 2337.0 (0.0) ; 2478.1 (0.0) ; 145.6 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 4124 (0) ; 2969 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ;; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.3 (3.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 20.1 (20.1) ; 21.0 (21.0) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 4.3 (4.3) ; 4.3 (4.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo| ; 20.2 (20.2) ; 20.2 (20.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo| ; 6.4 (6.4) ; 6.7 (6.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo| ; 14.7 (14.7) ; 17.7 (17.7) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo| ; 6.1 (6.1) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 17.0 (17.0) ; 18.2 (18.2) ; 1.3 (1.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 9.0 (9.0) ; 9.0 (9.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 18.3 (18.3) ; 18.5 (18.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 4.2 (4.2) ; 4.2 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 15.1 (15.1) ; 20.6 (20.6) ; 5.6 (5.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 20.7 (20.7) ; 22.0 (22.0) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.8 (2.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo| ; 17.2 (17.2) ; 18.8 (18.8) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 19.7 (19.7) ; 1.8 (1.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.8 (2.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo| ; 18.7 (18.7) ; 19.3 (19.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo| ; 14.4 (14.4) ; 17.5 (17.5) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo| ; 5.2 (5.2) ; 6.3 (6.3) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 17.7 (17.7) ; 19.0 (19.0) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 6.0 (6.0) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 21.0 (21.0) ; 21.6 (21.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 19.5 (19.5) ; 20.1 (20.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 20.8 (20.8) ; 22.2 (22.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo| ; 2.4 (2.4) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 17.0 (17.0) ; 17.0 (17.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 7.5 (7.5) ; 8.2 (8.2) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 17.6 (17.6) ; 17.6 (17.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 8.0 (8.0) ; 8.2 (8.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.8 (20.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.5 (20.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 2.5 (2.5) ; 3.1 (3.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 18.1 (18.1) ; 18.7 (18.7) ; 1.0 (1.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 9.0 (9.0) ; 9.2 (9.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 20.3 (20.3) ; 20.6 (20.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.6 (20.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 61.8 (29.2) ; 65.0 (32.7) ; 3.2 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 116 (57) ; 26 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 32.3 (32.3) ; 32.3 (32.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 44.3 (0.0) ; 47.3 (0.0) ; 3.0 (0.0) ; 0.1 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.3 (44.1) ; 47.3 (47.0) ; 3.0 (3.0) ; 0.1 (0.1) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 44.3 (0.0) ; 47.2 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (0) ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.3 (44.1) ; 47.2 (46.9) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (66) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 41.2 (0.0) ; 43.6 (0.0) ; 2.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 41.2 (40.9) ; 43.6 (43.1) ; 2.3 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 39.8 (0.0) ; 41.5 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.5) ; 41.5 (41.2) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 38.8 (0.0) ; 40.4 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.8 (38.5) ; 40.4 (40.1) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 39.0 (0.0) ; 40.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.0 (38.7) ; 40.5 (40.5) ; 1.5 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 44.6 (0.0) ; 48.7 (0.0) ; 4.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.6 (44.3) ; 48.7 (48.4) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 39.6 (0.0) ; 41.5 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.6 (39.3) ; 41.5 (41.2) ; 1.9 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 39.8 (0.0) ; 43.5 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.5) ; 43.5 (43.2) ; 3.7 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 39.3 (0.0) ; 41.6 (0.0) ; 2.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.3 (39.0) ; 41.6 (41.2) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 39.8 (0.0) ; 41.5 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.3) ; 41.5 (41.5) ; 1.7 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 40.2 (0.0) ; 44.7 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 61 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 40.2 (39.8) ; 44.7 (44.3) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 61 (60) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 44.7 (0.0) ; 48.1 (0.0) ; 3.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 66 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.7 (44.4) ; 48.1 (47.8) ; 3.4 (3.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 66 (66) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 45.7 (0.0) ; 49.6 (0.0) ; 3.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.7 (45.4) ; 49.6 (49.3) ; 3.9 (3.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 43.4 (0.0) ; 45.8 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.4 (43.2) ; 45.8 (45.6) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 39.3 (0.0) ; 40.8 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.3 (38.9) ; 40.8 (40.6) ; 1.6 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 41.5 (0.0) ; 42.3 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 41.5 (41.2) ; 42.3 (42.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 47.2 (0.0) ; 52.6 (0.0) ; 5.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 69 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 47.2 (47.0) ; 52.6 (52.3) ; 5.3 (5.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 46.0 (0.0) ; 47.6 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 70 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 46.0 (45.8) ; 47.6 (47.3) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 70 (69) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 40.5 (0.0) ; 42.3 (0.0) ; 1.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 40.5 (40.2) ; 42.3 (42.3) ; 1.8 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 46.8 (0.0) ; 50.0 (0.0) ; 3.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 70 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 46.8 (46.6) ; 50.0 (49.7) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 70 (70) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 45.7 (0.0) ; 48.0 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.7 (45.5) ; 48.0 (47.7) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;; |altera_merlin_slave_agent:auto_start_s1_agent| ; 14.8 (5.3) ; 14.8 (5.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 15.3 (5.7) ; 15.5 (5.7) ; 0.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.8 (9.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 12.2 (2.7) ; 12.2 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 12.0 (2.5) ; 13.2 (2.8) ; 1.1 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.6 (9.6) ; 10.3 (10.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 12.2 (2.2) ; 12.2 (2.2) ; 0.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:data_info_s1_agent| ; 11.7 (2.2) ; 12.6 (2.4) ; 0.9 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 10.2 (10.2) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 15.3 (5.5) ; 17.5 (6.3) ; 2.2 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 11.2 (11.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 11.8 (2.3) ; 11.8 (2.3) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 12.7 (2.5) ; 13.8 (2.7) ; 1.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 11.2 (11.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 12.1 (2.2) ; 12.1 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 12.1 (2.1) ; 12.1 (2.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 11.8 (2.2) ; 12.0 (2.3) ; 0.2 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.7 (9.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 14.9 (4.8) ; 16.6 (5.8) ; 1.7 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.8 (10.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:link_disable_s1_agent| ; 14.9 (5.4) ; 16.0 (6.8) ; 1.1 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:link_start_s1_agent| ; 15.2 (5.6) ; 15.5 (5.8) ; 0.3 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 11.6 (2.2) ; 11.7 (2.2) ; 0.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.5 (9.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 11.9 (2.2) ; 12.4 (2.5) ; 0.5 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.9 (9.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 15.5 (5.3) ; 15.8 (5.6) ; 0.2 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.2 (10.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 15.1 (5.4) ; 15.7 (5.8) ; 0.6 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.8 (9.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 12.1 (2.5) ; 12.1 (2.8) ; 0.0 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.3 (9.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 15.5 (5.4) ; 15.5 (5.5) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.0 (10.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 14.5 (5.2) ; 14.5 (5.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.3 (9.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;; |altera_merlin_slave_translator:auto_start_s1_translator| ; 2.1 (2.1) ; 3.3 (3.3) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 3.1 (3.1) ; 3.8 (3.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 2.6 (2.6) ; 3.4 (3.4) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 1.8 (1.8) ; 3.2 (3.2) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 3.0 (3.0) ; 4.4 (4.4) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:data_info_s1_translator| ; 1.8 (1.8) ; 3.2 (3.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 1.2 (1.2) ; 2.1 (2.1) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 1.1 (1.1) ; 1.9 (1.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 1.4 (1.4) ; 2.1 (2.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 1.9 (1.9) ; 2.5 (2.5) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 3.6 (3.6) ; 3.8 (3.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:link_disable_s1_translator| ; 2.5 (2.5) ; 2.8 (2.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:link_start_s1_translator| ; 2.3 (2.3) ; 3.0 (3.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 1.7 (1.7) ; 2.0 (2.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2.4 (2.4) ; 5.0 (5.0) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 3.5 (3.5) ; 4.5 (4.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 2.2 (2.2) ; 2.9 (2.9) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 1.0 (1.0) ; 1.6 (1.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 4.2 (4.2) ; 5.1 (5.1) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 2.3 (2.3) ; 2.8 (2.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 15.3 (15.3) ; 15.3 (15.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 14.4 (14.4) ; 14.4 (14.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 18.4 (18.4) ; 20.1 (20.1) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (35) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 31.6 (31.6) ; 31.6 (31.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 11.7 (9.8) ; 12.5 (10.5) ; 0.8 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (32) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 2.0 (2.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 7.0 (7.0) ; 8.1 (8.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 7.0 (7.0) ; 8.2 (8.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 6.7 (6.7) ; 7.8 (7.8) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 11.1 (9.6) ; 12.2 (10.7) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 6.8 (6.8) ; 7.2 (7.2) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 7.1 (7.1) ; 8.0 (8.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 12.3 (10.3) ; 12.7 (10.8) ; 0.3 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 12.0 (9.8) ; 11.9 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 1.9 (1.9) ; 2.2 (2.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 11.5 (9.7) ; 12.4 (10.6) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 14.5 (12.5) ; 14.5 (12.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (37) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 11.6 (9.6) ; 12.8 (10.5) ; 1.3 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.3 (2.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 6.6 (6.6) ; 6.6 (6.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 12.6 (10.8) ; 14.0 (12.2) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (35) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 10.6 (8.6) ; 12.1 (10.1) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (28) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 6.8 (6.8) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 6.3 (6.3) ; 6.3 (6.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 11.4 (9.9) ; 13.2 (10.7) ; 1.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (31) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |altera_merlin_arbitrator:arb| ; 1.5 (1.5) ; 2.5 (2.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 6.7 (6.7) ; 7.1 (7.1) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 6.4 (6.4) ; 6.7 (6.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_router:router| ; 10.2 (10.2) ; 13.2 (13.2) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (28) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_router:router_001| ; 16.0 (16.0) ; 18.3 (18.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 1.1 (1.1) ; 1.2 (1.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009| ; 1.5 (1.5) ; 1.7 (1.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014| ; 1.4 (1.4) ; 1.8 (1.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 1.5 (1.5) ; 1.7 (1.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 0.8 (0.8) ; 0.9 (0.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 37.3 (37.3) ; 36.9 (36.9) ; 0.3 (0.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 88 (88) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 127.2 (127.2) ; 135.9 (135.9) ; 10.3 (10.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 294 (294) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;; |ulight_fifo_pll_0:pll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo_pll_0 ; ulight_fifo ;; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ; altera_pll ; work ;; |altera_cyclonev_pll:cyclonev_pll| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll ; altera_cyclonev_pll ; work ;; |altera_cyclonev_pll_base:fpll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0 ; altera_cyclonev_pll_base ; work ;; |ulight_fifo_timecode_rx:timecode_rx| ; 2.8 (2.8) ; 3.3 (3.3) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo_timecode_rx ; ulight_fifo ;; |ulight_fifo_timecode_tx_data:timecode_tx_data| ; 3.3 (3.3) ; 6.0 (6.0) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo_timecode_tx_data ; ulight_fifo ;; |ulight_fifo_write_data_fifo_tx:write_data_fifo_tx| ; 2.5 (2.5) ; 7.6 (7.6) ; 5.1 (5.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo_write_data_fifo_tx ; ulight_fifo ;+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+-----------------------------------------------------------------------------------------------------------------------------+; Delay Chain Summary ;+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+; LED[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;; LED[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;; dout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;; sout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;; LED[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;; LED[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;; LED[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;; LED[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;; LED[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;; LED[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;; FPGA_CLK1_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;; din_a ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;; sin_a ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;; dout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;; sout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;; din_a(n) ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;; sin_a(n) ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Pad To Core Delay Chain Fanout ;+---------------------------------------------------------------------------------------------------------------+-------------------+---------+; Source Pin / Fanout ; Pad To Core Index ; Setting ;+---------------------------------------------------------------------------------------------------------------+-------------------+---------+; KEY[0] ; ; ;; FPGA_CLK1_50 ; ; ;; KEY[1] ; ; ;; - debounce_db:db_system_spwulight_b|PB_down~0 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|aux_pb~0 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~0 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~1 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~2 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~3 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~4 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~5 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~6 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~7 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~8 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~9 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~10 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~11 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~12 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~13 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~14 ; 0 ; 0 ;; - debounce_db:db_system_spwulight_b|counter~15 ; 0 ; 0 ;; din_a ; ; ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_1 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_0 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_1 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|control_bit_found ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 0 ; 0 ;; sin_a ; ; ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 1 ; 0 ;; din_a(n) ; ; ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_1 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_0 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_1 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|control_bit_found ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 0 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 0 ; 0 ;; sin_a(n) ; ; ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 1 ; 0 ;; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 1 ; 0 ;+---------------------------------------------------------------------------------------------------------------+-------------------+---------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+; FPGA_CLK1_50 ; PIN_Y13 ; 3073 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FF_X48_Y7_N35 ; 1319 ; Clock ; no ; -- ; -- ; -- ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FF_X61_Y4_N41 ; 105 ; Clock ; no ; -- ; -- ; -- ;; debounce_db:db_system_spwulight_b|aux_pb ; FF_X56_Y3_N59 ; 72 ; Async. clear ; no ; -- ; -- ; -- ;; detector_tokens:m_x|always5~1 ; LABCELL_X53_Y3_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; detector_tokens:m_x|comb ; LABCELL_X53_Y3_N27 ; 21 ; Clock ; no ; -- ; -- ; -- ;; detector_tokens:m_x|counter_neg:cnt_neg|WideOr8~0 ; LABCELL_X51_Y3_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; detector_tokens:m_x|negedge_clk ; LABCELL_X53_Y3_N39 ; 18 ; Clock ; no ; -- ; -- ; -- ;; detector_tokens:m_x|state_data_process.01 ; FF_X53_Y3_N11 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always5~0 ; LABCELL_X48_Y10_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~0 ; LABCELL_X51_Y9_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~1 ; LABCELL_X58_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~10 ; LABCELL_X53_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~11 ; LABCELL_X53_Y11_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~12 ; LABCELL_X58_Y9_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~13 ; LABCELL_X53_Y11_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~14 ; LABCELL_X53_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~15 ; LABCELL_X53_Y11_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~16 ; LABCELL_X58_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~17 ; LABCELL_X56_Y9_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~18 ; MLABCELL_X50_Y8_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~19 ; LABCELL_X54_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~2 ; LABCELL_X51_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~20 ; LABCELL_X58_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~21 ; MLABCELL_X50_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~22 ; MLABCELL_X50_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~23 ; LABCELL_X54_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~24 ; LABCELL_X53_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~25 ; LABCELL_X51_Y11_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~26 ; MLABCELL_X50_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~27 ; MLABCELL_X50_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~28 ; LABCELL_X51_Y9_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~29 ; LABCELL_X51_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~3 ; LABCELL_X58_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~30 ; LABCELL_X51_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~31 ; LABCELL_X51_Y9_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~32 ; LABCELL_X51_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~33 ; LABCELL_X58_Y9_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~34 ; MLABCELL_X50_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~35 ; LABCELL_X51_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~36 ; LABCELL_X58_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~37 ; LABCELL_X58_Y9_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~38 ; MLABCELL_X50_Y8_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~39 ; LABCELL_X56_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~4 ; LABCELL_X56_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~40 ; LABCELL_X58_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~41 ; LABCELL_X58_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~42 ; LABCELL_X56_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~43 ; LABCELL_X58_Y9_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~44 ; LABCELL_X58_Y8_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~45 ; LABCELL_X58_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~46 ; MLABCELL_X50_Y8_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~47 ; LABCELL_X56_Y9_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~48 ; LABCELL_X53_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~49 ; LABCELL_X53_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~5 ; LABCELL_X58_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~50 ; LABCELL_X58_Y8_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~51 ; LABCELL_X53_Y10_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~52 ; LABCELL_X54_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~53 ; LABCELL_X53_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~54 ; LABCELL_X56_Y9_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~55 ; LABCELL_X56_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~56 ; LABCELL_X51_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~57 ; LABCELL_X53_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~58 ; MLABCELL_X50_Y10_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~59 ; MLABCELL_X50_Y10_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~6 ; MLABCELL_X50_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~60 ; LABCELL_X54_Y9_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~61 ; LABCELL_X54_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~62 ; LABCELL_X58_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~63 ; LABCELL_X53_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~7 ; LABCELL_X58_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~8 ; LABCELL_X58_Y9_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~9 ; LABCELL_X51_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~0 ; MLABCELL_X42_Y5_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~1 ; MLABCELL_X42_Y6_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~10 ; MLABCELL_X42_Y8_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~11 ; LABCELL_X40_Y8_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~12 ; MLABCELL_X42_Y6_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~13 ; MLABCELL_X42_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~14 ; MLABCELL_X42_Y9_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~15 ; MLABCELL_X42_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~16 ; LABCELL_X41_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~17 ; LABCELL_X41_Y6_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~18 ; MLABCELL_X42_Y5_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~19 ; LABCELL_X41_Y6_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~2 ; MLABCELL_X42_Y5_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~20 ; MLABCELL_X42_Y5_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~21 ; LABCELL_X40_Y5_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~22 ; LABCELL_X41_Y5_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~23 ; LABCELL_X40_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~24 ; LABCELL_X40_Y5_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~25 ; MLABCELL_X42_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~26 ; LABCELL_X40_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~27 ; MLABCELL_X42_Y8_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~28 ; LABCELL_X41_Y7_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~29 ; LABCELL_X41_Y7_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~3 ; LABCELL_X40_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~30 ; MLABCELL_X42_Y5_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~31 ; LABCELL_X41_Y7_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~32 ; MLABCELL_X42_Y6_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~33 ; LABCELL_X40_Y8_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~34 ; MLABCELL_X42_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~35 ; MLABCELL_X42_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~36 ; MLABCELL_X42_Y6_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~37 ; MLABCELL_X42_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~38 ; MLABCELL_X42_Y6_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~39 ; LABCELL_X41_Y9_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~4 ; LABCELL_X41_Y5_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~40 ; LABCELL_X40_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~41 ; MLABCELL_X42_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~42 ; MLABCELL_X42_Y5_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~43 ; LABCELL_X41_Y7_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~44 ; MLABCELL_X42_Y6_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~45 ; MLABCELL_X42_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~46 ; MLABCELL_X42_Y5_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~47 ; MLABCELL_X42_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~48 ; LABCELL_X41_Y6_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~49 ; LABCELL_X41_Y6_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~5 ; LABCELL_X41_Y6_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~50 ; LABCELL_X41_Y6_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~51 ; LABCELL_X41_Y6_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~52 ; MLABCELL_X42_Y6_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~53 ; MLABCELL_X42_Y6_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~54 ; LABCELL_X41_Y6_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~55 ; LABCELL_X40_Y5_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~56 ; MLABCELL_X42_Y6_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~57 ; LABCELL_X40_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~58 ; LABCELL_X41_Y5_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~59 ; LABCELL_X40_Y8_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~6 ; LABCELL_X40_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~60 ; MLABCELL_X42_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~61 ; MLABCELL_X42_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~62 ; LABCELL_X40_Y5_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~63 ; LABCELL_X41_Y7_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~7 ; LABCELL_X40_Y8_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~8 ; MLABCELL_X42_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~9 ; MLABCELL_X42_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|next_state_data_read.11~0 ; LABCELL_X49_Y5_N48 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.10 ; FF_X41_Y9_N50 ; 15 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; FF_X50_Y3_N32 ; 104 ; Async. clear ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|rx_resetn ; FF_X49_Y3_N44 ; 75 ; Async. clear ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; LABCELL_X54_Y5_N51 ; 60 ; Clock ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|WideOr8~0 ; LABCELL_X53_Y6_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|negedge_clk ; LABCELL_X53_Y6_N0 ; 17 ; Clock ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1 ; LABCELL_X56_Y6_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1 ; LABCELL_X54_Y6_N27 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0 ; LABCELL_X54_Y6_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; FF_X53_Y6_N44 ; 26 ; Clock enable ; no ; -- ; -- ; -- ;; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; LABCELL_X48_Y5_N12 ; 1260 ; Async. clear ; no ; -- ; -- ; -- ;; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X22_Y29_N56 ; 74 ; Async. clear ; no ; -- ; -- ; -- ;; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X61_Y6_N44 ; 2974 ; Async. clear ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_auto_start:auto_start|always0~0 ; LABCELL_X17_Y18_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx|always0~0 ; LABCELL_X17_Y14_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_auto_start:link_disable|always0~0 ; LABCELL_X17_Y19_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_auto_start:link_start|always0~0 ; MLABCELL_X14_Y15_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable|always0~0 ; MLABCELL_X14_Y22_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx|always0~0 ; LABCELL_X21_Y27_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel|always0~0 ; LABCELL_X21_Y25_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK11 ; -- ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|always0~0 ; LABCELL_X33_Y16_N48 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y18_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y18_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y25_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y25_N36 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X42_Y11_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y12_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|always0~0 ; LABCELL_X43_Y11_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X42_Y12_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X45_Y11_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X42_Y13_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X40_Y10_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y10_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y14_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X15_Y14_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y12_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y12_N39 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y9_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y9_N0 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y10_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y10_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X18_Y10_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y10_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X43_Y15_N9 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|always0~0 ; LABCELL_X40_Y15_N6 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|always0~0 ; LABCELL_X35_Y15_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|always0~0 ; LABCELL_X33_Y16_N51 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y19_N51 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y19_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X11_Y15_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|always0~0 ; LABCELL_X11_Y15_N21 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X31_Y11_N33 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X32_Y11_N51 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X45_Y11_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y9_N27 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y27_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|always0~0 ; LABCELL_X27_Y27_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y23_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y22_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X25_Y8_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y8_N42 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X28_Y19_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y19_N30 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y27_N21 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y27_N24 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X15_Y20_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y18_N48 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y24_N27 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y25_N6 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X37_Y13_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X37_Y13_N36 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X41_Y12_N57 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X41_Y12_N42 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X37_Y14_N45 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X38_Y14_N42 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X31_Y11_N3 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X35_Y10_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y16_N15 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y14_N48 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X15_Y13_N36 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X14_Y13_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y11_N57 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y11_N57 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y9_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y9_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y11_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y11_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X38_Y15_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X38_Y15_N54 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X30_Y16_N18 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X32_Y16_N18 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y18_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y19_N0 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y16_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X11_Y16_N18 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X31_Y9_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y9_N9 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X33_Y12_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X35_Y9_N36 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y26_N24 ; 37 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y26_N36 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X18_Y23_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y23_N6 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y12_N33 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y12_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y20_N18 ; 38 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y20_N30 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y28_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y27_N18 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y18_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y25_N21 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X37_Y12_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X43_Y12_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X42_Y13_N3 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X40_Y10_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y14_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y12_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y9_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y10_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y10_N24 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X43_Y15_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X35_Y16_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X25_Y19_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X11_Y15_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X32_Y11_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X38_Y9_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y27_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y22_N21 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y8_N24 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y19_N45 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y27_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|always1~0 ; LABCELL_X21_Y20_N27 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|internal_valid~0 ; LABCELL_X23_Y16_N36 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|always1~0 ; MLABCELL_X25_Y24_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|internal_valid~0 ; LABCELL_X22_Y24_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 ; MLABCELL_X25_Y24_N33 ; 26 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|update_grant~0 ; LABCELL_X33_Y12_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|update_grant~0 ; LABCELL_X31_Y9_N9 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|update_grant~0 ; MLABCELL_X37_Y14_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|update_grant~0 ; MLABCELL_X19_Y16_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|update_grant~0 ; LABCELL_X22_Y9_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|update_grant~0 ; LABCELL_X15_Y13_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|update_grant~0 ; LABCELL_X21_Y16_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|update_grant~0 ; LABCELL_X15_Y20_N51 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|update_grant~0 ; MLABCELL_X19_Y18_N54 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|update_grant~0 ; LABCELL_X22_Y20_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|update_grant~0 ; LABCELL_X23_Y28_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|update_grant~0 ; MLABCELL_X19_Y11_N39 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|update_grant~0 ; LABCELL_X22_Y11_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|update_grant~0 ; LABCELL_X23_Y26_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|update_grant~0 ; LABCELL_X18_Y23_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|update_grant~0 ; LABCELL_X27_Y12_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|update_grant~0 ; LABCELL_X31_Y11_N18 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|update_grant~0 ; LABCELL_X21_Y24_N54 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|update_grant~0 ; LABCELL_X38_Y13_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|update_grant~0 ; LABCELL_X41_Y12_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|update_grant~0 ; LABCELL_X38_Y13_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|update_grant~0 ; LABCELL_X30_Y16_N54 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Clock ; yes ; Global Clock ; GCLK8 ; -- ;; ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data|always0~0 ; LABCELL_X30_Y25_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx|always0~0 ; LABCELL_X30_Y19_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+; FPGA_CLK1_50 ; PIN_Y13 ; 3073 ; Global Clock ; GCLK4 ; -- ;; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Global Clock ; GCLK11 ; -- ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fboutclk_wire[0] ; FRACTIONALPLL_X68_Y1_N0 ; 1 ; Global Clock ; -- ; -- ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Global Clock ; GCLK8 ; -- ;+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Non-Global High Fan-Out Signals ;+------------------------------------------------------------------------------------------------------------------------------------------+---------+; Name ; Fan-Out ;+------------------------------------------------------------------------------------------------------------------------------------------+---------+; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 2974 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1319 ;; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; 1260 ;+------------------------------------------------------------------------------------------------------------------------------------------+---------++------------------------------------------------------------------------+; Routing Usage Summary ;+---------------------------------------------+--------------------------+; Routing Resource Type ; Usage ;+---------------------------------------------+--------------------------+; Block interconnects ; 10,851 / 130,276 ( 8 % ) ;; C12 interconnects ; 122 / 6,848 ( 2 % ) ;; C2 interconnects ; 2,619 / 51,436 ( 5 % ) ;; C4 interconnects ; 1,582 / 25,120 ( 6 % ) ;; DQS bus muxes ; 0 / 19 ( 0 % ) ;; DQS-18 I/O buses ; 0 / 19 ( 0 % ) ;; DQS-9 I/O buses ; 0 / 19 ( 0 % ) ;; Direct links ; 1,438 / 130,276 ( 1 % ) ;; Global clocks ; 3 / 16 ( 19 % ) ;; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 1 / 6 ( 17 % ) ;; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;; HPS_INTERFACE_HPS2FPGA_INPUTs ; 40 / 165 ( 24 % ) ;; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 101 / 282 ( 36 % ) ;; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;; Local interconnects ; 3,340 / 31,760 ( 11 % ) ;; Quadrant clocks ; 0 / 72 ( 0 % ) ;; R14 interconnects ; 250 / 6,046 ( 4 % ) ;; R14/C12 interconnect drivers ; 333 / 8,584 ( 4 % ) ;; R3 interconnects ; 4,393 / 56,712 ( 8 % ) ;; R6 interconnects ; 6,014 / 131,000 ( 5 % ) ;; Spine clocks ; 6 / 150 ( 4 % ) ;; Wire stub REs ; 0 / 6,650 ( 0 % ) ;+---------------------------------------------+--------------------------++------------------------------------------+; I/O Rules Summary ;+----------------------------------+-------+; I/O Rules Statistic ; Total ;+----------------------------------+-------+; Total I/O Rules ; 28 ;; Number of I/O Rules Passed ; 8 ;; Number of I/O Rules Failed ; 0 ;; Number of I/O Rules Unchecked ; 0 ;; Number of I/O Rules Inapplicable ; 20 ;+----------------------------------+-------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; I/O Rules Details ;+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; 0 such failures found. ; I/O ; ;; ---- ; ---- ; Disclaimer ; LVDS rules are checked but not reported. ; None ; ---- ; Differential Signaling ; ;+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; I/O Rules Matrix ;+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000022 ; IO_000021 ; IO_000046 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000047 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+; Total Pass ; 5 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 19 ; 16 ;; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; Total Inapplicable ; 14 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 0 ; 3 ;; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; LED[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; LED[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; dout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; sout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; LED[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; LED[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; LED[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; LED[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; LED[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;; LED[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; FPGA_CLK1_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;; din_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; sin_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; dout_a(n) ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; sout_a(n) ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; din_a(n) ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;; sin_a(n) ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------++------------------------------------------------------------------------------------------------+; Fitter Device Options ;+------------------------------------------------------------------+-----------------------------+; Option ; Setting ;+------------------------------------------------------------------+-----------------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Passive Serial ;; Enable Error Detection CRC_ERROR pin ; Off ;; Enable CvP_CONFDONE pin ; Off ;; Enable open drain on CRC_ERROR pin ; On ;; Enable open drain on CvP_CONFDONE pin ; On ;; Enable open drain on INIT_DONE pin ; On ;; Enable open drain on Partial Reconfiguration pins ; Off ;; Enable open drain on nCEO pin ; On ;; Enable Partial Reconfiguration pins ; Off ;; Enable input tri-state on active configuration pins in user mode ; Off ;; Enable internal scrubbing ; Off ;; Active Serial clock source ; 100 MHz Internal Oscillator ;; Device initialization clock source ; Internal Oscillator ;; Configuration via Protocol ; Off ;; Configuration Voltage Level ; Auto ;; Force Configuration Voltage Level ; Off ;; Enable nCEO output ; Off ;; Data[15..8] ; Unreserved ;; Data[7..5] ; Unreserved ;; Base pin-out file on sameframe device ; Off ;+------------------------------------------------------------------+-----------------------------++------------------------------------+; Operating Settings and Conditions ;+---------------------------+--------+; Setting ; Value ;+---------------------------+--------+; Nominal Core Voltage ; 1.10 V ;+---------------------------+--------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Estimated Delay Added for Hold Timing Summary ;+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 603.1 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 152.8 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 85.5 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 83.9 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; 65.3 ;; din_a ; din_a ; 47.9 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 39.2 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 31.9 ;; I/O ; din_a ; 25.0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 23.3 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i,clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 23.3 ;+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Estimated Delay Added for Hold Timing Details ;+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+; Source Register ; Destination Register ; Delay Added in ns ;+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+; din_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 4.535 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; detector_tokens:m_x|bit_capture_data:capture_d|bit_d_0 ; 4.290 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[1] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[1] ; 2.916 ;; sin_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; 2.828 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[4] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[4] ; 2.799 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[7] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[7] ; 2.654 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[3] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[3] ; 2.645 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[0] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[0] ; 2.639 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[1] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[1] ; 2.638 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[2] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[2] ; 2.608 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[5] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[5] ; 2.608 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[3] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[3] ; 2.546 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[5] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[5] ; 2.540 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_sout_e ; detector_tokens:m_x|info[4] ; 2.341 ;; detector_tokens:m_x|info[5] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[5] ; 2.334 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.run ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[4] ; 2.323 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.ready ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[1] ; 2.323 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.error_wait ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[0] ; 2.310 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[4] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[4] ; 2.289 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[2] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[2] ; 2.289 ;; detector_tokens:m_x|info[2] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[2] ; 2.265 ;; detector_tokens:m_x|info[4] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[4] ; 2.253 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[8] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[8] ; 2.240 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[0] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[0] ; 2.076 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[0] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[0] ; 2.018 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.started ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[2] ; 2.009 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|open_slot_fct ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.001 ; 2.008 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[6] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[6] ; 2.007 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[3] ; 2.001 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[1] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[1] ; 1.991 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[2] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[2] ; 1.983 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[3] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[3] ; 1.970 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|f_empty ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[0] ; 1.934 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|send_null_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.862 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[4] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[4] ; 1.857 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[5] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[5] ; 1.839 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.702 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.687 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ready_tx_timecode ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[0] ; 1.682 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|f_full ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[0] ; 1.670 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.599 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|get_rx_got_fct_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; 1.540 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c_0 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.518 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_timec ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|data_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|eop_eep_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|fct_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|null_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_time_code_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_start ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|f_empty ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[0] ; 1.346 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|f_full ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[0] ; 1.343 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[0] ; 1.343 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[0] ; 1.318 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|data_out[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[0] ; 1.260 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|overflow_credit_error ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|get_rx_credit_error_b ; 1.259 ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|write_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|process_data ; 1.258 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ready_tx_data ; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read~5 ; 1.255 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.249 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.238 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[10] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.230 ;; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[5] ; detector_tokens:m_x|counter_neg:cnt_neg|is_control ; 1.228 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.215 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.169 ;; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[3] ; detector_tokens:m_x|counter_neg:cnt_neg|is_control ; 1.153 ;+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+Note: This table only shows the top 100 path(s) that have the largest delay added for hold.+-----------------+; Fitter Messages ;+-----------------+Info (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation timeInfo (16304): Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)Info (16304): Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal)Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detectedInfo (119006): Selected device 5CSEMA4U23C6 for design "spw_fifo_ulight"Info (21077): Low junction temperature is 0 degrees CInfo (21077): High junction temperature is 85 degrees CInfo (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation timeWarning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for detailsInfo (184025): 4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins.Info (184026): differential I/O pin "dout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "dout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 9Info (184026): differential I/O pin "sout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 10Info (184026): differential I/O pin "din_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "din_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 5Info (184026): differential I/O pin "sin_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sin_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 6Info (184020): Starting Fitter periphery placement operationsWarning (177007): PLL(s) placed in location FRACTIONALPLL_X68_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocksInfo (177008): PLL ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpllInfo (11178): Promoted 2 clocks (2 global)Info (11162): ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G11Info (11162): ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G8Info (11191): Automatically promoted 1 clock (1 global)Info (11162): FPGA_CLK1_50~inputCLKENA0 with 3068 fanout uses global clock CLKCTRL_G4Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00Info (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataa to: comboutInfo (332098): Cell: m_x|comb from: datab to: comboutInfo (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclkInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkoutInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclkInfo (332152): The following assignments are ignored by the derive_clock_uncertainty commandInfo (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirementsInfo (332111): Found 7 clocksInfo (332111): Period Clock NameInfo (332111): ======== ============Info (332111): 10.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332111): 2.500 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332111): 4.000 din_aInfo (332111): 20.000 FPGA_CLK1_50Info (332111): 4.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]Info (176233): Starting register packingInfo (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.Info (176235): Finished register packingExtra Info (176218): Packed 5 registers into blocks of type I/O output bufferExtra Info (176220): Created 5 register duplicatesInfo (223000): Starting Vectorless Power Activity EstimationInfo (223001): Completed Vectorless Power Activity EstimationInfo (128000): Starting physical synthesis optimizations for speedInfo (128002): Starting physical synthesis algorithm combinational resynthesis using boolean divisionInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 662 psInfo (128002): Starting physical synthesis algorithm combinational resynthesis using boolean divisionInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 psInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:09Info (176233): Starting register packingInfo (176235): Finished register packingExtra Info (176219): No registers were packed into other blocksInfo (11798): Fitter preparation operations ending: elapsed time is 00:00:30Warning (170136): Design uses Placement Effort Multiplier = 4.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt.Info (170189): Fitter placement preparation operations beginningInfo (223000): Starting Vectorless Power Activity EstimationInfo (223001): Completed Vectorless Power Activity EstimationInfo (14951): The Fitter is using Advanced Physical Optimization.Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:35Info (223000): Starting Vectorless Power Activity EstimationInfo (223001): Completed Vectorless Power Activity EstimationInfo (170191): Fitter placement operations beginningInfo (170137): Fitter placement was successfulInfo (170192): Fitter placement operations ending: elapsed time is 00:00:58Info (170193): Fitter routing operations beginningInfo (223000): Starting Vectorless Power Activity EstimationInfo (223001): Completed Vectorless Power Activity EstimationInfo (170195): Router estimated average interconnect usage is 4% of the available device resourcesInfo (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.Info (170194): Fitter routing operations ending: elapsed time is 00:01:16Info (11888): Total time spent on timing analysis during the Fitter is 27.50 seconds.Info (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (11801): Fitter post-fit operations ending: elapsed time is 00:00:38Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.Info (144001): Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsgInfo: Quartus Prime Fitter was successful. 0 errors, 6 warningsInfo: Peak virtual memory: 2473 megabytesInfo: Processing ended: Mon Feb 5 00:57:20 2018Info: Elapsed time: 00:05:09Info: Total CPU time (on all processors): 00:08:50+----------------------------+; Fitter Suppressed Messages ;+----------------------------+The suppressed messages can be found in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg.