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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.flow.rpt] - Rev 35
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Flow report for spw_fifo_ulightFri Sep 15 08:19:20 2017Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Flow Summary3. Flow Settings4. Flow Non-Default Global Settings5. Flow Elapsed Time6. Flow OS Summary7. Flow Log8. Flow Messages9. Flow Suppressed Messages----------------; Legal Notice ;----------------Copyright (C) 2017 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel MegaCore Function License Agreement, or otherapplicable license agreement, including, without limitation,that your use is for the sole purpose of programming logicdevices manufactured by Intel and sold by Intel or itsauthorized distributors. Please refer to the applicableagreement for further details.+-------------------------------------------------------------------------------+; Flow Summary ;+---------------------------------+---------------------------------------------+; Flow Status ; Successful - Fri Sep 15 08:19:20 2017 ;; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;; Revision Name ; spw_fifo_ulight ;; Top-level Entity Name ; SPW_ULIGHT_FIFO ;; Family ; Cyclone V ;; Device ; 5CSEMA4U23C6 ;; Timing Models ; Final ;; Logic utilization (in ALMs) ; 3,209 / 15,880 ( 20 % ) ;; Total registers ; 4692 ;; Total pins ; 19 / 314 ( 6 % ) ;; Total virtual pins ; 0 ;; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;; Total DSP Blocks ; 0 / 84 ( 0 % ) ;; Total HSSI RX PCSs ; 0 ;; Total HSSI PMA RX Deserializers ; 0 ;; Total HSSI TX PCSs ; 0 ;; Total HSSI PMA TX Serializers ; 0 ;; Total PLLs ; 1 / 5 ( 20 % ) ;; Total DLLs ; 0 / 4 ( 0 % ) ;+---------------------------------+---------------------------------------------++-----------------------------------------+; Flow Settings ;+-------------------+---------------------+; Option ; Setting ;+-------------------+---------------------+; Start date & time ; 09/15/2017 08:07:49 ;; Main task ; Compilation ;; Revision Name ; spw_fifo_ulight ;+-------------------+---------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Flow Non-Default Global Settings ;+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+; ALLOW_REGISTER_DUPLICATION ; Off ; On ; -- ; -- ;; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ;; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ;; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ;; AUTO_DELAY_CHAINS ; Off ; On ; -- ; -- ;; COMPILER_SIGNATURE_ID ; 31032335263289.150547366508423 ; -- ; -- ; -- ;; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; HPS_PARTITION ; On ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;; INFER_RAMS_FROM_RAW_LOGIC ; Off ; On ; -- ; -- ;; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/../ulight_fifo.cmp ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/ulight_fifo_hps_0_hps.svd ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/../../ulight_fifo.qsys ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; -- ; -- ;; MISC_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; -- ; -- ;; OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ;; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Off ; Normal ; -- ; -- ;; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ;; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;; PLACEMENT_EFFORT_MULTIPLIER ; 90.0 ; 1.0 ; -- ; -- ;; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ;; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ;; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;; SEED ; 893763639 ; 1 ; -- ; -- ;; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ;; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ;; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1502975928 ; -- ; ulight_fifo ; -- ;; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ;; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;; TOP_LEVEL_ENTITY ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ; -- ; -- ;+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------++-------------------------------------------------------------------------------------------------------------------------------+; Flow Elapsed Time ;+---------------------------+--------------+-------------------------+---------------------+------------------------------------+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;+---------------------------+--------------+-------------------------+---------------------+------------------------------------+; Analysis & Synthesis ; 00:01:16 ; 1.3 ; 1339 MB ; 00:01:53 ;; Fitter ; 00:04:42 ; 1.0 ; 2064 MB ; 00:08:17 ;; Assembler ; 00:00:18 ; 1.0 ; 1040 MB ; 00:00:12 ;; TimeQuest Timing Analyzer ; 00:00:54 ; 1.5 ; 1351 MB ; 00:01:15 ;; EDA Netlist Writer ; 00:00:08 ; 1.0 ; 1314 MB ; 00:00:08 ;; Total ; 00:07:18 ; -- ; -- ; 00:11:45 ;+---------------------------+--------------+-------------------------+---------------------+------------------------------------++-----------------------------------------------------------------------------------------+; Flow OS Summary ;+---------------------------+------------------+------------+------------+----------------+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;+---------------------------+------------------+------------+------------+----------------+; Analysis & Synthesis ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;; Fitter ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;; Assembler ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;; TimeQuest Timing Analyzer ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;; EDA Netlist Writer ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;+---------------------------+------------------+------------+------------+----------------+------------; Flow Log ;------------quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulightquartus_fit --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulightquartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulightquartus_sta spw_fifo_ulight -c spw_fifo_ulightquartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
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