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TimeQuest Timing Analyzer report for spw_fifo_ulightFri Sep 15 08:19:10 2017Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. TimeQuest Timing Analyzer Summary3. Parallel Compilation4. SDC File List5. Clocks6. Slow 1100mV 85C Model Fmax Summary7. Timing Closure Recommendations8. Slow 1100mV 85C Model Setup Summary9. Slow 1100mV 85C Model Hold Summary10. Slow 1100mV 85C Model Recovery Summary11. Slow 1100mV 85C Model Removal Summary12. Slow 1100mV 85C Model Minimum Pulse Width Summary13. Slow 1100mV 85C Model Metastability Summary14. Slow 1100mV 0C Model Fmax Summary15. Slow 1100mV 0C Model Setup Summary16. Slow 1100mV 0C Model Hold Summary17. Slow 1100mV 0C Model Recovery Summary18. Slow 1100mV 0C Model Removal Summary19. Slow 1100mV 0C Model Minimum Pulse Width Summary20. Slow 1100mV 0C Model Metastability Summary21. Fast 1100mV 85C Model Setup Summary22. Fast 1100mV 85C Model Hold Summary23. Fast 1100mV 85C Model Recovery Summary24. Fast 1100mV 85C Model Removal Summary25. Fast 1100mV 85C Model Minimum Pulse Width Summary26. Fast 1100mV 85C Model Metastability Summary27. Fast 1100mV 0C Model Setup Summary28. Fast 1100mV 0C Model Hold Summary29. Fast 1100mV 0C Model Recovery Summary30. Fast 1100mV 0C Model Removal Summary31. Fast 1100mV 0C Model Minimum Pulse Width Summary32. Fast 1100mV 0C Model Metastability Summary33. Multicorner Timing Analysis Summary34. Board Trace Model Assignments35. Input Transition Times36. Signal Integrity Metrics (Slow 1100mv 0c Model)37. Signal Integrity Metrics (Slow 1100mv 85c Model)38. Signal Integrity Metrics (Fast 1100mv 0c Model)39. Signal Integrity Metrics (Fast 1100mv 85c Model)40. Setup Transfers41. Hold Transfers42. Recovery Transfers43. Removal Transfers44. Report TCCS45. Report RSKM46. Unconstrained Paths Summary47. Clock Status Summary48. Unconstrained Input Ports49. Unconstrained Output Ports50. Unconstrained Input Ports51. Unconstrained Output Ports52. TimeQuest Timing Analyzer Messages----------------; Legal Notice ;----------------Copyright (C) 2017 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel MegaCore Function License Agreement, or otherapplicable license agreement, including, without limitation,that your use is for the sole purpose of programming logicdevices manufactured by Intel and sold by Intel or itsauthorized distributors. Please refer to the applicableagreement for further details.+-----------------------------------------------------------------------------+; TimeQuest Timing Analyzer Summary ;+-----------------------+-----------------------------------------------------+; Quartus Prime Version ; Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;; Timing Analyzer ; TimeQuest ;; Revision Name ; spw_fifo_ulight ;; Device Family ; Cyclone V ;; Device Name ; 5CSEMA4U23C6 ;; Timing Models ; Final ;; Delay Model ; Combined ;; Rise/Fall Delays ; Enabled ;+-----------------------+-----------------------------------------------------++------------------------------------------+; Parallel Compilation ;+----------------------------+-------------+; Processors ; Number ;+----------------------------+-------------+; Number detected on machine ; 4 ;; Maximum allowed ; 2 ;; ; ;; Average used ; 1.48 ;; Maximum used ; 2 ;; ; ;; Usage by Processor ; % Time Used ;; Processor 1 ; 100.0% ;; Processor 2 ; 47.8% ;+----------------------------+-------------++--------------------------------------------------------------------------------------------------+; SDC File List ;+--------------------------------------------------------------+--------+--------------------------+; SDC File Path ; Status ; Read at ;+--------------------------------------------------------------+--------+--------------------------+; sdc/spw_fifo_ulight.out.sdc ; OK ; Fri Sep 15 08:18:31 2017 ;; ulight_fifo/synthesis/submodules/altera_reset_controller.sdc ; OK ; Fri Sep 15 08:18:31 2017 ;+--------------------------------------------------------------+--------+--------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clocks ;+----------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------+; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;+----------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; Base ; 4.000 ; 250.0 MHz ; 0.000 ; 2.000 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i } ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; Base ; 3.000 ; 333.33 MHz ; 0.000 ; 1.500 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i } ;; din_a ; Base ; 3.000 ; 333.33 MHz ; 0.000 ; 1.500 ; ; ; ; ; ; ; ; ; ; ; { din_a } ;; FPGA_CLK1_50 ; Base ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; ; ; ; ; ; ; ; ; ; ; { FPGA_CLK1_50 } ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; Base ; 3.000 ; 333.33 MHz ; 0.000 ; 1.500 ; ; ; ; ; ; ; ; ; ; ; { spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e } ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 1 ; 1 ; ; ; ; ; false ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0] ; { u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk } ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 2 ; 8 ; ; ; ; ; false ; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin ; { u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] } ;+----------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------++----------------------------------------------------+; Slow 1100mV 85C Model Fmax Summary ;+------------+-----------------+--------------+------+; Fmax ; Restricted Fmax ; Clock Name ; Note ;+------------+-----------------+--------------+------+; 113.58 MHz ; 113.58 MHz ; FPGA_CLK1_50 ; ;+------------+-----------------+--------------+------+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.----------------------------------; Timing Closure Recommendations ;----------------------------------HTML report is unavailable in plain text report export.+--------------------------------------+; Slow 1100mV 85C Model Setup Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 1.196 ; 0.000 ;+--------------+-------+---------------++--------------------------------------+; Slow 1100mV 85C Model Hold Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 0.271 ; 0.000 ;+--------------+-------+---------------++----------------------------------------+; Slow 1100mV 85C Model Recovery Summary ;+--------------+-------+-----------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+-----------------+; FPGA_CLK1_50 ; 4.785 ; 0.000 ;+--------------+-------+-----------------++---------------------------------------+; Slow 1100mV 85C Model Removal Summary ;+--------------+-------+----------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+----------------+; FPGA_CLK1_50 ; 0.979 ; 0.000 ;+--------------+-------+----------------++----------------------------------------------------------------------------------------------------+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;+----------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+----------------------------------------------------------------------------+-------+---------------+; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.538 ; 0.000 ;; din_a ; 0.597 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.657 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; 0.679 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.084 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ;; FPGA_CLK1_50 ; 4.202 ; 0.000 ;+----------------------------------------------------------------------------+-------+---------------+-----------------------------------------------; Slow 1100mV 85C Model Metastability Summary ;-----------------------------------------------The design MTBF is not calculated because there are no specified synchronizers in the design.Number of Synchronizer Chains Found: 59Shortest Synchronizer Chain: 2 RegistersFraction of Chains for which MTBFs Could Not be Calculated: 1.000Worst Case Available Settling Time: 12.106 ns+----------------------------------------------------+; Slow 1100mV 0C Model Fmax Summary ;+------------+-----------------+--------------+------+; Fmax ; Restricted Fmax ; Clock Name ; Note ;+------------+-----------------+--------------+------+; 113.69 MHz ; 113.69 MHz ; FPGA_CLK1_50 ; ;+------------+-----------------+--------------+------+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.+--------------------------------------+; Slow 1100mV 0C Model Setup Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 1.204 ; 0.000 ;+--------------+-------+---------------++--------------------------------------+; Slow 1100mV 0C Model Hold Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 0.253 ; 0.000 ;+--------------+-------+---------------++---------------------------------------+; Slow 1100mV 0C Model Recovery Summary ;+--------------+-------+----------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+----------------+; FPGA_CLK1_50 ; 4.852 ; 0.000 ;+--------------+-------+----------------++--------------------------------------+; Slow 1100mV 0C Model Removal Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 0.920 ; 0.000 ;+--------------+-------+---------------++----------------------------------------------------------------------------------------------------+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;+----------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+----------------------------------------------------------------------------+-------+---------------+; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.465 ; 0.000 ;; din_a ; 0.633 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.663 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; 0.716 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.117 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ;; FPGA_CLK1_50 ; 4.284 ; 0.000 ;+----------------------------------------------------------------------------+-------+---------------+----------------------------------------------; Slow 1100mV 0C Model Metastability Summary ;----------------------------------------------The design MTBF is not calculated because there are no specified synchronizers in the design.Number of Synchronizer Chains Found: 59Shortest Synchronizer Chain: 2 RegistersFraction of Chains for which MTBFs Could Not be Calculated: 1.000Worst Case Available Settling Time: 12.241 ns+--------------------------------------+; Fast 1100mV 85C Model Setup Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 4.542 ; 0.000 ;+--------------+-------+---------------++--------------------------------------+; Fast 1100mV 85C Model Hold Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 0.162 ; 0.000 ;+--------------+-------+---------------++----------------------------------------+; Fast 1100mV 85C Model Recovery Summary ;+--------------+-------+-----------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+-----------------+; FPGA_CLK1_50 ; 6.857 ; 0.000 ;+--------------+-------+-----------------++---------------------------------------+; Fast 1100mV 85C Model Removal Summary ;+--------------+-------+----------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+----------------+; FPGA_CLK1_50 ; 0.574 ; 0.000 ;+--------------+-------+----------------++----------------------------------------------------------------------------------------------------+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;+----------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+----------------------------------------------------------------------------+-------+---------------+; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.799 ; 0.000 ;; din_a ; 0.812 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; 0.897 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.920 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.333 ; 0.000 ;; FPGA_CLK1_50 ; 4.076 ; 0.000 ;+----------------------------------------------------------------------------+-------+---------------+-----------------------------------------------; Fast 1100mV 85C Model Metastability Summary ;-----------------------------------------------The design MTBF is not calculated because there are no specified synchronizers in the design.Number of Synchronizer Chains Found: 59Shortest Synchronizer Chain: 2 RegistersFraction of Chains for which MTBFs Could Not be Calculated: 1.000Worst Case Available Settling Time: 15.202 ns+--------------------------------------+; Fast 1100mV 0C Model Setup Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 5.038 ; 0.000 ;+--------------+-------+---------------++--------------------------------------+; Fast 1100mV 0C Model Hold Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 0.146 ; 0.000 ;+--------------+-------+---------------++---------------------------------------+; Fast 1100mV 0C Model Recovery Summary ;+--------------+-------+----------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+----------------+; FPGA_CLK1_50 ; 7.031 ; 0.000 ;+--------------+-------+----------------++--------------------------------------+; Fast 1100mV 0C Model Removal Summary ;+--------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------+-------+---------------+; FPGA_CLK1_50 ; 0.524 ; 0.000 ;+--------------+-------+---------------++----------------------------------------------------------------------------------------------------+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;+----------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+----------------------------------------------------------------------------+-------+---------------+; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.793 ; 0.000 ;; din_a ; 0.828 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; 0.961 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.969 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.399 ; 0.000 ;; FPGA_CLK1_50 ; 4.039 ; 0.000 ;+----------------------------------------------------------------------------+-------+---------------+----------------------------------------------; Fast 1100mV 0C Model Metastability Summary ;----------------------------------------------The design MTBF is not calculated because there are no specified synchronizers in the design.Number of Synchronizer Chains Found: 59Shortest Synchronizer Chain: 2 RegistersFraction of Chains for which MTBFs Could Not be Calculated: 1.000Worst Case Available Settling Time: 15.621 ns+----------------------------------------------------------------------------------------------------------------------------------------+; Multicorner Timing Analysis Summary ;+-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;+-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+; Worst-case Slack ; 1.196 ; 0.146 ; 4.785 ; 0.524 ; 0.465 ;; FPGA_CLK1_50 ; 1.196 ; 0.146 ; 4.785 ; 0.524 ; 4.039 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; N/A ; N/A ; N/A ; N/A ; 1.084 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; N/A ; N/A ; N/A ; N/A ; 0.657 ;; din_a ; N/A ; N/A ; N/A ; N/A ; 0.597 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; N/A ; N/A ; N/A ; N/A ; 0.679 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; N/A ; N/A ; N/A ; N/A ; 0.465 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.250 ;; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;; FPGA_CLK1_50 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; N/A ; N/A ; N/A ; N/A ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; N/A ; N/A ; N/A ; N/A ; 0.000 ;; din_a ; N/A ; N/A ; N/A ; N/A ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; N/A ; N/A ; N/A ; N/A ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; N/A ; N/A ; N/A ; N/A ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ;+-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Board Trace Model Assignments ;+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+; dout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;; sout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;; LED[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; dout_a(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;; sout_a(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------++-----------------------------------------------------------------+; Input Transition Times ;+--------------+--------------+-----------------+-----------------+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;+--------------+--------------+-----------------+-----------------+; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FPGA_CLK1_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; din_a ; LVDS ; 2000 ps ; 2000 ps ;; sin_a ; LVDS ; 2000 ps ; 2000 ps ;; din_a(n) ; LVDS ; 2000 ps ; 2000 ps ;; sin_a(n) ; LVDS ; 2000 ps ; 2000 ps ;+--------------+--------------+-----------------+-----------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; dout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;; sout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; dout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;; sout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; dout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;; sout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; dout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;; sout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup Transfers ;+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; false path ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0 ; false path ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; false path ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; false path ; 0 ; 0 ;; din_a ; din_a ; false path ; false path ; false path ; false path ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;; din_a ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 198264 ; 0 ; 0 ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ;; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; false path ; false path ; false path ;; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; false path ; 0 ; 0 ; 0 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; false path ; 0 ; 0 ; 0 ;+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold Transfers ;+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; false path ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0 ; false path ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; false path ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; false path ; 0 ; 0 ;; din_a ; din_a ; false path ; false path ; false path ; false path ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;; din_a ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 198264 ; 0 ; 0 ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ;; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; false path ; false path ; false path ;; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; false path ; 0 ; 0 ; 0 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; false path ; 0 ; 0 ; 0 ;+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Recovery Transfers ;+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; din_a ; 100 ; 0 ; 69 ; 0 ;; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3102 ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ;+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Removal Transfers ;+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; din_a ; 100 ; 0 ; 69 ; 0 ;; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3102 ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ;+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.---------------; Report TCCS ;---------------No dedicated SERDES Transmitter circuitry present in device or used in design---------------; Report RSKM ;---------------No non-DPA dedicated SERDES Receiver circuitry present in device or used in design+------------------------------------------------+; Unconstrained Paths Summary ;+---------------------------------+-------+------+; Property ; Setup ; Hold ;+---------------------------------+-------+------+; Illegal Clocks ; 0 ; 0 ;; Unconstrained Clocks ; 0 ; 0 ;; Unconstrained Input Ports ; 2 ; 2 ;; Unconstrained Input Port Paths ; 36 ; 36 ;; Unconstrained Output Ports ; 10 ; 10 ;; Unconstrained Output Port Paths ; 10 ; 10 ;+---------------------------------+-------+------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Status Summary ;+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------+-------------+; Target ; Clock ; Type ; Status ;+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------+-------------+; FPGA_CLK1_50 ; FPGA_CLK1_50 ; Base ; Constrained ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; Base ; Constrained ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; Base ; Constrained ;; din_a ; din_a ; Base ; Constrained ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; Base ; Constrained ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; Generated ; Constrained ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; Generated ; Constrained ;+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------+-------------++---------------------------------------------------------------------------------------------------+; Unconstrained Input Ports ;+------------+--------------------------------------------------------------------------------------+; Input Port ; Comment ;+------------+--------------------------------------------------------------------------------------+; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;; sin_a ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;+------------+--------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------+; Unconstrained Output Ports ;+-------------+---------------------------------------------------------------------------------------+; Output Port ; Comment ;+-------------+---------------------------------------------------------------------------------------+; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; dout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; dout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; sout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; sout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;+-------------+---------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------+; Unconstrained Input Ports ;+------------+--------------------------------------------------------------------------------------+; Input Port ; Comment ;+------------+--------------------------------------------------------------------------------------+; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;; sin_a ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;+------------+--------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------+; Unconstrained Output Ports ;+-------------+---------------------------------------------------------------------------------------+; Output Port ; Comment ;+-------------+---------------------------------------------------------------------------------------+; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; dout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; dout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; sout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; sout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;+-------------+---------------------------------------------------------------------------------------++------------------------------------+; TimeQuest Timing Analyzer Messages ;+------------------------------------+Info: *******************************************************************Info: Running Quartus Prime TimeQuest Timing AnalyzerInfo: Version 17.0.1 Build 598 06/07/2017 SJ Lite EditionInfo: Processing started: Fri Sep 15 08:18:16 2017Info: Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulightInfo: qsta_default_script.tcl version: #1Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detectedInfo (21077): Low junction temperature is 0 degrees CInfo (21077): High junction temperature is 85 degrees CInfo (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataf to: comboutInfo (332098): Cell: m_x|always3~0 from: dataf to: comboutInfo (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclkInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkoutInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclkInfo (332152): The following assignments are ignored by the derive_clock_uncertainty commandInfo: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ONInfo: Analyzing Slow 1100mV 85C ModelInfo (332146): Worst-case setup slack is 1.196Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 1.196 0.000 FPGA_CLK1_50Info (332146): Worst-case hold slack is 0.271Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.271 0.000 FPGA_CLK1_50Info (332146): Worst-case recovery slack is 4.785Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 4.785 0.000 FPGA_CLK1_50Info (332146): Worst-case removal slack is 0.979Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.979 0.000 FPGA_CLK1_50Info (332146): Worst-case minimum pulse width slack is 0.538Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.538 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.597 0.000 din_aInfo (332119): 0.657 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.679 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_eInfo (332119): 1.084 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]Info (332119): 4.202 0.000 FPGA_CLK1_50Info (332114): Report Metastability: Found 59 synchronizer chains.Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.Info (332114): Number of Synchronizer Chains Found: 59Info (332114): Shortest Synchronizer Chain: 2 RegistersInfo (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000Info (332114): Worst Case Available Settling Time: 12.106 nsInfo (332114):Info: Analyzing Slow 1100mV 0C ModelInfo (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataf to: comboutInfo (332098): Cell: m_x|always3~0 from: dataf to: comboutInfo (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclkInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkoutInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclkInfo (332152): The following assignments are ignored by the derive_clock_uncertainty commandInfo (332146): Worst-case setup slack is 1.204Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 1.204 0.000 FPGA_CLK1_50Info (332146): Worst-case hold slack is 0.253Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.253 0.000 FPGA_CLK1_50Info (332146): Worst-case recovery slack is 4.852Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 4.852 0.000 FPGA_CLK1_50Info (332146): Worst-case removal slack is 0.920Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.920 0.000 FPGA_CLK1_50Info (332146): Worst-case minimum pulse width slack is 0.465Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.465 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.633 0.000 din_aInfo (332119): 0.663 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.716 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_eInfo (332119): 1.117 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]Info (332119): 4.284 0.000 FPGA_CLK1_50Info (332114): Report Metastability: Found 59 synchronizer chains.Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.Info (332114): Number of Synchronizer Chains Found: 59Info (332114): Shortest Synchronizer Chain: 2 RegistersInfo (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000Info (332114): Worst Case Available Settling Time: 12.241 nsInfo (332114):Info: Analyzing Fast 1100mV 85C ModelInfo (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataf to: comboutInfo (332098): Cell: m_x|always3~0 from: dataf to: comboutInfo (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclkInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkoutInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclkInfo (332152): The following assignments are ignored by the derive_clock_uncertainty commandInfo (332146): Worst-case setup slack is 4.542Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 4.542 0.000 FPGA_CLK1_50Info (332146): Worst-case hold slack is 0.162Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.162 0.000 FPGA_CLK1_50Info (332146): Worst-case recovery slack is 6.857Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 6.857 0.000 FPGA_CLK1_50Info (332146): Worst-case removal slack is 0.574Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.574 0.000 FPGA_CLK1_50Info (332146): Worst-case minimum pulse width slack is 0.799Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.799 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.812 0.000 din_aInfo (332119): 0.897 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_eInfo (332119): 0.920 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]Info (332119): 1.333 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 4.076 0.000 FPGA_CLK1_50Info (332114): Report Metastability: Found 59 synchronizer chains.Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.Info (332114): Number of Synchronizer Chains Found: 59Info (332114): Shortest Synchronizer Chain: 2 RegistersInfo (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000Info (332114): Worst Case Available Settling Time: 15.202 nsInfo (332114):Info: Analyzing Fast 1100mV 0C ModelInfo (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataf to: comboutInfo (332098): Cell: m_x|always3~0 from: dataf to: comboutInfo (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclkInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkoutInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclkInfo (332152): The following assignments are ignored by the derive_clock_uncertainty commandInfo (332146): Worst-case setup slack is 5.038Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 5.038 0.000 FPGA_CLK1_50Info (332146): Worst-case hold slack is 0.146Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.146 0.000 FPGA_CLK1_50Info (332146): Worst-case recovery slack is 7.031Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 7.031 0.000 FPGA_CLK1_50Info (332146): Worst-case removal slack is 0.524Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.524 0.000 FPGA_CLK1_50Info (332146): Worst-case minimum pulse width slack is 0.793Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.793 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.828 0.000 din_aInfo (332119): 0.961 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_eInfo (332119): 0.969 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]Info (332119): 1.399 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 4.039 0.000 FPGA_CLK1_50Info (332114): Report Metastability: Found 59 synchronizer chains.Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.Info (332114): Number of Synchronizer Chains Found: 59Info (332114): Shortest Synchronizer Chain: 2 RegistersInfo (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000Info (332114): Worst Case Available Settling Time: 15.621 nsInfo (332114):Info (332102): Design is not fully constrained for setup requirementsInfo (332102): Design is not fully constrained for hold requirementsInfo: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 1 warningInfo: Peak virtual memory: 1351 megabytesInfo: Processing ended: Fri Sep 15 08:19:10 2017Info: Elapsed time: 00:00:54Info: Total CPU time (on all processors): 00:01:15
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