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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [top_rtl/] [spw_fifo_ulight.v.bak] - Rev 32
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module SPW_ULIGHT_FIFO(
input FPGA_CLK1_50,
input [1:0] KEY,
input din_a,
input sin_a,
//input din_b,
//input sin_b,
output dout_a,
output sout_a,
//output dout_b,
//output sout_b,
//////////// LED ////////////
/* 3.3-V LVTTL */
output [7:0] LED
);