Subversion Repositories spacewiresystemc

Info: Starting: Create simulation model
Info: qsys-generate /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation --family="Cyclone V" --part=5CSEMA4U23C6
Progress: Loading spw_fifo_ulight/ulight_fifo.qsys
Progress: Reading input file
Progress: Adding auto_start [altera_avalon_pio 17.1]
Progress: Parameterizing module auto_start
Progress: Adding clk_0 [clock_source 17.1]
Progress: Parameterizing module clk_0
Progress: Adding clock_sel [altera_avalon_pio 17.1]
Progress: Parameterizing module clock_sel
Progress: Adding counter_rx_fifo [altera_avalon_pio 17.1]
Progress: Parameterizing module counter_rx_fifo
Progress: Adding counter_tx_fifo [altera_avalon_pio 17.1]
Progress: Parameterizing module counter_tx_fifo
Progress: Adding data_flag_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module data_flag_rx
Progress: Adding data_info [altera_avalon_pio 17.1]
Progress: Parameterizing module data_info
Progress: Adding data_read_en_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module data_read_en_rx
Progress: Adding fifo_empty_rx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_empty_rx_status
Progress: Adding fifo_empty_tx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_empty_tx_status
Progress: Adding fifo_full_rx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_full_rx_status
Progress: Adding fifo_full_tx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_full_tx_status
Progress: Adding fsm_info [altera_avalon_pio 17.1]
Progress: Parameterizing module fsm_info
Progress: Adding hps_0 [altera_hps 17.1]
Progress: Parameterizing module hps_0
Progress: Adding led_pio_test [altera_avalon_pio 17.1]
Progress: Parameterizing module led_pio_test
Progress: Adding link_disable [altera_avalon_pio 17.1]
Progress: Parameterizing module link_disable
Progress: Adding link_start [altera_avalon_pio 17.1]
Progress: Parameterizing module link_start
Progress: Adding pll_0 [altera_pll 17.1]
Progress: Parameterizing module pll_0
Progress: Adding timecode_ready_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_ready_rx
Progress: Adding timecode_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_rx
Progress: Adding timecode_tx_data [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_tx_data
Progress: Adding timecode_tx_enable [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_tx_enable
Progress: Adding timecode_tx_ready [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_tx_ready
Progress: Adding write_data_fifo_tx [altera_avalon_pio 17.1]
Progress: Parameterizing module write_data_fifo_tx
Progress: Adding write_en_tx [altera_avalon_pio 17.1]
Progress: Parameterizing module write_en_tx
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0  m = 36
Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0  m = 19
Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
Info: ulight_fifo.pll_0: Able to implement PLL with user settings
Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo: Generating ulight_fifo "ulight_fifo" for SIM_VERILOG
Warning: ulight_fifo: "No matching role found for clk_0:clk:clk_out (clk)"
Warning: ulight_fifo: "No matching role found for pll_0:refclk1:refclk1 (refclk1)"
Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'
Info: auto_start:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/  ]
Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'
Info: auto_start: "ulight_fifo" instantiated altera_avalon_pio "auto_start"
Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'
Info: clock_sel:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/  ]
Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'
Info: clock_sel: "ulight_fifo" instantiated altera_avalon_pio "clock_sel"
Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'
Info: counter_rx_fifo:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/  ]
Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'
Info: counter_rx_fifo: "ulight_fifo" instantiated altera_avalon_pio "counter_rx_fifo"
Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'
Info: data_flag_rx:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/  ]
Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'
Info: data_flag_rx: "ulight_fifo" instantiated altera_avalon_pio "data_flag_rx"
Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'
Info: data_info:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/  ]
Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'
Info: data_info: "ulight_fifo" instantiated altera_avalon_pio "data_info"
Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
Info: fifo_empty_rx_status:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/  ]
Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
Info: fifo_empty_rx_status: "ulight_fifo" instantiated altera_avalon_pio "fifo_empty_rx_status"
Info: hps_0: "Running  for module: hps_0"
Info: hps_0: HPS Main PLL counter settings: n = 0  m = 36
Info: hps_0: HPS peripherial PLL counter settings: n = 0  m = 19
Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
Warning: hps_0: set_interface_assignment: Interface "hps_io" does not exist
Info: hps_0: "ulight_fifo" instantiated altera_hps "hps_0"
Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'
Info: led_pio_test:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/  ]
Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'
Info: led_pio_test: "ulight_fifo" instantiated altera_avalon_pio "led_pio_test"
Info: pll_0: Generating simgen model
Info: pll_0: Info: ******************************************************************* Info: Running Quartus Prime Shell     Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition     Info: Copyright (C) 2017  Intel Corporation. All rights reserved.     Info: Your use of Intel Corporation's design tools, logic functions      Info: and other software and tools, and its AMPP partner logic      Info: functions, and any output files from any of the foregoing      Info: (including device programming or simulation files), and any      Info: associated documentation or information are expressly subject      Info: to the terms and conditions of the Intel Program License      Info: Subscription Agreement, the Intel Quartus Prime License Agreement,     Info: the Intel FPGA IP License Agreement, or other applicable license     Info: agreement, including, without limitation, that your use is for     Info: the sole purpose of programming logic devices manufactured by     Info: Intel and sold by Intel or its authorized distributors.  Please     Info: refer to the applicable agreement for further details.     Info: Processing started: Tue Jan 23 17:29:46 2018 Info: Command: quartus_sh -t run_simgen_cmd.tcl Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis     Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition     Info: Copyright (C) 2017  Intel Corporation. All rights reserved.     Info: Your use of Intel Corporation's design tools, logic functions      Info: and other software and tools, and its AMPP partner logic      Info: functions, and any output files from any of the foregoing      Info: (including device programming or simulation files), and any      Info: associated documentation or information are expressly subject      Info: to the terms and conditions of the Intel Program License      Info: Subscription Agreement, the Intel Quartus Prime License Agreement,     Info: the Intel FPGA IP License Agreement, or other applicable license     Info: agreement, including, without limitation, that your use is for     Info: the sole purpose of programming logic devices manufactured by     Info: Intel and sold by Intel or its authorized distributors.  Please     Info: refer to the applicable agreement for further details.     Info: Processing started: Tue Jan 23 17:29:50 2018 Info: Command: quartus_map ulight_fifo_pll_0.qpf --simgen --ini=disable_check_quartus_compatibility_qsys_only=on --simgen_parameter=CBX_HDL_LANGUAGE=VERILOG Info (20034): Auto device selection is not supported for Cyclone V device family. The default device, 5CGXFC7C7F23C8, is set. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo_pll_0.v     Info (12023): Found entity 1: ulight_fifo_pll_0 File: /tmp/alt7554_7831099621877055177.dir/0009_pll_0_gen/ulight_fifo_pll_0.v Line: 2 Info (12127): Elaborating entity "ulight_fifo_pll_0" for the top level hierarchy Info (12128): Elaborating entity "altera_pll" for hierarchy "altera_pll:altera_pll_i" File: /tmp/alt7554_7831099621877055177.dir/0009_pll_0_gen/ulight_fifo_pll_0.v Line: 241 Warning (10034): Output port "lvds_clk" at altera_pll.v(319) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 319 Warning (10034): Output port "loaden" at altera_pll.v(320) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 320 Warning (10034): Output port "extclk_out" at altera_pll.v(321) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 321 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus Info (12130): Elaborated megafunction instantiation "altera_pll:altera_pll_i" File: /tmp/alt7554_7831099621877055177.dir/0009_pll_0_gen/ulight_fifo_pll_0.v Line: 241 Info (12133): Instantiated megafunction "altera_pll:altera_pll_i" with the following parameter: File: /tmp/alt7554_7831099621877055177.dir/0009_pll_0_gen/ulight_fifo_pll_0.v Line: 241     Info (12134): Parameter "fractional_vco_multiplier" = "false"     Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz"     Info (12134): Parameter "pll_fractional_cout" = "32"     Info (12134): Parameter "pll_dsm_out_sel" = "1st_order"     Info (12134): Parameter "operation_mode" = "normal"     Info (12134): Parameter "number_of_clocks" = "1"     Info (12134): Parameter "output_clock_frequency0" = "400.000000 MHz"     Info (12134): Parameter "phase_shift0" = "0 ps"     Info (12134): Parameter "duty_cycle0" = "50"     Info (12134): Parameter "output_clock_frequency1" = "0 MHz"     Info (12134): Parameter "phase_shift1" = "0 ps"     Info (12134): Parameter "duty_cycle1" = "50"     Info (12134): Parameter "output_clock_frequency2" = "0 MHz"     Info (12134): Parameter "phase_shift2" = "0 ps"     Info (12134): Parameter "duty_cycle2" = "50"     Info (12134): Parameter "output_clock_frequency3" = "0 MHz"     Info (12134): Parameter "phase_shift3" = "0 ps"     Info (12134): Parameter "duty_cycle3" = "50"     Info (12134): Parameter "output_clock_frequency4" = "0 MHz"     Info (12134): Parameter "phase_shift4" = "0 ps"     Info (12134): Parameter "duty_cycle4" = "50"     Info (12134): Parameter "output_clock_frequency5" = "0 MHz"     Info (12134): Parameter "phase_shift5" = "0 ps"     Info (12134): Parameter "duty_cycle5" = "50"     Info (12134): Parameter "output_clock_frequency6" = "0 MHz"     Info (12134): Parameter "phase_shift6" = "0 ps"     Info (12134): Parameter "duty_cycle6" = "50"     Info (12134): Parameter "output_clock_frequency7" = "0 MHz"     Info (12134): Parameter "phase_shift7" = "0 ps"     Info (12134): Parameter "duty_cycle7" = "50"     Info (12134): Parameter "output_clock_frequency8" = "0 MHz"     Info (12134): Parameter "phase_shift8" = "0 ps"     Info (12134): Parameter "duty_cycle8" = "50"     Info (12134): Parameter "output_clock_frequency9" = "0 MHz"     Info (12134): Parameter "phase_shift9" = "0 ps"     Info (12134): Parameter "duty_cycle9" = "50"     Info (12134): Parameter "output_clock_frequency10" = "0 MHz"     Info (12134): Parameter "phase_shift10" = "0 ps"     Info (12134): Parameter "duty_cycle10" = "50"     Info (12134): Parameter "output_clock_frequency11" = "0 MHz"     Info (12134): Parameter "phase_shift11" = "0 ps"     Info (12134): Parameter "duty_cycle11" = "50"     Info (12134): Parameter "output_clock_frequency12" = "0 MHz"     Info (12134): Parameter "phase_shift12" = "0 ps"     Info (12134): Parameter "duty_cycle12" = "50"     Info (12134): Parameter "output_clock_frequency13" = "0 MHz"     Info (12134): Parameter "phase_shift13" = "0 ps"     Info (12134): Parameter "duty_cycle13" = "50"     Info (12134): Parameter "output_clock_frequency14" = "0 MHz"     Info (12134): Parameter "phase_shift14" = "0 ps"     Info (12134): Parameter "duty_cycle14" = "50"     Info (12134): Parameter "output_clock_frequency15" = "0 MHz"     Info (12134): Parameter "phase_shift15" = "0 ps"     Info (12134): Parameter "duty_cycle15" = "50"     Info (12134): Parameter "output_clock_frequency16" = "0 MHz"     Info (12134): Parameter "phase_shift16" = "0 ps"     Info (12134): Parameter "duty_cycle16" = "50"     Info (12134): Parameter "output_clock_frequency17" = "0 MHz"     Info (12134): Parameter "phase_shift17" = "0 ps"     Info (12134): Parameter "duty_cycle17" = "50"     Info (12134): Parameter "pll_type" = "Cyclone V"     Info (12134): Parameter "pll_subtype" = "General"     Info (12134): Parameter "m_cnt_hi_div" = "4"     Info (12134): Parameter "m_cnt_lo_div" = "4"     Info (12134): Parameter "n_cnt_hi_div" = "256"     Info (12134): Parameter "n_cnt_lo_div" = "256"     Info (12134): Parameter "m_cnt_bypass_en" = "false"     Info (12134): Parameter "n_cnt_bypass_en" = "true"     Info (12134): Parameter "m_cnt_odd_div_duty_en" = "false"     Info (12134): Parameter "n_cnt_odd_div_duty_en" = "false"     Info (12134): Parameter "c_cnt_hi_div0" = "256"     Info (12134): Parameter "c_cnt_lo_div0" = "256"     Info (12134): Parameter "c_cnt_prst0" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst0" = "0"     Info (12134): Parameter "c_cnt_in_src0" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en0" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en0" = "false"     Info (12134): Parameter "c_cnt_hi_div1" = "1"     Info (12134): Parameter "c_cnt_lo_div1" = "1"     Info (12134): Parameter "c_cnt_prst1" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst1" = "0"     Info (12134): Parameter "c_cnt_in_src1" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en1" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en1" = "false"     Info (12134): Parameter "c_cnt_hi_div2" = "1"     Info (12134): Parameter "c_cnt_lo_div2" = "1"     Info (12134): Parameter "c_cnt_prst2" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst2" = "0"     Info (12134): Parameter "c_cnt_in_src2" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en2" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en2" = "false"     Info (12134): Parameter "c_cnt_hi_div3" = "1"     Info (12134): Parameter "c_cnt_lo_div3" = "1"     Info (12134): Parameter "c_cnt_prst3" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst3" = "0"     Info (12134): Parameter "c_cnt_in_src3" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en3" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en3" = "false"     Info (12134): Parameter "c_cnt_hi_div4" = "1"     Info (12134): Parameter "c_cnt_lo_div4" = "1"     Info (12134): Parameter "c_cnt_prst4" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst4" = "0"     Info (12134): Parameter "c_cnt_in_src4" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en4" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en4" = "false"     Info (12134): Parameter "c_cnt_hi_div5" = "1"     Info (12134): Parameter "c_cnt_lo_div5" = "1"     Info (12134): Parameter "c_cnt_prst5" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst5" = "0"     Info (12134): Parameter "c_cnt_in_src5" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en5" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en5" = "false"     Info (12134): Parameter "c_cnt_hi_div6" = "1"     Info (12134): Parameter "c_cnt_lo_div6" = "1"     Info (12134): Parameter "c_cnt_prst6" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst6" = "0"     Info (12134): Parameter "c_cnt_in_src6" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en6" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en6" = "false"     Info (12134): Parameter "c_cnt_hi_div7" = "1"     Info (12134): Parameter "c_cnt_lo_div7" = "1"     Info (12134): Parameter "c_cnt_prst7" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst7" = "0"     Info (12134): Parameter "c_cnt_in_src7" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en7" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en7" = "false"     Info (12134): Parameter "c_cnt_hi_div8" = "1"     Info (12134): Parameter "c_cnt_lo_div8" = "1"     Info (12134): Parameter "c_cnt_prst8" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst8" = "0"     Info (12134): Parameter "c_cnt_in_src8" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en8" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en8" = "false"     Info (12134): Parameter "c_cnt_hi_div9" = "1"     Info (12134): Parameter "c_cnt_lo_div9" = "1"     Info (12134): Parameter "c_cnt_prst9" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst9" = "0"     Info (12134): Parameter "c_cnt_in_src9" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en9" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en9" = "false"     Info (12134): Parameter "c_cnt_hi_div10" = "1"     Info (12134): Parameter "c_cnt_lo_div10" = "1"     Info (12134): Parameter "c_cnt_prst10" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst10" = "0"     Info (12134): Parameter "c_cnt_in_src10" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en10" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en10" = "false"     Info (12134): Parameter "c_cnt_hi_div11" = "1"     Info (12134): Parameter "c_cnt_lo_div11" = "1"     Info (12134): Parameter "c_cnt_prst11" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst11" = "0"     Info (12134): Parameter "c_cnt_in_src11" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en11" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en11" = "false"     Info (12134): Parameter "c_cnt_hi_div12" = "1"     Info (12134): Parameter "c_cnt_lo_div12" = "1"     Info (12134): Parameter "c_cnt_prst12" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst12" = "0"     Info (12134): Parameter "c_cnt_in_src12" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en12" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en12" = "false"     Info (12134): Parameter "c_cnt_hi_div13" = "1"     Info (12134): Parameter "c_cnt_lo_div13" = "1"     Info (12134): Parameter "c_cnt_prst13" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst13" = "0"     Info (12134): Parameter "c_cnt_in_src13" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en13" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en13" = "false"     Info (12134): Parameter "c_cnt_hi_div14" = "1"     Info (12134): Parameter "c_cnt_lo_div14" = "1"     Info (12134): Parameter "c_cnt_prst14" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst14" = "0"     Info (12134): Parameter "c_cnt_in_src14" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en14" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en14" = "false"     Info (12134): Parameter "c_cnt_hi_div15" = "1"     Info (12134): Parameter "c_cnt_lo_div15" = "1"     Info (12134): Parameter "c_cnt_prst15" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst15" = "0"     Info (12134): Parameter "c_cnt_in_src15" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en15" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en15" = "false"     Info (12134): Parameter "c_cnt_hi_div16" = "1"     Info (12134): Parameter "c_cnt_lo_div16" = "1"     Info (12134): Parameter "c_cnt_prst16" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst16" = "0"     Info (12134): Parameter "c_cnt_in_src16" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en16" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en16" = "false"     Info (12134): Parameter "c_cnt_hi_div17" = "1"     Info (12134): Parameter "c_cnt_lo_div17" = "1"     Info (12134): Parameter "c_cnt_prst17" = "1"     Info (12134): Parameter "c_cnt_ph_mux_prst17" = "0"     Info (12134): Parameter "c_cnt_in_src17" = "ph_mux_clk"     Info (12134): Parameter "c_cnt_bypass_en17" = "true"     Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false"     Info (12134): Parameter "pll_vco_div" = "2"     Info (12134): Parameter "pll_cp_current" = "20"     Info (12134): Parameter "pll_bwctrl" = "4000"     Info (12134): Parameter "pll_output_clk_frequency" = "400.0 MHz"     Info (12134): Parameter "pll_fractional_division" = "1"     Info (12134): Parameter "mimic_fbclk_type" = "gclk"     Info (12134): Parameter "pll_fbclk_mux_1" = "glb"     Info (12134): Parameter "pll_fbclk_mux_2" = "fb_1"     Info (12134): Parameter "pll_m_cnt_in_src" = "ph_mux_clk"     Info (12134): Parameter "pll_slf_rst" = "false"     Info (12134): Parameter "refclk1_frequency" = "100.0 MHz"     Info (12134): Parameter "pll_clk_loss_sw_en" = "true"     Info (12134): Parameter "pll_manu_clk_sw_en" = "false"     Info (12134): Parameter "pll_auto_clk_sw_en" = "true"     Info (12134): Parameter "pll_clkin_1_src" = "clk_1"     Info (12134): Parameter "pll_clk_sw_dly" = "0" Info (281010): Generating sgate simulator netlist using Simgen SIMGEN_PROGRESS Start of Model generation -- 0% complete SIMGEN_PROGRESS Phase 1 : Internal Objects created -- 25% complete SIMGEN_PROGRESS Phase 2 : Connections between internal objects made -- 60% complete SIMGEN_PROGRESS Phase 3 : Netlist generated -- 100% complete Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings     Info: Peak virtual memory: 941 megabytes     Info: Processing ended: Tue Jan 23 17:30:09 2018     Info: Elapsed time: 00:00:19     Info: Total CPU time (on all processors): 00:00:40 Info (23030): Evaluation of Tcl script run_simgen_cmd.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings     Info: Peak virtual memory: 753 megabytes     Info: Processing ended: Tue Jan 23 17:30:10 2018     Info: Elapsed time: 00:00:24     Info: Total CPU time (on all processors): 00:00:41
Info: pll_0: Simgen was successful
Info: pll_0: "ulight_fifo" instantiated altera_pll "pll_0"
Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'
Info: timecode_rx:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/  ]
Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'
Info: timecode_rx: "ulight_fifo" instantiated altera_avalon_pio "timecode_rx"
Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'
Info: timecode_tx_data:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/  ]
Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'
Info: timecode_tx_data: "ulight_fifo" instantiated altera_avalon_pio "timecode_tx_data"
Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'
Info: write_data_fifo_tx:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/  ]
Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'
Info: write_data_fifo_tx: "ulight_fifo" instantiated altera_avalon_pio "write_data_fifo_tx"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "ulight_fifo" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: rst_controller: "ulight_fifo" instantiated altera_reset_controller "rst_controller"
Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
Info: led_pio_test_s1_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "led_pio_test_s1_translator"
Info: hps_0_h2f_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_axi_master_agent"
Info: led_pio_test_s1_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "led_pio_test_s1_agent"
Info: led_pio_test_s1_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "led_pio_test_s1_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: hps_0_h2f_axi_master_wr_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "hps_0_h2f_axi_master_wr_limiter"
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_sc_fifo.v
Info: led_pio_test_s1_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "led_pio_test_s1_burst_adapter"
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_merlin_address_alignment.sv
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_merlin_arbitrator.sv
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: border: "hps_io" instantiated altera_interface_generator "border"
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/verbosity_pkg.sv
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/avalon_utilities_pkg.sv
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/avalon_mm_pkg.sv
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_mm_slave_bfm.sv
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_interrupt_sink.sv
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_clock_source.sv
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_reset_source.sv
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: ulight_fifo: Done "ulight_fifo" with 32 modules, 58 files
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
Info:   mentor/msim_setup.tcl
Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
Info:   synopsys/vcs/vcs_setup.sh
Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
Info:   synopsys/vcsmx/synopsys_sim.setup
Info:   synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
Info:   cadence/cds.lib
Info:   cadence/hdl.var
Info:   cadence/ncsim_setup.sh
Info:   32 .cds.lib files in cadence/cds_libs/ directory
Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
Info:   aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo.qsys --block-symbol-file --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo --family="Cyclone V" --part=5CSEMA4U23C6
Progress: Loading spw_fifo_ulight/ulight_fifo.qsys
Progress: Reading input file
Progress: Adding auto_start [altera_avalon_pio 17.1]
Progress: Parameterizing module auto_start
Progress: Adding clk_0 [clock_source 17.1]
Progress: Parameterizing module clk_0
Progress: Adding clock_sel [altera_avalon_pio 17.1]
Progress: Parameterizing module clock_sel
Progress: Adding counter_rx_fifo [altera_avalon_pio 17.1]
Progress: Parameterizing module counter_rx_fifo
Progress: Adding counter_tx_fifo [altera_avalon_pio 17.1]
Progress: Parameterizing module counter_tx_fifo
Progress: Adding data_flag_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module data_flag_rx
Progress: Adding data_info [altera_avalon_pio 17.1]
Progress: Parameterizing module data_info
Progress: Adding data_read_en_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module data_read_en_rx
Progress: Adding fifo_empty_rx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_empty_rx_status
Progress: Adding fifo_empty_tx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_empty_tx_status
Progress: Adding fifo_full_rx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_full_rx_status
Progress: Adding fifo_full_tx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_full_tx_status
Progress: Adding fsm_info [altera_avalon_pio 17.1]
Progress: Parameterizing module fsm_info
Progress: Adding hps_0 [altera_hps 17.1]
Progress: Parameterizing module hps_0
Progress: Adding led_pio_test [altera_avalon_pio 17.1]
Progress: Parameterizing module led_pio_test
Progress: Adding link_disable [altera_avalon_pio 17.1]
Progress: Parameterizing module link_disable
Progress: Adding link_start [altera_avalon_pio 17.1]
Progress: Parameterizing module link_start
Progress: Adding pll_0 [altera_pll 17.1]
Progress: Parameterizing module pll_0
Progress: Adding timecode_ready_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_ready_rx
Progress: Adding timecode_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_rx
Progress: Adding timecode_tx_data [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_tx_data
Progress: Adding timecode_tx_enable [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_tx_enable
Progress: Adding timecode_tx_ready [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_tx_ready
Progress: Adding write_data_fifo_tx [altera_avalon_pio 17.1]
Progress: Parameterizing module write_data_fifo_tx
Progress: Adding write_en_tx [altera_avalon_pio 17.1]
Progress: Parameterizing module write_en_tx
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0  m = 36
Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0  m = 19
Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
Info: ulight_fifo.pll_0: Able to implement PLL with user settings
Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo.qsys --synthesis=VERILOG --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis --family="Cyclone V" --part=5CSEMA4U23C6
Progress: Loading spw_fifo_ulight/ulight_fifo.qsys
Progress: Reading input file
Progress: Adding auto_start [altera_avalon_pio 17.1]
Progress: Parameterizing module auto_start
Progress: Adding clk_0 [clock_source 17.1]
Progress: Parameterizing module clk_0
Progress: Adding clock_sel [altera_avalon_pio 17.1]
Progress: Parameterizing module clock_sel
Progress: Adding counter_rx_fifo [altera_avalon_pio 17.1]
Progress: Parameterizing module counter_rx_fifo
Progress: Adding counter_tx_fifo [altera_avalon_pio 17.1]
Progress: Parameterizing module counter_tx_fifo
Progress: Adding data_flag_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module data_flag_rx
Progress: Adding data_info [altera_avalon_pio 17.1]
Progress: Parameterizing module data_info
Progress: Adding data_read_en_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module data_read_en_rx
Progress: Adding fifo_empty_rx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_empty_rx_status
Progress: Adding fifo_empty_tx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_empty_tx_status
Progress: Adding fifo_full_rx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_full_rx_status
Progress: Adding fifo_full_tx_status [altera_avalon_pio 17.1]
Progress: Parameterizing module fifo_full_tx_status
Progress: Adding fsm_info [altera_avalon_pio 17.1]
Progress: Parameterizing module fsm_info
Progress: Adding hps_0 [altera_hps 17.1]
Progress: Parameterizing module hps_0
Progress: Adding led_pio_test [altera_avalon_pio 17.1]
Progress: Parameterizing module led_pio_test
Progress: Adding link_disable [altera_avalon_pio 17.1]
Progress: Parameterizing module link_disable
Progress: Adding link_start [altera_avalon_pio 17.1]
Progress: Parameterizing module link_start
Progress: Adding pll_0 [altera_pll 17.1]
Progress: Parameterizing module pll_0
Progress: Adding timecode_ready_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_ready_rx
Progress: Adding timecode_rx [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_rx
Progress: Adding timecode_tx_data [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_tx_data
Progress: Adding timecode_tx_enable [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_tx_enable
Progress: Adding timecode_tx_ready [altera_avalon_pio 17.1]
Progress: Parameterizing module timecode_tx_ready
Progress: Adding write_data_fifo_tx [altera_avalon_pio 17.1]
Progress: Parameterizing module write_data_fifo_tx
Progress: Adding write_en_tx [altera_avalon_pio 17.1]
Progress: Parameterizing module write_en_tx
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0  m = 36
Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0  m = 19
Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
Info: ulight_fifo.pll_0: Able to implement PLL with user settings
Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ulight_fifo: Generating ulight_fifo "ulight_fifo" for QUARTUS_SYNTH
Warning: ulight_fifo: "No matching role found for clk_0:clk:clk_out (clk)"
Warning: ulight_fifo: "No matching role found for pll_0:refclk1:refclk1 (refclk1)"
Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'
Info: auto_start:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl  --do_build_sim=0  ]
Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'
Info: auto_start: "ulight_fifo" instantiated altera_avalon_pio "auto_start"
Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'
Info: clock_sel:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl  --do_build_sim=0  ]
Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'
Info: clock_sel: "ulight_fifo" instantiated altera_avalon_pio "clock_sel"
Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'
Info: counter_rx_fifo:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl  --do_build_sim=0  ]
Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'
Info: counter_rx_fifo: "ulight_fifo" instantiated altera_avalon_pio "counter_rx_fifo"
Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'
Info: data_flag_rx:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl  --do_build_sim=0  ]
Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'
Info: data_flag_rx: "ulight_fifo" instantiated altera_avalon_pio "data_flag_rx"
Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'
Info: data_info:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen//ulight_fifo_data_info_component_configuration.pl  --do_build_sim=0  ]
Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'
Info: data_info: "ulight_fifo" instantiated altera_avalon_pio "data_info"
Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
Info: fifo_empty_rx_status:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl  --do_build_sim=0  ]
Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
Info: fifo_empty_rx_status: "ulight_fifo" instantiated altera_avalon_pio "fifo_empty_rx_status"
Info: hps_0: "Running  for module: hps_0"
Info: hps_0: HPS Main PLL counter settings: n = 0  m = 36
Info: hps_0: HPS peripherial PLL counter settings: n = 0  m = 19
Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
Warning: hps_0: set_interface_assignment: Interface "hps_io" does not exist
Info: hps_0: "ulight_fifo" instantiated altera_hps "hps_0"
Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'
Info: led_pio_test:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl  --do_build_sim=0  ]
Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'
Info: led_pio_test: "ulight_fifo" instantiated altera_avalon_pio "led_pio_test"
Info: pll_0: "ulight_fifo" instantiated altera_pll "pll_0"
Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'
Info: timecode_rx:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl  --do_build_sim=0  ]
Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'
Info: timecode_rx: "ulight_fifo" instantiated altera_avalon_pio "timecode_rx"
Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'
Info: timecode_tx_data:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl  --do_build_sim=0  ]
Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'
Info: timecode_tx_data: "ulight_fifo" instantiated altera_avalon_pio "timecode_tx_data"
Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'
Info: write_data_fifo_tx:   Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl  --do_build_sim=0  ]
Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'
Info: write_data_fifo_tx: "ulight_fifo" instantiated altera_avalon_pio "write_data_fifo_tx"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "ulight_fifo" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: rst_controller: "ulight_fifo" instantiated altera_reset_controller "rst_controller"
Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
Info: led_pio_test_s1_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "led_pio_test_s1_translator"
Info: hps_0_h2f_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_axi_master_agent"
Info: led_pio_test_s1_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "led_pio_test_s1_agent"
Info: led_pio_test_s1_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "led_pio_test_s1_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: hps_0_h2f_axi_master_wr_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "hps_0_h2f_axi_master_wr_limiter"
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v
Info: led_pio_test_s1_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "led_pio_test_s1_burst_adapter"
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: border: "hps_io" instantiated altera_interface_generator "border"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: ulight_fifo: Done "ulight_fifo" with 32 modules, 89 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis