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https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys.ucf] - Rev 24
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# This file is a general .ucf for Atlys rev C board# To use it in a project:# - remove or comment the lines corresponding to unused pins# - rename the used signals according to the project# clock pin for Atlys rev C board#### NET "gclk_i" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK# onBoard USB controller# NET "EppAstb" LOC = "B9"; # Bank = 0, Pin name = IO_L35P_GCLK17, Sch name = U1-FLAGA# NET "EppDstb" LOC = "A9"; # Bank = 0, Pin name = IO_L35N_GCLK16, Sch name = U1-FLAGB# NET "UsbFlag" LOC = "C15"; # Bank = 0, Pin name = IO_L64P_SCP5, Sch name = U1-FLAGC# NET "EppWait" LOC = "F13"; # Bank = 0, Pin name = IO_L63P_SCP7, Sch name = U1-SLRD# NET "EppDB<0>" LOC = "A2"; # Bank = 0, Pin name = IO_L2N, Sch name = U1-FD0# NET "EppDB<1>" LOC = "D6"; # Bank = 0, Pin name = IO_L3P, Sch name = U1-FD1# NET "EppDB<2>" LOC = "C6"; # Bank = 0, Pin name = IO_L3N, Sch name = U1-FD2# NET "EppDB<3>" LOC = "B3"; # Bank = 0, Pin name = IO_L4P, Sch name = U1-FD3# NET "EppDB<4>" LOC = "A3"; # Bank = 0, Pin name = IO_L4N, Sch name = U1-FD4# NET "EppDB<5>" LOC = "B4"; # Bank = 0, Pin name = IO_L5P, Sch name = U1-FD5# NET "EppDB<6>" LOC = "A4"; # Bank = 0, Pin name = IO_L5N, Sch name = U1-FD6# NET "EppDB<7>" LOC = "C5"; # Bank = 0, Pin name = IO_L6P, Sch name = U1-FD7# NET "UsbClk" LOC = "C10"; # Bank = 0, Pin name = IO_L37P_GCLK13, Sch name = U1-IFCLK# NET "UsbOE" LOC = "A15"; # Bank = 0, Pin name = IO_L64N_SCP4, Sch name = U1-SLOE# NET "UsbWR" LOC = "E13"; # Bank = 0, Pin name = IO_L63N_SCP6, Sch name = U1-SLWR# NET "UsbPktEnd" LOC = "C4"; # Bank = 0, Pin name = IO_L1N_VREF, Sch name = U1-PKTEND# NET "UsbDir" LOC = "B2"; # Bank = 0, Pin name = IO_L2P, Sch name = U1-SLCS# NET "UsbMode" LOC = "A5"; # Bank = 0, Pin name = IO_L6N, Sch name = U1-INT0## NET "UsbAdr<0>" LOC = "A14"; # Bank = 0, Pin name = IO_L62N_VREF, Sch name = U1-FIFOAD0# NET "UsbAdr<1>" LOC = "B14"; # Bank = 0, Pin name = IO_L62P, Sch name = U1-FIFOAD1# onBoard Quad-SPI Flash# NET "FlashCLK" LOC = "R15"; # Bank = 2, Pin name = IO_L1P_CCLK_2, Sch name = SCK# NET "FlashCS" LOC = "V3"; # Bank = 2, Pin name = IO_L65N_CSO_B_2, Sch name = CS# NET "FlashMemDq<0>" LOC = "T13"; # Bank = 2, Pin name = IO_L3N_MOSI_CSI_B_MISO0_2, Sch name = SDI# NET "FlashMemDq<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L3P_D0_DIN_MISO_MISO1_2, Sch name = DQ1# NET "FlashMemDq<2>" LOC = "T14"; # Bank = 2, Pin name = IO_L12P_D1_MISO2_2, Sch name = DQ2# NET "FlashMemDq<3>" LOC = "V14"; # Bank = 2, Pin name = IO_L12N_D2_MISO3_2, Sch name = DQ3# onBoard LedsNET "led_o<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = LD0NET "led_o<1>" LOC = "M14"; # Bank = 1, Pin name = IO_L53P, Sch name = LD1NET "led_o<2>" LOC = "N14"; # Bank = 1, Pin name = IO_L53N_VREF, Sch name = LD2NET "led_o<3>" LOC = "L14"; # Bank = 1, Pin name = IO_L61P, Sch name = LD3NET "led_o<4>" LOC = "M13"; # Bank = 1, Pin name = IO_L61N, Sch name = LD4NET "led_o<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5NET "led_o<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6NET "led_o<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7# onBoard PUSH BUTTONSNET "btn_i<0>" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESETNET "btn_i<1>" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNUNET "btn_i<2>" LOC = "P4"; # Bank = 3, Pin name = IO_L2P, Sch name = BTNLNET "btn_i<3>" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTNDNET "btn_i<4>" LOC = "F6"; # Bank = 3, Pin name = IO_L55P_M3A13, Sch name = BTNRNET "btn_i<5>" LOC = "F5"; # Bank = 3, Pin name = IO_L55N_M3A14, Sch name = BTNC# onBoard SWITCHESNET "sw_i<0>" LOC = "A10"; # Bank = 0, Pin name = IO_L37N_GCLK12, Sch name = SW0NET "sw_i<1>" LOC = "D14"; # Bank = 0, Pin name = IO_L65P_SCP3, Sch name = SW1NET "sw_i<2>" LOC = "C14"; # Bank = 0, Pin name = IO_L65N_SCP2, Sch name = SW2NET "sw_i<3>" LOC = "P15"; # Bank = 1, Pin name = IO_L74P_AWAKE_1, Sch name = SW3NET "sw_i<4>" LOC = "P12"; # Bank = 2, Pin name = IO_L13N_D10, Sch name = SW4NET "sw_i<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5NET "sw_i<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6NET "sw_i<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7# TEMAC Ethernet MAC# NET "phyrst" LOC = "G13"; # Bank = 1, Pin name = IO_L32N_A16_M1A9, Sch name = E-RESET# NET "phytxclk" LOC = "K16"; # Bank = 1, Pin name = IO_L41N_GCLK8_M1CASN, Sch name = E-TXCLK# NET "phyTXD<0>" LOC = "H16"; # Bank = 1, Pin name = IO_L37N_A6_M1A1, Sch name = E-TXD0# NET "phyTXD<1>" LOC = "H13"; # Bank = 1, Pin name = IO_L36P_A9_M1BA0, Sch name = E-TXD1# NET "phyTXD<2>" LOC = "K14"; # Bank = 1, Pin name = IO_L39N_M1ODT, Sch name = E-TXD2# NET "phyTXD<3>" LOC = "K13"; # Bank = 1, Pin name = IO_L34N_A12_M1BA2, Sch name = E-TXD3# NET "phyTXD<4>" LOC = "J13"; # Bank = 1, Pin name = IO_L39P_M1A3, Sch name = E-TXD4# NET "phyTXD<5>" LOC = "G14"; # Bank = 1, Pin name = IO_L30N_A20_M1A11, Sch name = E-TXD5# NET "phyTXD<6>" LOC = "H12"; # Bank = 1, Pin name = IO_L32P_A17_M1A8, Sch name = E-TXD6# NET "phyTXD<7>" LOC = "K12"; # Bank = 1, Pin name = IO_L34P_A13_M1WE, Sch name = E-TXD7# NET "phytxen" LOC = "H15"; # Bank = 1, Pin name = IO_L37P_A7_M1A0, Sch name = E-TXEN# NET "phytxer" LOC = "G18"; # Bank = 1, Pin name = IO_L38N_A4_M1CLKN, Sch name = E-TXER# NET "phygtxclk" LOC = "L12"; # Bank = 1, Pin name = IO_L40P_GCLK11_M1A5, Sch name = E-GTXCLK# NET "phyRXD<0>" LOC = "G16"; # Bank = 1, Pin name = IO_L38P_A5_M1CLK, Sch name = E-RXD0# NET "phyRXD<1>" LOC = "H14"; # Bank = 1, Pin name = IO_L36N_A8_M1BA1, Sch name = E-RXD1# NET "phyRXD<2>" LOC = "E16"; # Bank = 1, Pin name = IO_L33P_A15_M1A10, Sch name = E-RXD2# NET "phyRXD<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L1P_A25, Sch name = E-RXD3# NET "phyRXD<4>" LOC = "F14"; # Bank = 1, Pin name = IO_L30P_A21_M1RESET, Sch name = E-RXD4# NET "phyRXD<5>" LOC = "E18"; # Bank = 1, Pin name = IO_L33N_A14_M1A4, Sch name = E-RXD5# NET "phyRXD<6>" LOC = "D18"; # Bank = 1, Pin name = IO_L31N_A18_M1A12, Sch name = E-RXD6# NET "phyRXD<7>" LOC = "D17"; # Bank = 1, Pin name = IO_L31P_A19_M1CKE, Sch name = E-RXD7# NET "phyrxdv" LOC = "F17"; # Bank = 1, Pin name = IO_L35P_A11_M1A7, Sch name = E-RXDV# NET "phyrxer" LOC = "F18"; # Bank = 1, Pin name = IO_L35N_A10_M1A2, Sch name = E-RXER# NET "phyrxclk" LOC = "K15"; # Bank = 1, Pin name = IO_L41P_GCLK9_IRDY1_M1RASN, Sch name = E-RXCLK# NET "phymdc" LOC = "F16"; # Bank = 1, Pin name = IO_L1N_A24_VREF, Sch name = E-MDC# NET "phymdi" LOC = "N17"; # Bank = 1, Pin name = IO_L48P_HDC_M1DQ8, Sch name = E-MDIO# NET "phyint" LOC = "L16"; # Bank = 1, Pin name = IO_L42N_GCLK6_TRDY1_M1LDM, Sch name = E-INT# DDR2# NET "DDR2CLK0" LOC = "G3"; # Bank = 3, Pin name = IO_L46P_M3CLK, Sch name = DDR-CK_P# NET "DDR2CLK1" LOC = "G1"; # Bank = 3, Pin name = IO_L46N_M3CLKN, Sch name = DDR-CK_N# NET "DDR2CKE" LOC = "H7"; # Bank = 3, Pin name = IO_L53P_M3CKE, Sch name = DDR-CKE# NET "DDR2RASN" LOC = "L5"; # Bank = 3, Pin name = IO_L43P_GCLK23_M3RASN, Sch name = DDR-RAS# NET "DDR2CASN" LOC = "K5"; # Bank = 3, Pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = DDR-CAS# NET "DDR2WEN" LOC = "E3"; # Bank = 3, Pin name = IO_L50P_M3WE, Sch name = DDR-WE# NET "DDR2RZQ" LOC = "L6"; # Bank = 3, Pin name = IO_L31P, Sch name = RZQ# NET "DDR2ZIO" LOC = "C2"; # Bank = 3, Pin name = IO_L83P, Sch name = ZIO# NET "DDR2BA0" LOC = "F2"; # Bank = 3, Pin name = IO_L48P_M3BA0, Sch name = DDR-BA0# NET "DDR2BA1" LOC = "F1"; # Bank = 3, Pin name = IO_L48N_M3BA1, Sch name = DDR-BA1# NET "DDR2BA2" LOC = "E1"; # Bank = 3, Pin name = IO_L50N_M3BA2, Sch name = DDR-BA2# NET "DDR2A0" LOC = "J7"; # Bank = 3, Pin name = IO_L47P_M3A0, Sch name = DDR-A0# NET "DDR2A1" LOC = "J6"; # Bank = 3, Pin name = IO_L47N_M3A1, Sch name = DDR-A1# NET "DDR2A2" LOC = "H5"; # Bank = 3, Pin name = IO_L49N_M3A2, Sch name = DDR-A2# NET "DDR2A3" LOC = "L7"; # Bank = 3, Pin name = IO_L45P_M3A3, Sch name = DDR-A3# NET "DDR2A4" LOC = "F3"; # Bank = 3, Pin name = IO_L51N_M3A4, Sch name = DDR-A4# NET "DDR2A5" LOC = "H4"; # Bank = 3, Pin name = IO_L44P_GCLK21_M3A5, Sch name = DDR-A5# NET "DDR2A6" LOC = "H3"; # Bank = 3, Pin name = IO_L44N_GCLK20_M3A6, Sch name = DDR-A6# NET "DDR2A7" LOC = "H6"; # Bank = 3, Pin name = IO_L49P_M3A7, Sch name = DDR-A7# NET "DDR2A8" LOC = "D2"; # Bank = 3, Pin name = IO_L52P_M3A8, Sch name = DDR-A8# NET "DDR2A9" LOC = "D1"; # Bank = 3, Pin name = IO_L52N_M3A9, Sch name = DDR-A9# NET "DDR2A10" LOC = "F4"; # Bank = 3, Pin name = IO_L51P_M3A10, Sch name = DDR-A10# NET "DDR2A11" LOC = "D3"; # Bank = 3, Pin name = IO_L54N_M3A11, Sch name = DDR-A11# NET "DDR2A12" LOC = "G6"; # Bank = 3, Pin name = IO_L53N_M3A12, Sch name = DDR-A12# NET "DDR2DQ0" LOC = "L2"; # Bank = 3, Pin name = IO_L37P_M3DQ0, Sch name = DDR-DQ0# NET "DDR2DQ1" LOC = "L1"; # Bank = 3, Pin name = IO_L37N_M3DQ1, Sch name = DDR-DQ1# NET "DDR2DQ2" LOC = "K2"; # Bank = 3, Pin name = IO_L38P_M3DQ2, Sch name = DDR-DQ2# NET "DDR2DQ3" LOC = "K1"; # Bank = 3, Pin name = IO_L38N_M3DQ3, Sch name = DDR-DQ3# NET "DDR2DQ4" LOC = "H2"; # Bank = 3, Pin name = IO_L41P_GCLK27_M3DQ4, Sch name = DDR-DQ4# NET "DDR2DQ5" LOC = "H1"; # Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5, Sch name = DDR-DQ5# NET "DDR2DQ6" LOC = "J3"; # Bank = 3, Pin name = IO_L40P_M3DQ6, Sch name = DDR-DQ6# NET "DDR2DQ7" LOC = "J1"; # Bank = 3, Pin name = IO_L40N_M3DQ7, Sch name = DDR-DQ7# NET "DDR2DQ8" LOC = "M3"; # Bank = 3, Pin name = IO_L36P_M3DQ8, Sch name = DDR-DQ8# NET "DDR2DQ9" LOC = "M1"; # Bank = 3, Pin name = IO_L36N_M3DQ9, Sch name = DDR-DQ9# NET "DDR2DQ10" LOC = "N2"; # Bank = 3, Pin name = IO_L35P_M3DQ10, Sch name = DDR-DQ10# NET "DDR2DQ11" LOC = "N1"; # Bank = 3, Pin name = IO_L35N_M3DQ11, Sch name = DDR-DQ11# NET "DDR2DQ12" LOC = "T2"; # Bank = 3, Pin name = IO_L33P_M3DQ12, Sch name = DDR-DQ12# NET "DDR2DQ13" LOC = "T1"; # Bank = 3, Pin name = IO_L33N_M3DQ13, Sch name = DDR-DQ13# NET "DDR2DQ14" LOC = "U2"; # Bank = 3, Pin name = IO_L32P_M3DQ14, Sch name = DDR-DQ14# NET "DDR2DQ15" LOC = "U1"; # Bank = 3, Pin name = IO_L32N_M3DQ15, Sch name = DDR-DQ15# NET "DDR2UDQS" LOC="P2"; # Bank = 3, Pin name = IO_L34P_M3UDQS, Sch name = DDR-UDQS_P# NET "DDR2UDQSN" LOC="P1"; # Bank = 3, Pin name = IO_L34N_M3UDQSN, Sch name = DDR-UDQS_N# NET "DDR2LDQS" LOC="L4"; # Bank = 3, Pin name = IO_L39P_M3LDQS, Sch name = DDR-LDQS_P# NET "DDR2LDQSN" LOC="L3"; # Bank = 3, Pin name = IO_L39N_M3LDQSN, Sch name = DDR-LDQS_N# NET "DDR2LDM" LOC="K3"; # Bank = 3, Pin name = IO_L42N_GCLK24_M3LDM, Sch name = DDR-LDM# NET "DDR2UDM" LOC="K4"; # Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = DDR-UDM# NET "DDR2ODT" LOC="K6"; # Bank = 3, Pin name = IO_L45N_M3ODT, Sch name = DDR-ODT# NET "DDR2ZIO" LOC="C2"; # Bank = 3, Pin name = IO_L83P, Sch name = DDR-ODT# NET "DDR2RZM" LOC="L6"; # Bank = 3, Pin name = IO_L31P, Sch name = DDR-ODT# onboard HDMI OUT# NET "HDMIOUTCLKP" LOC = "B6"; # Bank = 0, Pin name = IO_L8P, Sch name = TMDS-TX-CLK_P# NET "HDMIOUTCLKN" LOC = "A6"; # Bank = 0, Pin name = IO_L8N_VREF, Sch name = TMDS-TX-CLK_N# NET "HDMIOUTD0P" LOC = "D8"; # Bank = 0, Pin name = IO_L11P, Sch name = TMDS-TX-0_P# NET "HDMIOUTD0N" LOC = "C8"; # Bank = 0, Pin name = IO_L11N, Sch name = TMDS-TX-0_N# NET "HDMIOUTD1P" LOC = "C7"; # Bank = 0, Pin name = IO_L10P, Sch name = TMDS-TX-1_P# NET "HDMIOUTD1N" LOC = "A7"; # Bank = 0, Pin name = IO_L10N, Sch name = TMDS-TX-1_N# NET "HDMIOUTD2P" LOC = "B8"; # Bank = 0, Pin name = IO_L33P, Sch name = TMDS-TX-2_P# NET "HDMIOUTD2N" LOC = "A8"; # Bank = 0, Pin name = IO_L33N, Sch name = TMDS-TX-2_N# NET "HDMIOUTSCL" LOC = "D9"; # Bank = 0, Pin name = IO_L34P_GCLK19, Sch name = TMDS-TX-SCL# NET "HDMIOUTSDA" LOC = "C9"; # Bank = 0, Pin name = IO_L34N_GCLK18, Sch name = TMDS-TX-SDA# onboard HDMI IN1 (PMODA)# NET "HDMIIN1CLKP" LOC = "D11"; # Bank = 0, Pin name = IO_L36P_GCLK15, Sch name = TMDS-RXB-CLK_P# NET "HDMIIN1CLKN" LOC = "C11"; # Bank = 0, Pin name = IO_L36N_GCLK14, Sch name = TMDS-RXB-CLK_N# NET "HDMIIN1D0P" LOC = "G9"; # Bank = 0, Pin name = IO_L38P, Sch name = TMDS-RXB-0_P# NET "HDMIIN1D0N" LOC = "F9"; # Bank = 0, Pin name = IO_L38N_VREF, Sch name = TMDS-RXB-0_N# NET "HDMIIN1D1P" LOC = "B11"; # Bank = 0, Pin name = IO_L39P, Sch name = TMDS-RXB-1_P# NET "HDMIIN1D1N" LOC = "A11"; # Bank = 0, Pin name = O_L39N, Sch name = TMDS-RXB-1_N# NET "HDMIIN1D2P" LOC = "B12"; # Bank = 0, Pin name = IO_L41P, Sch name = TMDS-RXB-2_P# NET "HDMIIN1D2N" LOC = "A12"; # Bank = 0, Pin name = IO_L41N, Sch name = TMDS-RXB-2_N# NET "HDMIIN1SCL" LOC = "C13"; # Bank = 0, Pin name = IO_L50P, Sch name = PMOD-SCL# NET "HDMIIN1SDA" LOC = "A13"; # Bank = 0, Pin name = IO_L50N, Sch name = PMOD-SDA# onboard HDMI IN2# NET "HDMIIN2CLKP" LOC = "H17"; # Bank = 1, Pin name = IO_L43P_GCLK5_M1DQ4, Sch name = TMDS-RX-CLK_P# NET "HDMIIN2CLKN" LOC = "H18"; # Bank = 1, Pin name = IO_L43N_GCLK4_M1DQ5, Sch name = TMDS-RX-CLK_N# NET "HDMIIN2D0P" LOC = "K17"; # Bank = 1, Pin name = IO_L45P_A1_M1LDQS, Sch name = TMDS-RX-0_P# NET "HDMIIN2D0N" LOC = "K18"; # Bank = 1, Pin name = IO_L45N_A0_M1LDQSN, Sch name = TMDS-RX-0_N# NET "HDMIIN2D1P" LOC = "L17"; # Bank = 1, Pin name = IO_L46P_FCS_B_M1DQ2, Sch name = TMDS-RX-1_P# NET "HDMIIN2D1N" LOC = "L18"; # Bank = 1, Pin name = IO_L46N_FOE_B_M1DQ3, Sch name = TMDS-RX-1_N# NET "HDMIIN2D2P" LOC = "J16"; # Bank = 1, Pin name = IO_L44P_A3_M1DQ6, Sch name = TMDS-RX-2_P# NET "HDMIIN2D2N" LOC = "J18"; # Bank = 1, Pin name = IO_L44N_A2_M1DQ7, Sch name = TMDS-RX-2_N# NET "HDMIIN2SCL" LOC = "M16"; # Bank = 1, Pin name = IO_L47P_FWE_B_M1DQ0, Sch name = TMDS-RX-SCL# NET "HDMIIN2SDA" LOC = "M18"; # Bank = 1, Pin name = IO_L47N_LDC_M1DQ1, Sch name = TMDS-RX-SDA# onboard USB Host Controller# NET "USBCLK" LOC = "P17"; # Bank = 1, Pin name = IO_L49P_M1DQ10, Sch name = PIC32-SCK1# NET "USBSS" LOC = "P18"; # Bank = 1, Pin name = IO_L49N_M1DQ11, Sch name = PIC32-SS1# NET "USBSDI" LOC = "N15"; # Bank = 1, Pin name = IO_L50P_M1UDQS, Sch name = PIC32-SDI1# NET "USBSDO" LOC = "N18"; # Bank = 1, Pin name = IO_L48N_M1DQ9, Sch name = PIC32-SDO1# Audio# NET "BITCLK" LOC = "L13"; # Bank = 1, Pin name = IO_L40N_GCLK10_M1A6, Sch name = AUD-BIT-CLK# NET "AUDSDI" LOC = "T18"; # Bank = 1, Pin name = IO_L51N_M1DQ13, Sch name = AUD-SDI# NET "AUDSDO" LOC = "N16"; # Bank = 1, Pin name = IO_L50N_M1UDQSN, Sch name = AUD-SDO# NET "AUDSYNC" LOC = "U17"; # Bank = 1, Pin name = IO_L52P_M1DQ14, Sch name = AUD-SYNC# NET "AUDRST" LOC = "T17"; # Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = AUD-RESET# PMOD ConnectorNET "m_state_o<0>" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, PMOD JB<1>, Sch name = JA-D0_NNET "m_state_o<1>" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, PMOD JB<2>, Sch name = JA-D0_PNET "m_state_o<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, PMOD JB<3>, Sch name = JA-D2_NNET "m_state_o<3>" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, PMOD JB<4>, Sch name = JA-D2_PNET "s_state_o<0>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, PMOD JB<7>, Sch name = JA-CLK_NNET "s_state_o<1>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, PMOD JB<8>, Sch name = JA-CLK_PNET "s_state_o<2>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, PMOD JB<9>, Sch name = JA-D1_NNET "s_state_o<3>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, PMOD JB<10>, Sch name = JA-D1_P# onboard VHDCI# Channnel 1 connects to P signals, Channel 2 to N signals# 16bit debug outputs for MSO2014 digital signals, in 2 pod connectors# D15-D8 connector podNET "spi_ssel_o" LOC = "U16"; # Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = EXP-IO1_P, MSO D15NET "spi_sck_o" LOC = "V16"; # Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = EXP-IO1_N, MSO D14NET "spi_mosi_o" LOC = "U15"; # Bank = 2, Pin name = *IO_L5P, Sch name = EXP-IO2_P, MSO D13NET "spi_miso_o" LOC = "V15"; # Bank = 2, Pin name = *IO_L5N, Sch name = EXP-IO2_N, MSO D12NET "dbg_o<11>" LOC = "U13"; # Bank = 2, Pin name = IO_L14P_D11, Sch name = EXP-IO3_P, MSO D11NET "dbg_o<10>" LOC = "V13"; # Bank = 2, Pin name = IO_L14N_D12, Sch name = EXP-IO3_N, MSO D10NET "dbg_o<9>" LOC = "M11"; # Bank = 2, Pin name = *IO_L15P, Sch name = EXP-IO4_P, MSO D9NET "dbg_o<8>" LOC = "N11"; # Bank = 2, Pin name = *IO_L15N, Sch name = EXP-IO4_N, MSO D8# D7-D0 connector podNET "dbg_o<7>" LOC = "R11"; # Bank = 2, Pin name = IO_L16P, Sch name = EXP-IO5_P, MSO D7NET "dbg_o<6>" LOC = "T11"; # Bank = 2, Pin name = IO_L16N_VREF, Sch name = EXP-IO5_N, MSO D6NET "dbg_o<5>" LOC = "T12"; # Bank = 2, Pin name = *IO_L19P, Sch name = EXP-IO6_P, MSO D5NET "dbg_o<4>" LOC = "V12"; # Bank = 2, Pin name = *IO_L19N, Sch name = EXP-IO6_N, MSO D4NET "dbg_o<3>" LOC = "N10"; # Bank = 2, Pin name = *IO_L20P, Sch name = EXP-IO7_P, MSO D3NET "dbg_o<2>" LOC = "P11"; # Bank = 2, Pin name = *IO_L20N, Sch name = EXP-IO7_N, MSO D2NET "dbg_o<1>" LOC = "M10"; # Bank = 2, Pin name = *IO_L22P, Sch name = EXP-IO8_P, MSO D1NET "dbg_o<0>" LOC = "N9"; # Bank = 2, Pin name = *IO_L22N, Sch name = EXP-IO8_N, MSO D0# NET "VHDCIIO1<8>" LOC = "U11"; # Bank = 2, Pin name = IO_L23P, Sch name = EXP-IO9_P# NET "VHDCIIO1<9>" LOC = "R10"; # Bank = 2, Pin name = IO_L29P_GCLK3, Sch name = EXP-IO10_P# NET "VHDCIIO1<10>" LOC = "U10"; # Bank = 2, Pin name = IO_L30P_GCLK1_D13, Sch name = EXP-IO11_P# NET "VHDCIIO1<11>" LOC = "R8"; # Bank = 2, Pin name = IO_L31P_GCLK31_D14, Sch name = EXP-IO12_P# NET "VHDCIIO1<12>" LOC = "M8"; # Bank = 2, Pin name = *IO_L40P, Sch name = EXP-IO13_P# NET "VHDCIIO1<13>" LOC = "U8"; # Bank = 2, Pin name = IO_L41P, Sch name = EXP-IO14_P# NET "VHDCIIO1<14>" LOC = "U7"; # Bank = 2, Pin name = IO_L43P, Sch name = EXP-IO15_P# NET "VHDCIIO1<15>" LOC = "N7"; # Bank = 2, Pin name = *IO_L44P, Sch name = EXP-IO16_P# NET "VHDCIIO1<16>" LOC = "T6"; # Bank = 2, Pin name = IO_L45P, Sch name = EXP-IO17_P# NET "VHDCIIO1<17>" LOC = "R7"; # Bank = 2, Pin name = IO_L46P, Sch name = EXP-IO18_P# NET "VHDCIIO1<18>" LOC = "N6"; # Bank = 2, Pin name = *IO_L47P, Sch name = EXP-IO19_P# NET "VHDCIIO1<19>" LOC = "U5"; # Bank = 2, Pin name = IO_49P_D3, Sch name = EXP-IO20_P# NET "VHDCIIO2<8>" LOC = "V11"; # Bank = 2, Pin name = IO_L23N, Sch name = EXP-IO9_N# NET "VHDCIIO2<9>" LOC = "T10"; # Bank = 2, Pin name = IO_L29N_GCLK2, Sch name = EXP-IO10_N# NET "VHDCIIO2<10>" LOC = "V10"; # Bank = 2, Pin name = IO_L30N_GCLK0_USERCCLK, Sch name = EXP-IO11_N# NET "VHDCIIO2<11>" LOC = "T8"; # Bank = 2, Pin name = IO_L31N_GCLK30_D15, Sch name = EXP-IO12_N# NET "VHDCIIO2<12>" LOC = "N8"; # Bank = 2, Pin name = *IO_L40N, Sch name = EXP-IO13_N# NET "VHDCIIO2<13>" LOC = "V8"; # Bank = 2, Pin name = IO_L41N_VREF, Sch name = EXP-IO14_N# NET "VHDCIIO2<14>" LOC = "V7"; # Bank = 2, Pin name = IO_L43N, Sch name = EXP-IO15_N# NET "VHDCIIO2<15>" LOC = "P8"; # Bank = 2, Pin name = *IO_L44N, Sch name = EXP-IO16_N# NET "VHDCIIO2<16>" LOC = "V6"; # Bank = 2, Pin name = IO_L45N, Sch name = EXP-IO17_N# NET "VHDCIIO2<17>" LOC = "T7"; # Bank = 2, Pin name = IO_L46N, Sch name = EXP-IO18_N# NET "VHDCIIO2<18>" LOC = "P7"; # Bank = 2, Pin name = *IO_L47N, Sch name = EXP-IO19_N# NET "VHDCIIO2<19>" LOC = "V5"; # Bank = 2, Pin name = IO_49N_D4, Sch name = EXP-IO20_N# USB UART Connector# NET "UartRx" LOC = "A16"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD# NET "UartTx" LOC = "B16"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD