Subversion Repositories spi_master_slave

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      <outfile xil_pn:name="spi_master_atlys_top.drc"/>
      <outfile xil_pn:name="spi_master_atlys_top.ut"/>
      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
      <outfile xil_pn:name="webtalk.log"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
    </transform>
    <transform xil_pn:end_ts="1314586528" xil_pn:in_ck="-5988982649231273448" xil_pn:name="TRAN_postParSimModel" xil_pn:prop_ck="5598892574118791338" xil_pn:start_ts="1314586521">
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      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="InputChanged"/>
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      <outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.nlf"/>
      <outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.sdf"/>
      <outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1314584667" xil_pn:in_ck="-7029858421675272663" xil_pn:name="TRAN_copyPost-ParAbstractToPreSimulation" xil_pn:start_ts="1314584667">
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      <status xil_pn:value="ReadyToRun"/>
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      <status xil_pn:value="OutOfDateForPredecessor"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.sdf"/>
      <outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.vhd"/>
      <outfile xil_pn:name="spi_master_atlys_test.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1314584674" xil_pn:in_ck="9156795390127265392" xil_pn:name="TRAN_ISimulatePostPlace&amp;RouteModelRunFuse" xil_pn:prop_ck="4831401045093024940" xil_pn:start_ts="1314584667">
      <status xil_pn:value="SuccessfullyRun"/>
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      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="OutOfDateForPredecessor"/>
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      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="OutputChanged"/>
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      <outfile xil_pn:name="isim.log"/>
      <outfile xil_pn:name="testbench_isim_par.exe"/>
      <outfile xil_pn:name="testbench_par.prj"/>
      <outfile xil_pn:name="xilinxsim.ini"/>
    </transform>
    <transform xil_pn:end_ts="1314584674" xil_pn:in_ck="7130759509275896515" xil_pn:name="TRAN_ISimulatePostPlace&amp;RouteModel" xil_pn:prop_ck="-3956543683666394319" xil_pn:start_ts="1314584674">
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      <status xil_pn:value="OutOfDateForPredecessor"/>
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      <outfile xil_pn:name="isim.cmd"/>
      <outfile xil_pn:name="isim.log"/>
      <outfile xil_pn:name="testbench_isim_par.wdb"/>
    </transform>
    <transform xil_pn:end_ts="1314587335" xil_pn:in_ck="-2449764723691034553" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1314587329">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
      <outfile xil_pn:name="spi_master_atlys_top.twr"/>
      <outfile xil_pn:name="spi_master_atlys_top.twx"/>
    </transform>
    <transform xil_pn:end_ts="1314586520" xil_pn:in_ck="-2655376893977800779" xil_pn:name="TRAN_postMapSimModel" xil_pn:prop_ck="-119654110892640368" xil_pn:start_ts="1314586513">
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      <status xil_pn:value="WarningsGenerated"/>
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      <outfile xil_pn:name="netgen/map/spi_master_atlys_top_map.nlf"/>
      <outfile xil_pn:name="netgen/map/spi_master_atlys_top_map.sdf"/>
      <outfile xil_pn:name="netgen/map/spi_master_atlys_top_map.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1314586512" xil_pn:in_ck="-5988982649231273316" xil_pn:name="TRAN_postXlateSimModel" xil_pn:prop_ck="4032524037721565697" xil_pn:start_ts="1314586510">
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      <status xil_pn:value="ReadyToRun"/>
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      <outfile xil_pn:name="netgen/translate/spi_master_atlys_top_translate.nlf"/>
      <outfile xil_pn:name="netgen/translate/spi_master_atlys_top_translate.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1314584431" xil_pn:in_ck="1721521412391114385" xil_pn:name="TRAN_copyPost-TranslateAbstractToPreSimulation" xil_pn:start_ts="1314584431">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
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      <status xil_pn:value="OutOfDateForPredecessor"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="netgen/translate/spi_master_atlys_top_translate.vhd"/>
      <outfile xil_pn:name="spi_master_atlys_test.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1314584434" xil_pn:in_ck="1721521412391114385" xil_pn:name="TRAN_ISimulatePostTranslateModelRunFuse" xil_pn:prop_ck="4831401045093024940" xil_pn:start_ts="1314584431">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
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      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="fuse.log"/>
      <outfile xil_pn:name="isim"/>
      <outfile xil_pn:name="isim.log"/>
      <outfile xil_pn:name="testbench_isim_translate.exe"/>
      <outfile xil_pn:name="testbench_translate.prj"/>
      <outfile xil_pn:name="xilinxsim.ini"/>
    </transform>
    <transform xil_pn:end_ts="1314584435" xil_pn:in_ck="-2373432107787769551" xil_pn:name="TRAN_ISimulatePostTranslateModel" xil_pn:prop_ck="-8441040086216995160" xil_pn:start_ts="1314584434">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForPredecessor"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="isim.cmd"/>
      <outfile xil_pn:name="isim.log"/>
      <outfile xil_pn:name="testbench_isim_translate.wdb"/>
    </transform>
    <transform xil_pn:end_ts="1314586509" xil_pn:in_ck="-5988982649231273317" xil_pn:name="TRAN_postSynthesisSimModel" xil_pn:prop_ck="367852130939253958" xil_pn:start_ts="1314586508">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="InputChanged"/>
      <outfile xil_pn:name="netgen"/>
      <outfile xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.nlf"/>
      <outfile xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.vhd"/>
    </transform>
  </transforms>

</generated_project>