Subversion Repositories spi_slave

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##
## Name     : opb_spi_slave
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN opb_spi_slave

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER


## Bus Interfaces
BUS_INTERFACE BUS = MSOPB, BUS_TYPE = MASTER_SLAVE, BUS_STD = OPB

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x80 
PARAMETER C_HIGHADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_USER_ID_CODE = 0, DT = INTEGER
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = MSOPB
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = MSOPB
PARAMETER C_FAMILY = virtex-4, DT = STRING
PARAMETER C_SR_WIDTH = 8, DT = INTEGER
PARAMETER C_MSB_FIRST = true, DT = BOOLEAN
PARAMETER C_CPOL = 0, DT = INTEGER
PARAMETER C_PHA = 0, DT = INTEGER
PARAMETER C_FIFO_SIZE_WIDTH = 7, DT = INTEGER
PARAMETER C_DMA_EN = true, DT = BOOLEAN
PARAMETER C_CRC_EN = true, DT = BOOLEAN

## Ports
PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB
PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB
PORT OPB_Clk = "", DIR = I, BUS = MSOPB, SIGIS = CLK
PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB
PORT OPB_RNW = OPB_RNW, DIR = I, BUS = MSOPB
PORT OPB_Rst = OPB_Rst, DIR = I, BUS = MSOPB, SIGIS = RST
PORT OPB_select = OPB_select, DIR = I, BUS = MSOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = MSOPB
PORT Sln_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB
PORT Sln_errAck = Sl_errAck, DIR = O, BUS = MSOPB
PORT Sln_retry = Sl_retry, DIR = O, BUS = MSOPB
PORT Sln_toutSup = Sl_toutSup, DIR = O, BUS = MSOPB
PORT Sln_xferAck = Sl_xferAck, DIR = O, BUS = MSOPB
PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB
PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB
PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB
PORT M_DBus = M_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB
PORT M_request = M_request, DIR = O, BUS = MSOPB
PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB
PORT M_select = M_select, DIR = O, BUS = MSOPB
PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB
PORT MOPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB
PORT MOPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB
PORT MOPB_retry = OPB_retry, DIR = I, BUS = MSOPB
PORT MOPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB
PORT MOPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB
PORT sclk = "", DIR = I, SIGIS = CLK
PORT ss_n = "", DIR = I
PORT mosi = "", DIR = I
PORT miso = "", DIR = IO, THREE_STATE = TRUE, TRI_I = miso_I, TRI_O = miso_O, TRI_T = miso_T
PORT miso_o = "", DIR = O
PORT miso_i = "", DIR = I
PORT miso_t = "", DIR = O
PORT opb_irq = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH

END