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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1424458772868 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition " "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1424458772868 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 20 13:59:32 2015 " "Processing started: Fri Feb 20 13:59:32 2015" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1424458772868 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1424458772868 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sport_top -c sport_top " "Command: quartus_map --read_settings_files=on --write_settings_files=off sport_top -c sport_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1424458772868 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1424458773321 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "wb_interface.v(208) " "Verilog HDL warning at wb_interface.v(208): extended using \"x\" or \"z\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 208 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1424458773414 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/jeffa/desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/jeffa/desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 wb_interface_sport " "Found entity 1: wb_interface_sport" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 57 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424458773414 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1424458773414 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "txFS txfs sport_top.v(158) " "Verilog HDL Declaration information at sport_top.v(158): object \"txFS\" differs only in case from object \"txfs\" in the same scope" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 158 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1424458773430 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rxFS rxfs sport_top.v(155) " "Verilog HDL Declaration information at sport_top.v(155): object \"rxFS\" differs only in case from object \"rxfs\" in the same scope" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 155 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1424458773430 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/jeffa/desktop/rtl/sport/trunk/rtl/verilog/sport_top.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/jeffa/desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 sport_top " "Found entity 1: sport_top" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 60 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424458773430 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1424458773430 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/jeffa/desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v 0 0 " "Found 0 design units, including 0 entities, in source file /users/jeffa/desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "fifos.v(223) " "Verilog HDL warning at fifos.v(223): extended using \"x\" or \"z\"" {  } { { "../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v" 223 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/jeffa/desktop/rtl/sport/trunk/rtl/verilog/fifos.v 3 3 " "Found 3 design units, including 3 entities, in source file /users/jeffa/desktop/rtl/sport/trunk/rtl/verilog/fifos.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_sport " "Found entity 1: fifo_sport" {  } { { "../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v" 71 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424458773446 ""} { "Info" "ISGN_ENTITY_NAME" "2 custom_fifo_dp " "Found entity 2: custom_fifo_dp" {  } { { "../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v" 130 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424458773446 ""} { "Info" "ISGN_ENTITY_NAME" "3 mem_byte " "Found entity 3: mem_byte" {  } { { "../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v" 204 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424458773446 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rst_o wb_interface.v(143) " "Verilog HDL Implicit Net warning at wb_interface.v(143): created implicit net for \"rst_o\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 143 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rst wb_interface.v(144) " "Verilog HDL Implicit Net warning at wb_interface.v(144): created implicit net for \"rst\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 144 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ack_o wb_interface.v(146) " "Verilog HDL Implicit Net warning at wb_interface.v(146): created implicit net for \"ack_o\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 146 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "stb_o wb_interface.v(147) " "Verilog HDL Implicit Net warning at wb_interface.v(147): created implicit net for \"stb_o\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 147 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "cyc_o wb_interface.v(148) " "Verilog HDL Implicit Net warning at wb_interface.v(148): created implicit net for \"cyc_o\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 148 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "we_o wb_interface.v(149) " "Verilog HDL Implicit Net warning at wb_interface.v(149): created implicit net for \"we_o\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 149 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "clk_o wb_interface.v(172) " "Verilog HDL Implicit Net warning at wb_interface.v(172): created implicit net for \"clk_o\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 172 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "lock_cfg_rx wb_interface.v(176) " "Verilog HDL Implicit Net warning at wb_interface.v(176): created implicit net for \"lock_cfg_rx\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 176 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "lock_cfg_tx wb_interface.v(177) " "Verilog HDL Implicit Net warning at wb_interface.v(177): created implicit net for \"lock_cfg_tx\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 177 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wb_dat_rdbk wb_interface.v(207) " "Verilog HDL Implicit Net warning at wb_interface.v(207): created implicit net for \"wb_dat_rdbk\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 207 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wb_wr_en wb_interface.v(213) " "Verilog HDL Implicit Net warning at wb_interface.v(213): created implicit net for \"wb_wr_en\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 213 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wb_rd_en wb_interface.v(214) " "Verilog HDL Implicit Net warning at wb_interface.v(214): created implicit net for \"wb_rd_en\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 214 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RFSx sport_top.v(166) " "Verilog HDL Implicit Net warning at sport_top.v(166): created implicit net for \"RFSx\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 166 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wb_data_i sport_top.v(321) " "Verilog HDL Implicit Net warning at sport_top.v(321): created implicit net for \"wb_data_i\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 321 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773446 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wb_wr_en sport_top.v(321) " "Verilog HDL Implicit Net warning at sport_top.v(321): created implicit net for \"wb_wr_en\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 321 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773461 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wei_rd_en sport_top.v(321) " "Verilog HDL Implicit Net warning at sport_top.v(321): created implicit net for \"wei_rd_en\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 321 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773461 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "fullwrite sport_top.v(321) " "Verilog HDL Implicit Net warning at sport_top.v(321): created implicit net for \"fullwrite\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 321 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773461 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "emptywrite sport_top.v(321) " "Verilog HDL Implicit Net warning at sport_top.v(321): created implicit net for \"emptywrite\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 321 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773461 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "data_o sport_top.v(322) " "Verilog HDL Implicit Net warning at sport_top.v(322): created implicit net for \"data_o\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 322 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773461 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "fullread sport_top.v(322) " "Verilog HDL Implicit Net warning at sport_top.v(322): created implicit net for \"fullread\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 322 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773461 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "emptyread sport_top.v(322) " "Verilog HDL Implicit Net warning at sport_top.v(322): created implicit net for \"emptyread\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 322 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773461 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wb_sel_i sport_top.v(400) " "Verilog HDL Implicit Net warning at sport_top.v(400): created implicit net for \"wb_sel_i\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 400 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773461 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wb_cti_i sport_top.v(401) " "Verilog HDL Implicit Net warning at sport_top.v(401): created implicit net for \"wb_cti_i\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 401 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458773461 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "sport_top " "Elaborating entity \"sport_top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1424458773492 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RFSx sport_top.v(166) " "Verilog HDL or VHDL warning at sport_top.v(166): object \"RFSx\" assigned a value but never read" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 166 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rxstate sport_top.v(119) " "Verilog HDL or VHDL warning at sport_top.v(119): object \"rxstate\" assigned a value but never read" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 119 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "rxsecEn_rx sport_top.v(145) " "Verilog HDL warning at sport_top.v(145): object rxsecEn_rx used but never assigned" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 145 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "rxlateFS_earlyFSn_rx sport_top.v(146) " "Verilog HDL warning at sport_top.v(146): object rxlateFS_earlyFSn_rx used but never assigned" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 146 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "txsecEn_tx sport_top.v(147) " "Verilog HDL warning at sport_top.v(147): object txsecEn_tx used but never assigned" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 147 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "txlateFS_earlyFSn_tx sport_top.v(148) " "Verilog HDL warning at sport_top.v(148): object txlateFS_earlyFSn_tx used but never assigned" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 148 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rxidle sport_top.v(153) " "Verilog HDL or VHDL warning at sport_top.v(153): object \"rxidle\" assigned a value but never read" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 153 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "txidle sport_top.v(156) " "Verilog HDL or VHDL warning at sport_top.v(156): object \"txidle\" assigned a value but never read" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 156 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 sport_top.v(216) " "Verilog HDL assignment warning at sport_top.v(216): truncated value with size 32 to match size of target (5)" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 216 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 sport_top.v(217) " "Verilog HDL assignment warning at sport_top.v(217): truncated value with size 32 to match size of target (5)" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 217 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 sport_top.v(225) " "Verilog HDL assignment warning at sport_top.v(225): truncated value with size 32 to match size of target (10)" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 225 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 sport_top.v(226) " "Verilog HDL assignment warning at sport_top.v(226): truncated value with size 32 to match size of target (10)" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 226 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 sport_top.v(277) " "Verilog HDL assignment warning at sport_top.v(277): truncated value with size 32 to match size of target (5)" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 277 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 sport_top.v(278) " "Verilog HDL assignment warning at sport_top.v(278): truncated value with size 32 to match size of target (5)" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 278 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773492 "|sport_top"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 sport_top.v(286) " "Verilog HDL assignment warning at sport_top.v(286): truncated value with size 32 to match size of target (10)" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 286 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773508 "|sport_top"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 sport_top.v(287) " "Verilog HDL assignment warning at sport_top.v(287): truncated value with size 32 to match size of target (10)" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 287 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773508 "|sport_top"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "rxsecEn_rx 0 sport_top.v(145) " "Net \"rxsecEn_rx\" at sport_top.v(145) has no driver or initial value, using a default initial value '0'" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 145 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1424458773508 "|sport_top"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "txsecEn_tx 0 sport_top.v(147) " "Net \"txsecEn_tx\" at sport_top.v(147) has no driver or initial value, using a default initial value '0'" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 147 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1424458773508 "|sport_top"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "txlateFS_earlyFSn_tx 0 sport_top.v(148) " "Net \"txlateFS_earlyFSn_tx\" at sport_top.v(148) has no driver or initial value, using a default initial value '0'" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 148 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1424458773508 "|sport_top"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "TRSx sport_top.v(95) " "Output port \"TRSx\" at sport_top.v(95) has no driver" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 95 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1424458773508 "|sport_top"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_sport fifo_sport:datafifowrite " "Elaborating entity \"fifo_sport\" for hierarchy \"fifo_sport:datafifowrite\"" {  } { { "../../rtl/verilog/sport_top.v" "datafifowrite" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 321 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458773508 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custom_fifo_dp fifo_sport:datafifowrite\|custom_fifo_dp:custom_fifo_dp5 " "Elaborating entity \"custom_fifo_dp\" for hierarchy \"fifo_sport:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\"" {  } { { "../../rtl/verilog/fifos.v" "custom_fifo_dp5" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v" 112 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458773508 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mem_byte fifo_sport:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte:mem\[0\].mem_byte " "Elaborating entity \"mem_byte\" for hierarchy \"fifo_sport:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte:mem\[0\].mem_byte\"" {  } { { "../../rtl/verilog/fifos.v" "mem\[0\].mem_byte" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v" 161 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458773508 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "wb_interface_sport wb_interface_sport:wb_interface " "Elaborating entity \"wb_interface_sport\" for hierarchy \"wb_interface_sport:wb_interface\"" {  } { { "../../rtl/verilog/sport_top.v" "wb_interface" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 403 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458773602 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rst_o wb_interface.v(143) " "Verilog HDL or VHDL warning at wb_interface.v(143): object \"rst_o\" assigned a value but never read" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 143 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ack_o wb_interface.v(146) " "Verilog HDL or VHDL warning at wb_interface.v(146): object \"ack_o\" assigned a value but never read" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 146 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "stb_o wb_interface.v(147) " "Verilog HDL or VHDL warning at wb_interface.v(147): object \"stb_o\" assigned a value but never read" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 147 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cyc_o wb_interface.v(148) " "Verilog HDL or VHDL warning at wb_interface.v(148): object \"cyc_o\" assigned a value but never read" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 148 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "we_o wb_interface.v(149) " "Verilog HDL or VHDL warning at wb_interface.v(149): object \"we_o\" assigned a value but never read" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 149 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "clk_o wb_interface.v(172) " "Verilog HDL or VHDL warning at wb_interface.v(172): object \"clk_o\" assigned a value but never read" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 172 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "wb_wr_en wb_interface.v(213) " "Verilog HDL or VHDL warning at wb_interface.v(213): object \"wb_wr_en\" assigned a value but never read" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 213 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "wb_rd_en wb_interface.v(214) " "Verilog HDL or VHDL warning at wb_interface.v(214): object \"wb_rd_en\" assigned a value but never read" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 214 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "full wb_interface.v(135) " "Verilog HDL warning at wb_interface.v(135): object full used but never assigned" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 135 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 1 wb_interface.v(158) " "Verilog HDL assignment warning at wb_interface.v(158): truncated value with size 6 to match size of target (1)" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 158 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 wb_interface.v(207) " "Verilog HDL assignment warning at wb_interface.v(207): truncated value with size 32 to match size of target (1)" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 207 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "full 0 wb_interface.v(135) " "Net \"full\" at wb_interface.v(135) has no driver or initial value, using a default initial value '0'" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 135 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1424458773602 "|sport_top|wb_interface_sport:wb_interface"}
{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "wb_data_i " "Net \"wb_data_i\" is missing source, defaulting to GND" {  } { { "../../rtl/verilog/sport_top.v" "wb_data_i" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 321 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1424458773711 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "wb_wr_en " "Net \"wb_wr_en\" is missing source, defaulting to GND" {  } { { "../../rtl/verilog/sport_top.v" "wb_wr_en" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 321 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1424458773711 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "wei_rd_en " "Net \"wei_rd_en\" is missing source, defaulting to GND" {  } { { "../../rtl/verilog/sport_top.v" "wei_rd_en" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 321 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1424458773711 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "rst " "Net \"rst\" is missing source, defaulting to GND" {  } { { "../../rtl/verilog/sport_top.v" "rst" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 116 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1424458773711 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "clk " "Net \"clk\" is missing source, defaulting to GND" {  } { { "../../rtl/verilog/sport_top.v" "clk" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 120 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1424458773711 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Quartus II" 0 -1 1424458773711 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1424458774272 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DTxPRI GND " "Pin \"DTxPRI\" is stuck at GND" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 88 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1424458774319 "|sport_top|DTxPRI"} { "Warning" "WMLS_MLS_STUCK_PIN" "DTxSEC GND " "Pin \"DTxSEC\" is stuck at GND" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 89 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1424458774319 "|sport_top|DTxSEC"} { "Warning" "WMLS_MLS_STUCK_PIN" "TRSx GND " "Pin \"TRSx\" is stuck at GND" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 95 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1424458774319 "|sport_top|TRSx"} { "Warning" "WMLS_MLS_STUCK_PIN" "wb_err_o GND " "Pin \"wb_err_o\" is stuck at GND" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 107 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1424458774319 "|sport_top|wb_err_o"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1424458774319 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1424458774397 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "364 " "364 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1424458774803 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/output_files/sport_top.map.smsg " "Generated suppressed messages file C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/output_files/sport_top.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1424458774865 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1424458775068 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775068 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "15 " "Design contains 15 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "DRxPRI " "No output dependent on input pin \"DRxPRI\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 92 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|DRxPRI"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "DRxSEC " "No output dependent on input pin \"DRxSEC\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 93 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|DRxSEC"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[18\] " "No output dependent on input pin \"wb_dat_i\[18\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[18]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[19\] " "No output dependent on input pin \"wb_dat_i\[19\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[19]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[21\] " "No output dependent on input pin \"wb_dat_i\[21\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[21]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[22\] " "No output dependent on input pin \"wb_dat_i\[22\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[22]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[23\] " "No output dependent on input pin \"wb_dat_i\[23\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[23]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[24\] " "No output dependent on input pin \"wb_dat_i\[24\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[24]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[25\] " "No output dependent on input pin \"wb_dat_i\[25\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[25]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[26\] " "No output dependent on input pin \"wb_dat_i\[26\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[26]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[27\] " "No output dependent on input pin \"wb_dat_i\[27\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[27]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[28\] " "No output dependent on input pin \"wb_dat_i\[28\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[28]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[29\] " "No output dependent on input pin \"wb_dat_i\[29\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[29]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[30\] " "No output dependent on input pin \"wb_dat_i\[30\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[30]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_dat_i\[31\] " "No output dependent on input pin \"wb_dat_i\[31\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424458775177 "|sport_top|wb_dat_i[31]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1424458775177 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "150 " "Implemented 150 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "47 " "Implemented 47 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1424458775177 ""} { "Info" "ICUT_CUT_TM_OPINS" "42 " "Implemented 42 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1424458775177 ""} { "Info" "ICUT_CUT_TM_LCELLS" "61 " "Implemented 61 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1424458775177 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1424458775177 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 84 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 84 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "583 " "Peak virtual memory: 583 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1424458775240 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 20 13:59:35 2015 " "Processing ended: Fri Feb 20 13:59:35 2015" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1424458775240 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1424458775240 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1424458775240 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1424458775240 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Flow 0 s 84 s " "Quartus II Flow was successful. 0 errors, 84 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1424458776129 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1424458777611 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Design Assistant Quartus II 64-Bit " "Running Quartus II 64-Bit Design Assistant" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition " "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1424458777611 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 20 13:59:37 2015 " "Processing started: Fri Feb 20 13:59:37 2015" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1424458777611 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Assistant" 0 -1 1424458777611 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_drc --read_settings_files=off --write_settings_files=off sport_top -c sport_top " "Command: quartus_drc --read_settings_files=off --write_settings_files=off sport_top -c sport_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Assistant" 0 -1 1424458777611 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "sport_top EP4CGX15BF14C6 " "Selected device EP4CGX15BF14C6 for design \"sport_top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Design Assistant" 0 -1 1424458777673 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sport_top.sdc " "Synopsys Design Constraints File file not found: 'sport_top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Design Assistant" 0 -1 1424458778500 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Design Assistant" 0 -1 1424458778500 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Design Assistant" 0 -1 1424458778516 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Design Assistant" 0 -1 1424458778516 ""}
{ "Critical Warning" "WDRC_NO_SYNZER_IN_ASYNC_CLK_DOMAIN" "Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains 2 16 " "(High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 16 asynchronous clock domain interface structure(s) related to this rule." { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[7\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[7\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 202 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[6\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[6\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 203 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[4\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[4\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 205 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[5\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[5\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 204 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[2\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[2\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 207 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[3\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[3\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 206 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[1\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[1\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 208 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[0\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[0\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 209 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[9\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[9\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 200 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[8\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[8\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 201 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[13\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[13\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 196 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[12\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[12\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 197 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[11\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[11\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 198 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[10\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[10\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 199 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[14\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[14\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 195 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[16\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[16\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 194 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""}  } {  } 1 308060 "(High) %1!s!. (Value defined:%2!d!). Found %3!d! asynchronous clock domain interface structure(s) related to this rule." 0 0 "Design Assistant" 0 -1 1424458778672 ""}
{ "Critical Warning" "WDRC_IMPROPER_SYNZER_IN_ASYNC_CLK_DOMAIN" "Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains 2 15 " "(High) Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 15 asynchronous clock domain interface structure(s) related to this rule." { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[7\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[7\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 202 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[6\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[6\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 203 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[4\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[4\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 205 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[5\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[5\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 204 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[2\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[2\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 207 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[3\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[3\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 206 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[1\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[1\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 208 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[0\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[0\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 209 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[9\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[9\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 200 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[8\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[8\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 201 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[13\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[13\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 196 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[12\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[12\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 197 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[11\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[11\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 198 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[10\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[10\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 199 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[14\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[14\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 195 9684 10422 0}  }  } }  } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""}  } {  } 1 308067 "(High) %1!s!. (Value defined:%2!d!). Found %3!d! asynchronous clock domain interface structure(s) related to this rule." 0 0 "Design Assistant" 0 -1 1424458778672 ""}
{ "Warning" "WDRC_EXTERNAL_RESET" "Rule R102: External reset signals should be synchronized using two cascaded registers 1 " "(Medium) Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule." { { "Warning" "WDRC_NODES_WARNING" " wb_rst_i " "Node  \"wb_rst_i\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 99 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 179 9684 10422 0}  }  } }  } 0 308010 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""}  } {  } 0 308023 "(Medium) %1!s!. Found %2!d! node(s) related to this rule." 0 0 "Design Assistant" 0 -1 1424458778672 ""}
{ "Warning" "WDRC_SYNZER_IN_ALL_SIGNAL_BTW_ASYNC_CLK_DOMAIN" "Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain 2 1 " "(Medium) Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain. (Value defined:2). Found 1 asynchronous clock domain interface structure(s) related to this rule." { { "Warning" "WDRC_NODES_WARNING" " wb_interface_sport:wb_interface\|txreg (Bus) " "Node  \"wb_interface_sport:wb_interface\|txreg (Bus)\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 202 9684 10422 0}  }  } }  } 0 308010 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""}  } {  } 0 308071 "(Medium) %1!s!. (Value defined:%2!d!). Found %3!d! asynchronous clock domain interface structure(s) related to this rule." 0 0 "Design Assistant" 0 -1 1424458778687 ""}
{ "Info" "IDRC_HIGH_FANOUT" "Rule T101: Nodes with more than the specified number of fan-outs 30 1 " "(Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 1 node(s) with highest fan-out." { { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|wb_dat_o~31 " "Node  \"wb_interface_sport:wb_interface\|wb_dat_o~31\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 107 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 256 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""}  } {  } 0 308046 "(Information) %1!s!. (Value defined:%2!d!). Found %3!d! node(s) with highest fan-out." 0 0 "Design Assistant" 0 -1 1424458778687 ""}
{ "Info" "IDRC_TOP_FANOUT" "Rule T102: Top nodes with the highest number of fan-outs 50 50 " "(Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out." { { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|wb_dat_o~31 " "Node  \"wb_interface_sport:wb_interface\|wb_dat_o~31\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 107 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 256 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|always4~1 " "Node  \"wb_interface_sport:wb_interface\|always4~1\"" {  } { { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 251 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " state.010 " "Node  \"state.010\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 118 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 231 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txsampleCnt_tx\[1\] " "Node  \"txsampleCnt_tx\[1\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 276 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 219 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txsampleCnt_tx\[0\] " "Node  \"txsampleCnt_tx\[0\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 276 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 220 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[4\] " "Node  \"txpacketCnt_tx\[4\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 226 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|Equal1~0 " "Node  \"wb_interface_sport:wb_interface\|Equal1~0\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 207 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 249 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[2\] " "Node  \"txpacketCnt_tx\[2\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 228 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|always3~1 " "Node  \"wb_interface_sport:wb_interface\|always3~1\"" {  } { { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 253 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[3\] " "Node  \"txpacketCnt_tx\[3\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 227 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[7\] " "Node  \"txpacketCnt_tx\[7\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 223 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[8\] " "Node  \"txpacketCnt_tx\[8\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 222 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal0~1 " "Node  \"Equal0~1\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 265 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 261 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal1~5 " "Node  \"Equal1~5\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 266 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 269 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[5\] " "Node  \"txpacketCnt_tx\[5\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 225 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Selector1~0 " "Node  \"Selector1~0\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 252 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 263 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[6\] " "Node  \"txpacketCnt_tx\[6\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 224 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " state.011 " "Node  \"state.011\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 118 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 237 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal1~0 " "Node  \"Equal1~0\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 266 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 264 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal0~2 " "Node  \"Equal0~2\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 265 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 262 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " tx_start_tx " "Node  \"tx_start_tx\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 152 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 239 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal0~0 " "Node  \"Equal0~0\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 265 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 260 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " state.001 " "Node  \"state.001\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 118 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 230 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|txreg\[0\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[0\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 209 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[9\] " "Node  \"txpacketCnt_tx\[9\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 221 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_dat_i\[10\] " "Node  \"wb_dat_i\[10\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 107 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|txreg\[3\] " "Node  \"wb_interface_sport:wb_interface\|txreg\[3\]\"" {  } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 206 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Selector1~1 " "Node  \"Selector1~1\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 252 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 273 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_rst_i " "Node  \"wb_rst_i\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 99 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 179 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_dat_i\[13\] " "Node  \"wb_dat_i\[13\]\"" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 110 9684 10422 0}  }  } }  } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_REPORT_TRUNCATE_MESSAGE" "30 " "Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated." {  } {  } 0 308002 "Truncated list of Design Assistant messages to %1!d! messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated." 0 0 "Quartus II" 0 -1 1424458778687 ""}  } {  } 0 308044 "(Information) %1!s!. (Value defined:%2!d!). Found %3!d! node(s) with highest fan-out." 0 0 "Design Assistant" 0 -1 1424458778687 ""}
{ "Info" "IDRC_REPORT_HEALTH_POST_SYNTHESIS" "51 33 " "Design Assistant information: finished post-synthesis analysis of current design -- generated 51 information messages and 33 warning messages" {  } {  } 2 308006 "Design Assistant information: finished post-synthesis analysis of current design -- generated %1!d! information messages and %2!d! warning messages" 0 0 "Design Assistant" 0 -1 1424458778687 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Design Assistant 0 s 38 s Quartus II 64-Bit " "Quartus II 64-Bit Design Assistant was successful. 0 errors, 38 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "474 " "Peak virtual memory: 474 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1424458778765 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 20 13:59:38 2015 " "Processing ended: Fri Feb 20 13:59:38 2015" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1424458778765 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1424458778765 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1424458778765 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Assistant" 0 -1 1424458778765 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Flow 0 s 122 s " "Quartus II Flow was successful. 0 errors, 122 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Assistant" 0 -1 1424458779436 ""}