Subversion Repositories sport

{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1424458783539 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "sport_top EP4CGX15BF14C6 " "Selected device EP4CGX15BF14C6 for design \"sport_top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1424458783554 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1424458783601 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1424458783601 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1424458783601 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1424458783835 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX30BF14C6 " "Device EP4CGX30BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1424458783851 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX22BF14C6 " "Device EP4CGX22BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1424458783851 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1424458783851 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCEO~ N5 " "Pin ~ALTERA_NCEO~ is reserved at location N5" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCEO~ } } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 391 9684 10422 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1424458783851 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ A5 " "Pin ~ALTERA_DATA0~ is reserved at location A5" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 393 9684 10422 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1424458783851 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO~ B5 " "Pin ~ALTERA_ASDO~ is reserved at location B5" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO~ } } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 395 9684 10422 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1424458783851 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCSO~ C5 " "Pin ~ALTERA_NCSO~ is reserved at location C5" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCSO~ } } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 397 9684 10422 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1424458783851 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ A4 " "Pin ~ALTERA_DCLK~ is reserved at location A4" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 399 9684 10422 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1424458783851 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1424458783851 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1424458783851 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "88 89 " "No exact pin location assignment(s) for 88 pins of 89 total pins. For the list of the pins please refer to the Input Pins, Output Pins, and Bidir Pins tables in the Fitter report and look for the user pins whose location is assigned by Fitter." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of the pins please refer to the Input Pins, Output Pins, and Bidir Pins tables in the Fitter report and look for the user pins whose location is assigned by Fitter." 0 0 "Fitter" 0 -1 1424458784147 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "wb_clk_i~input (placed in PIN J7 (CLK13, DIFFCLK_7n, REFCLK0n)) " "Automatically promoted node wb_clk_i~input (placed in PIN J7 (CLK13, DIFFCLK_7n, REFCLK0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1424458784194 ""}  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 98 0 0 } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { wb_clk_i~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 358 9684 10422 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1424458784194 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "txclk~input (placed in PIN N7 (CLK15, DIFFCLK_6n)) " "Automatically promoted node txclk~input (placed in PIN N7 (CLK15, DIFFCLK_6n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1424458784194 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "TSCLKx~output " "Destination node TSCLKx~output" {  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 90 0 0 } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TSCLKx~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 332 9684 10422 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1424458784194 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1424458784194 ""}  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 113 0 0 } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { txclk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 355 9684 10422 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1424458784194 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "wb_rst_i~input (placed in PIN M7 (CLK14, DIFFCLK_6p)) " "Automatically promoted node wb_rst_i~input (placed in PIN M7 (CLK14, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1424458784194 ""}  } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 99 0 0 } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { wb_rst_i~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 359 9684 10422 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1424458784194 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "85 unused 2.5V 44 41 0 " "Number of I/O pins in group: 85 (unused VREF, 2.5V VCCIO, 44 input, 41 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1424458784210 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1424458784210 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1424458784210 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 2.5V 1 7 " "I/O bank number 3 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 1 1 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  1 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 2.5V 2 12 " "I/O bank number 4 does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 2.5V 0 12 " "I/O bank number 6 does not use VREF pins and has 2.5V VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 1 13 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used --  13 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 2.5V 0 5 " "I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 0 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1424458784210 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1424458784210 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "I/O bank details after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 2.5V 1 7 " "I/O bank number 3 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 1 1 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  1 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 2.5V 2 12 " "I/O bank number 4 does not use VREF pins and has 2.5V VCCIO pins. 2 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 2.5V 0 12 " "I/O bank number 6 does not use VREF pins and has 2.5V VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 1 13 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 1 total pin(s) used --  13 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 2.5V 0 5 " "I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 0 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1424458784210 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1424458784210 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1424458784210 ""}
{ "Error" "EFSAC_FSAC_IOSTD_CAPACITY_FAIL" "85 2.5 V 64 " "Can't place 85 pins with 2.5 V I/O standard because Fitter has only 64 such free pins available for general purpose I/O placement" {  } {  } 0 176205 "Can't place %1!d! pins with %2!s! I/O standard because Fitter has only %3!d! such free pins available for general purpose I/O placement" 0 0 "Fitter" 0 -1 1424458784210 ""}
{ "Error" "EFSAC_FSAC_FAIL_TO_PLACE_PIN" "" "Can't place pins due to device constraints" {  } {  } 0 176204 "Can't place pins due to device constraints" 0 0 "Fitter" 0 -1 1424458784210 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1424458784210 ""}
{ "Error" "EFITCC_FITCC_FAIL" "" "Can't fit design in device" {  } {  } 0 171000 "Can't fit design in device" 0 0 "Fitter" 0 -1 1424458784288 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV GX " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV GX Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "wb_clk_i 2.5 V J7 " "Pin wb_clk_i uses I/O standard 2.5 V at J7" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { wb_clk_i } } } { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 98 0 0 } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { wb_clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 178 9684 10422 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1424458784288 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1424458784288 ""}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DTxPRI GND " "Pin DTxPRI has GND driving its datain port" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { DTxPRI } } } { "c:/altera/14.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/14.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DTxPRI" } } } } { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 88 0 0 } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DTxPRI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 168 9684 10422 0}  }  } }  } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Quartus II" 0 -1 1424458784288 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DTxSEC GND " "Pin DTxSEC has GND driving its datain port" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { DTxSEC } } } { "c:/altera/14.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/14.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DTxSEC" } } } } { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 89 0 0 } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DTxSEC } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 169 9684 10422 0}  }  } }  } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Quartus II" 0 -1 1424458784288 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TRSx GND " "Pin TRSx has GND driving its datain port" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { TRSx } } } { "c:/altera/14.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/14.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TRSx" } } } } { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 95 0 0 } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TRSx } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 174 9684 10422 0}  }  } }  } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Quartus II" 0 -1 1424458784288 ""} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "wb_err_o GND " "Pin wb_err_o has GND driving its datain port" {  } { { "c:/altera/14.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/14.0/quartus/bin64/pin_planner.ppl" { wb_err_o } } } { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 107 0 0 } } { "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/14.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { wb_err_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 184 9684 10422 0}  }  } }  } 0 169070 "Pin %1!s! has %2!s! driving its datain port" 0 0 "Quartus II" 0 -1 1424458784288 ""}  } {  } 0 169069 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1424458784288 ""}
{ "Error" "EQEXE_ERROR_COUNT" "I/O Assignment Analysis 3 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit I/O Assignment Analysis was unsuccessful. 3 errors, 6 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "663 " "Peak virtual memory: 663 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1424458784459 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Feb 20 13:59:44 2015 " "Processing ended: Fri Feb 20 13:59:44 2015" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1424458784459 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1424458784459 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1424458784459 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1424458784459 ""}