URL
https://opencores.org/ocsvn/sport/sport/trunk
Subversion Repositories sport
[/] [sport/] [trunk/] [syn/] [xilinx/] [ise/] [sport_top/] [_xmsgs/] [par.xmsgs] - Rev 7
Compare with Previous | Blame | View Log
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DRxSEC_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">DRxPRI_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="info" file="Place" num="834" delta="new" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">42</arg> IOs, <arg fmt="%d" index="2">5</arg> are locked and <arg fmt="%d" index="3">37</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">2</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">2</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
</messages>