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[/] [sport/] [trunk/] [syn/] [xilinx/] [ise/] [sport_top/] [planAhead.ngc2edif.log] - Rev 7
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Release 14.7 - ngc2edif P.20131013 (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.Reading design sport_top.ngc ...WARNING:NetListWriters:298 - No output is written to sport_top.xncf, ignored.Processing design ...Preping design's networks ...Preping design's macros ...WARNING:NetListWriters:306 - Signal bus wb_interface/rxreg<20 : 0> on blocksport_top is not reconstructed, because there are some missing bus signals.WARNING:NetListWriters:306 - Signal bus wb_interface/txreg<20 : 0> on blocksport_top is not reconstructed, because there are some missing bus signals.finished :PrepWriting EDIF netlist file sport_top.edif ...ngc2edif: Total memory usage is 79372 kilobytesRelease 14.7 - ngc2edif P.20131013 (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.Reading design sport_top.ngc ...WARNING:NetListWriters:298 - No output is written to sport_top.xncf, ignored.Processing design ...Preping design's networks ...Preping design's macros ...WARNING:NetListWriters:306 - Signal bus wb_interface/rxreg<20 : 0> on blocksport_top is not reconstructed, because there are some missing bus signals.WARNING:NetListWriters:306 - Signal bus wb_interface/txreg<20 : 0> on blocksport_top is not reconstructed, because there are some missing bus signals.finished :PrepWriting EDIF netlist file sport_top.edif ...ngc2edif: Total memory usage is 79052 kilobytes