Subversion Repositories sport

****** PlanAhead v14.7 (64-bit)
  **** Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
source C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/pa.fromNetlist.tcl
# create_project -name sport_top -dir "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/planAhead_run_2" -part xc3s700anfgg484-4
# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
# set_property edif_top_file "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/sport_top.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top} }
# set_param project.pinAheadLayout  yes
# set_property target_constrs_file "sport_top.ucf" [current_fileset -constrset]
Adding file 'C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/sport_top.ucf' to fileset 'constrs_1'
# add_files [list {sport_top.ucf}] -fileset [get_property constrset [current_run]]
# link_design
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xc3s700anfgg484-4
Release 14.7 - ngc2edif P.20131013 (nt64)

Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

Reading design sport_top.ngc ...

WARNING:NetListWriters:298 - No output is written to sport_top.xncf, ignored.

Processing design ...

   Preping design's networks ...

   Preping design's macros ...

WARNING:NetListWriters:306 - Signal bus wb_interface/rxreg<20 : 0> on block

   sport_top is not reconstructed, because there are some missing bus signals.

WARNING:NetListWriters:306 - Signal bus wb_interface/txreg<20 : 0> on block

   sport_top is not reconstructed, because there are some missing bus signals.

  finished :Prep

Writing EDIF netlist file sport_top.edif ...

ngc2edif: Total memory usage is 79372 kilobytes



Parsing EDIF File [./planAhead_run_2/sport_top.data/cache/sport_top_ngc_zx.edif]
Finished Parsing EDIF File [./planAhead_run_2/sport_top.data/cache/sport_top_ngc_zx.edif]
INFO: [Designutils 20-910] Reading macro library C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3a/hd_int_macros.edn
Parsing EDIF File [C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3a/hd_int_macros.edn]
Finished Parsing EDIF File [C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3a/hd_int_macros.edn]
Loading clock regions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/xc3s700an/ClockRegion.xml
Loading clock buffers from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/xc3s700an/ClockBuffers.xml
Loading package from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/xc3s700an/fgg484/Package.xml
Loading io standards from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3a/IOStandards.xml
INFO: [Device 21-19] Loading pkg sso from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/xc3s700an/fgg484/SSORules.xml
Loading list of drcs for the architecture : C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3a/drc.xml
INFO: [Timing 38-77] Reading timing library C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/spartan3a-4.lib.
INFO: [Timing 38-34] Done reading timing library C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/spartan3a-4.lib.
Parsing UCF File [C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/sport_top.ucf]
Finished Parsing UCF File [C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/sport_top.ucf]
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Phase 0 | Netlist Checksum: 0b0d73e8
link_design: Time (s): elapsed = 00:00:15 . Memory (MB): peak = 561.336 ; gain = 138.750
startgroup
set_property package_pin A2 [get_ports DRxPRI]
endgroup
startgroup
set_property package_pin A3 [get_ports DRxSEC]
endgroup
startgroup
set_property package_pin A4 [get_ports DTxPRI]
endgroup
set_property package_pin "" [get_ports [list  DTxSEC]]
set_property package_pin "" [get_ports [list  RSCLKx]]
startgroup
set_property package_pin A5 [get_ports DTxSEC]
endgroup
startgroup
set_property package_pin A6 [get_ports RSCLKx]
endgroup
set_property package_pin "" [get_ports [list  rx_int]]
save_constraints
exit
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
INFO: [Common 17-206] Exiting PlanAhead at Fri Feb 20 14:04:22 2015...
INFO: [Common 17-83] Releasing license: PlanAhead