Subversion Repositories sport

Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

JEFFA-PC::  Fri Feb 20 14:09:00 2015

par -w -intstyle ise -ol high -t 1 sport_top_map.ncd sport_top.ncd
sport_top.pcf 


Constraints file: sport_top.pcf.
Loading device for application Rf_Device from file '3s700a.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
   "sport_top" is an NCD, version 3.2, device xc3s700an, package fgg484, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.42 2013-10-13".


Design Summary Report:

 Number of External IOBs                          76 out of 372    20%

   Number of External Input IOBs                 34

      Number of External Input IBUFs             34
        Number of LOCed External Input IBUFs      2 out of 34      5%


   Number of External Output IOBs                42

      Number of External Output IOBs             42
        Number of LOCed External Output IOBs      5 out of 42     11%


   Number of External Bidir IOBs                  0


   Number of BUFGMUXs                        3 out of 24     12%
   Number of Slices                         41 out of 5888    1%
      Number of SLICEMs                      0 out of 2944    0%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 5 secs 
Finished initial Timing Analysis.  REAL time: 5 secs 

WARNING:Par:288 - The signal DRxSEC_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DRxPRI_IBUF has no load.  PAR will not attempt to route this signal.

Starting Placer
Total REAL time at the beginning of Placer: 6 secs 
Total CPU  time at the beginning of Placer: 2 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:6b5992a5) REAL time: 8 secs 

Phase 2.7  Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 42 IOs, 5 are locked and 37 are not locked. If you would like
   to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
Phase 2.7  Design Feasibility Check (Checksum:6b5992a5) REAL time: 9 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:6b5992a5) REAL time: 9 secs 

Phase 4.2  Initial Clock and IO Placement
.....
Phase 4.2  Initial Clock and IO Placement (Checksum:a0a71119) REAL time: 12 secs 

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:a0a71119) REAL time: 12 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:a0a71119) REAL time: 12 secs 

Phase 7.3  Local Placement Optimization
......
Phase 7.3  Local Placement Optimization (Checksum:a69910d4) REAL time: 14 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:a69910d4) REAL time: 14 secs 

Phase 9.8  Global Placement
....
..
Phase 9.8  Global Placement (Checksum:f6127ce3) REAL time: 14 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:f6127ce3) REAL time: 14 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:f44e05d2) REAL time: 16 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:f44e05d2) REAL time: 16 secs 

Total REAL time to Placer completion: 16 secs 
Total CPU  time to Placer completion: 10 secs 
Writing design to file sport_top.ncd



Starting Router


Phase  1  : 308 unrouted;      REAL time: 21 secs 

Phase  2  : 277 unrouted;      REAL time: 21 secs 

Phase  3  : 38 unrouted;      REAL time: 21 secs 

Phase  4  : 38 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 22 secs 

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 22 secs 

Updating file: sport_top.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 22 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 22 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 22 secs 

Total REAL time to Router completion: 22 secs 
Total CPU time to Router completion: 15 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|      wb_clk_i_BUFGP |  BUFGMUX_X1Y1| No   |   13 |  0.053     |  1.090      |
+---------------------+--------------+------+------+------------+-------------+
|         TSCLKx_OBUF | BUFGMUX_X1Y10| No   |   13 |  0.076     |  1.070      |
+---------------------+--------------+------+------+------------+-------------+
|         RSCLKx_OBUF |  BUFGMUX_X1Y0| No   |    1 |  0.000     |  0.994      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 1 | SETUP       |     6.860ns|     3.140ns|       0|           0
  0 ns HIGH 50%                             | HOLD        |     1.912ns|            |       0|           0
                                            | MINLOWPULSE |     6.796ns|     3.204ns|       0|           0
----------------------------------------------------------------------------------------------------------
  TS_txclk = PERIOD TIMEGRP "txclk" 20 ns H | SETUP       |    15.365ns|     4.635ns|       0|           0
  IGH 50%                                   | HOLD        |     1.314ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  TS_rxclk = PERIOD TIMEGRP "rxclk" 20 ns H | MINPERIOD   |    18.398ns|     1.602ns|       0|           0
  IGH 50%                                   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 24 secs 
Total CPU time to PAR completion: 16 secs 

Peak Memory Usage:  357 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file sport_top.ncd



PAR done!