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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'sport_top'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s700an-fgg484-4 -cm area -ir off -pr
off -c 100 -o sport_top_map.ncd sport_top.ngd sport_top.pcf 
Target Device  : xc3s700an
Target Package : fgg484
Target Speed   : -4
Mapper Version : spartan3a -- $Revision: 1.55 $
Mapped Date    : Fri Feb 20 14:08:41 2015

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
WARNING:PhysDesignRules:367 - The signal <DRxSEC_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DRxPRI_IBUF> is incomplete. The signal
   does not drive any load pins in the design.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:            42 out of  11,776    1%
  Number of 4 input LUTs:                42 out of  11,776    1%
Logic Distribution:
  Number of occupied Slices:             41 out of   5,888    1%
    Number of Slices containing only related logic:      41 out of      41 100%
    Number of Slices containing unrelated logic:          0 out of      41   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:          51 out of  11,776    1%
    Number used as logic:                42
    Number used as a route-thru:          9

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 76 out of     372   20%
    IOB Flip Flops:                       2
  Number of BUFGMUXs:                     3 out of      24   12%

Average Fanout of Non-Clock Nets:                2.40

Peak Memory Usage:  342 MB
Total REAL time to MAP completion:  15 secs 
Total CPU time to MAP completion:   4 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "sport_top_map.mrp" for details.